Showing papers on "Switched capacitor published in 2006"

Analysis and Optimization of Switched-Capacitor DC-DC Converters

Abstract: Analysis methods are developed that fully determine a switched-capacitor (SC) DC-DC converter's steady-state performance through evaluation of its output impedance. The simple formulation developed permits optimization of the capacitor sizes to meet a constraint such as a total capacitance or total energy storage limit, and also permits optimization of the switch sizes subject to constraints on total switch conductances or total switch volt-ampere (V-A) products. These optimizations then permit comparison among the switched-capacitor topologies, and comparisons of SC converters with conventional magnetic-based DC-DC converter circuits, in the context of various application settings. Significantly, the performance (based on conduction loss) of a ladder-type converter is found to be superior to that of a conventional boost converter for medium to high conversion ratios

Comparator-based switched-capacitor circuits for scaled CMOS technologies

Abstract: A comparator-based switched-capacitor (CBSC) design method for sampled-data systems utilizes topologies similar to traditional opamp-based methods but relies on the detection of the virtual ground using a comparator instead of forcing it with feedback. A prototype 10b CBSC 1.5b/stage pipelined ADC is implemented in a 0.18mum CMOS process. The converter operates at 8MHz and consumes 2.5mW

Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies

Abstract: A comparator-based switched-capacitor circuit (CBSC) technique is presented for the design of analog and mixed-signal circuits in scaled CMOS technologies. The technique involves replacing the operational amplifier in a standard switched-capacitor circuit with a comparator and a current source. During charge transfer, the comparator detects the virtual ground condition in place of the opamp which normally forces the virtual ground condition. A prototype 1.5-bit/stage 10-bit 7.9-MS/s pipeline ADC was designed using the comparator-based switched-capacitor technique. The prototype ADC was implemented in 0.18-mum CMOS. It achieves an ENOB of 8.6 bits for a 3.8-MHz input signal and dissipates 2.5 mW

A Micropower Chopper-Stabilized Operational Amplifier Using a SC Notch Filter With Synchronous Integration Inside the Continuous-Time Signal Path

Abstract: A micropower chopper stabilized opamp is presented. The new topology incorporates a switched capacitor filter with synchronous integration inside the continuous time signal path virtually eliminating chopping noise. A three-stage amplifier with multipath nested Miller compensation is modified to incorporate chopping of the input stage, sinc filtering to notch any chopping ripple, and a compensation scheme to maintain an undistorted high-speed signal path. Characteristics of the amplifier presented include rail to rail input and output operating on supplies of 1.8 to 5.5 V over -40degC to 125degC. Quiescent supply current is 17 muA, input offset is 3 muV, input offset drift is 0.02 muV/degC, GBW is 350 kHz, and the chopping frequency is 125 kHz. Die area is 0.7 mm2 using a precision analog mixed-signal CMOS process combining low-noise 0.6-mum analog transistors with 0.3-mum digital CMOS capability

A Compact Switched-Capacitor Regulated Charge Pump Power Supply

Abstract: A CMOS switched-capacitor reference is combined with a switched-capacitor voltage doubling charge pump to produce a compact regulated 3.2-V power supply from an input that ranges from 1.8 to 3.5 V. It can supply up to 6 mA at minimum input. The switched-capacitor topology uses a single PN junction and could allow for inputs and outputs less than 1 V. The concept of constant frequency charge pump regulation is discussed, as is the theory behind stability, load regulation, and efficiency. Measured results from a 0.5-mum CMOS process are given

A New Approach to Reducing Output Ripple in Switched-Capacitor-Based Step-Down DC–DC Converters

Abstract: Rapidly dropping power supply voltages and tight voltage regulation requirements for integrated circuits challenges power supply designers. A novel interleaved discharging (ID) approach is presented to reduce the output ripple in step-down switched-capacitor (SC) dc-dc converters. Simulation and experimental results of a four-stage SC dc-dc converter show that the ID approach can reduce the output ripple by a factor of three. The proposed approach also improves the converter efficiency by 7%. The ID method provides flexibility in the design optimization of step-down SC dc-dc converters

Radio frequency tuner

Abstract: A radio frequency tuner comprises one or more tracking filters ahead of at least one frequency changer. A controller has a filter alignment mode and a reception mode. Each filter has one or more resonant networks comprising an inductance and a switched capacitor network which is digitally controlled for selecting the network resonant frequency. In the alignment mode, the controller determines the difference between the nominal and actual capacitances of the network for achieving a known resonant frequency in order to determine a correction factor for the capacitor network. The correction factor is then used during normal reception by the tuner.

Modeling and application studies for a modern static VAr system installation

Abstract: This paper presents a description of modeling and application studies related to a modern static VAr system (SVS) installation in a utility grid. The SVS incorporates a fully integrated static VAr compensator (SVC) and coordinated, automatically switched capacitor banks using a sophisticated control system. The capacitor banks are switched by individual circuit breakers. Descriptions are provided for the SVC control strategy and various levels of modeling details for the application and design studies performed for this device. The stability model described in the paper expands on a previously published work to incorporate the slow susceptance regulator, coordinated/automatic capacitor switching, as well as pertinent protection functions. New insight is presented on the effect of SVC controls on the torsional damping of nearby generators and how such interaction can be easily avoided through proper voltage regulator tuning.

Switched-capacitor based implantable low-power wireless microstimulating systems

Abstract: The main objective of this paper is to introduce a new category of implantable wireless microstimulators based on discharging a series of small capacitors to inject quantized lumps of electric charge into the excitable tissue, namely switched-capacitor based micro-stimulators (SCS). In this method, the total amount of charge per stimulation phase can be controlled by changing the initial and final capacitor voltages as well as the number of capacitors being discharged. The rate of discharge, which is the stimulus current, is also a controllable parameter that adds more flexibility to this stimulation approach, while improving the implant safety. The key reason for adopting SCS in implantable low-power devices was to combine the power efficiency of the voltage-controlled stimulators (VCS) with the safety and stimulation parameter controllability of the current-controlled stimulation (CCS) circuits. In addition, the SCS technique substantially simplifies the microstimulator architecture, and depending on the application, can potentially reduce the implant size and power requirements. It also provides an opportunity to apply different stimulus waveforms to the excitable tissue that can be more efficacious in activating the surrounding nerve or muscle fibers compared to the commonly used square-shaped pulses.

A New DC-DC Converter Circuit with Larger Step-up/down Ratio

Abstract: A novel DC-DC converter circuit Is proposed In this paper. It works as a boost converter, but its step-up ratio is much larger than that of the conventional boost converter. The point is that it has two identical capacitors on the output of a boost converter, which are charged in parallel and discharged In series automatically by the on-off transition of the main switching device, thus pumping up the output voltage. The circuit is simple and has some significant features of extended output voltage, less input current ripple and output voltage ripple as compared with the conventional boost converter. Moreover, the circuit can be modified to a bi-directional one with larger step-up and step-down ratio, which would facilitate UPS applications.

Managing subthreshold leakage in charge-based analog circuits with low-V/sub TH/ transistors by analog T- switch (AT-switch) and super cut-off CMOS (SCCMOS)

Abstract: The analog T-switch (AT-switch) scheme is introduced to suppress subthreshold-leakage problems in charge-based analog circuits such as switched capacitors and sample-and-hold circuits. A 0.5-V sigma-delta modulator is manufactured in a 0.15-/spl mu/m FD-SOI process with low V/sub TH/ of 0.1 V using the concept. The scheme is compared with another leakage-suppression scheme based on super cut-off CMOS (SCCMOS) and the conventional circuit which are also fabricated. The sigma-delta modulator based on AT-switch greatly improves 8.1-dB SNDR through reducing nonlinear leakage effects while the modulator based on SCCMOS improves the dynamic range rather than the SNDR by comparing with the conventional sigma-delta modulator.

Chaos-based true random number generator embedded in a mixed-signal reconfigurable hardware

Abstract: The paper presents a chaos-based True Random Number Generator (TRNG) implemented in commercially available mixed-signal PSoC reconfigurable devices without any external components Contrary to the traditionally used sources of randomness (eg various ”well-behaved” analog noise sources) it uses well-defined deterministic analog circuit that exhibits chaos A new simple method of mapping the deterministic chaos into the switched capacitor based mixed-signal PSoC devices is proposed The design is optimized for reduction of influence of circuit non-idealities to the quality of generated random bit stream The influence of circuit non-idealities is significantly reduced by the proposed XOR corrector and optimized circuit topology The high quality of generated true random numbers is confirmed by passing standard NIST statistical tests K e y w o r d s: cryptography, chaos, Markov chains, PSoC mixed-signal array, statistical tests, NIST test suite

CMOS switched capacitor liquid crystal driver

Abstract: A novel analogue drive circuit for a liquid crystal cell has been designed. The design was realised in a 0.5 µm CMOS process and eight phase-locked channels with independent voltage control were developed. The channels were shown to produce over 5.6π optical phase shift using a ±2.5 V power supply. This drive circuit is proposed for use in portable battery operated applications where optical phase control is desired.

A new design method for high efficiency DC-DC converters with flying capacitor technology

Abstract: Flying capacitor technology is widely used in low power dc-dc converter, especially in power management of the integrated circuit. These circuits have a limitation: high pulse currents will occur at the switching transients, which will reduce the efficiency and cause EMI problems. This makes it difficult to use this technology in high power level conversion. This paper presents a new design method for dc-dc converter with flying capacitor technology. The new method can reduce the high pulse current which usually causes serious problem in traditional converters. Therefore the power level of this new designed converter can be extended to 1 kW or even higher. A 1 kW 42/14 V flying capacitor converter was designed for 42 V automotive system. The experimental results verified the analysis and the prototype achieved the efficiency close to 96% at full load.

Methods, systems, and apparatus for integrated circuit capacitors in capacitor arrays

Abstract: A capacitor array in an integrated circuit with active unit capacitor cells arranged amongst the dummy unit capacitor cells to provide visual and electrical symmetry. The electrical symmetry provides electrical matching between active unit capacitor cells and the visual symmetry provide process uniformity between the unit capacitor cells. Visual symmetry may be provided by uniform capacitor plate selection and uniform spacing between each. Electrical symmetry is provided by appropriately arranging active unit capacitors amongst dummy unit capacitors in the capacitor array. The capacitor array may be used in an integrated circuit such as for a equally weighted or binary weighted capacitor array or ladder in an analog to digital converter or a digital to analog converter. Methods and rules of layout for arranging the unit capacitors may be manually performed or automatically performed by computer aided design software.

Comments on "Design and analysis of switched-capacitor-based step-up resonant Converters"

Abstract: With reference to a recently published paper, the realization of line and load regulation in switched-capacitor-based converters is discussed. We point out that achieving zero-current switching at the expense of losing line and load regulation is not practically feasible

Switched-capacitor (SC)/switched inductor (SL) structures for getting hybrid step-down Cuk/Sepic/Zeta converters

Abstract: Three basic switching structures are defined: one is formed by two capacitors and three diodes; the other two are formed by two inductors and two diodes They are inserted in either a Cuk converter, or a Sepic, or a Zeta converter The SC/SL structures are built in such a way as when the active switch of the converter is on, the two inductors are charged in series or the two capacitors are discharged in parallel When the active switch is off, the two inductors are discharged in parallel or the two capacitors are charged in series As a result, the line voltage is reduced more times than in classical Cuk/Sepic/Zeta converters The steady-state analysis of the new converters, a comparison of the DC voltage gain and of the voltage and current stresses of the new hybrid converters with those of the available quadratic converters, and experimental results are given

Analytical and Practical Analysis of Switched- Capacitor DC-DC Converters

Abstract: : Switched-capacitor DC-DC converters are useful alternatives to inductor-based converters in many lowpower and medium-power applications. This work develops a straightforward analysis method to determine a switched-capacitor converter's output impedance "a measure of performance and power loss". This resistive impedance is a function of frequency and has two asymptotic limits, one corresponding to very high switching frequency where resistive paths dominate the impedance, and one corresponding to very low switching frequency where charge transfers among idealized capacitors dominate the impedance. An optimization method is developed to improve the performance of these converters through component sizing based on practical constraints. Several switched-capacitor converter topologies are compared in the two asymptotic limits. Switched-capacitor converter performance "based on conduction loss" is compared with that of two magnetics-based DC-DC converters. At moderate to high conversion ratios, the switched capacitor converter has significantly less conduction loss than an inductor-based buck converter. Some aspects of converter implementation are discussed, including the power loss due to device parasitics and methods for transistor control. Implementation using both integrated and discrete devices is discussed. With the correct analysis methods, switched-capacitor DC-DC converters can provide an attractive alternative to conventional power converters.

The Switching Function: Analysis of power electronic circuits

Abstract: This book demonstrates the usefulness of the switching function in analysing power electronic circuits in the steady state. It includes analysis of generic circuits of power electronics using the switching function, and derives compact expressions for output voltage and current and input current. Further coverage includes frequency spectrums and distortion figures together with the power factor where appropriate, and switching function algebra.

Technique for reducing capacitance of a switched capacitor array

Abstract: A circuit reducing the capacitance of a switched capacitor array by mitigating switch capacitance. Reducing the effect of switch capacitance increases the frequency range of an inductor-capacitor tank containing the switched capacitor array. A pull-up circuit is coupled between a voltage source and a node. A switched capacitor and a switch are coupled to the node. The pull-up circuit biases the switch to reduce switch junction capacitance when the switch is off. In an example, a pull-up resistor is coupled between the node and a voltage source to bias the switch. In another example, a pull-up switch and pull-up resistor are coupled between the node and a voltage source to bias the switch.

Switched capacitor DRAM sense amplifier with immunity to mismatch and offsets

Abstract: A switched capacitor sense amplifier includes capacitively coupled input, feedback, and reset paths to provide immunity to the mismatches in transistor characteristics and offsets. The sense amplifier includes a cross-coupled pair of inverters with capacitors absorbing offset voltages developed as effects of the mismatches. When used in a dynamic random access memory (DRAM) device, this immunity to the mismatches and offsets allows the sense amplifier to reliably detect and refresh small signals.

Comparator design and analysis for comparator-based switched-capacitor circuits

Abstract: The design of high gain, wide dynamic range op-amps for switched-capacitor circuits has become increasingly challenging with the migration of designs to scaled CMOS technologies. The reduced power supply voltages and the low intrinsic device gain in scaled technologies offset some of the benefits of the reduced device parasitics. An alternative comparator-based switched-capacitor circuit (CBSC) technique that eliminates the need for high gain op-amps in the signal path is proposed. The CBSC technique applies to switched-capacitor circuits in general and is compatible with most known architectures. A prototype 1.5 b/stage pipeline ADC implemented in a 0.18 Fým CMOS process is presented that operates at 7.9 MHz, achieves 8.6 effective bits of accuracy, and consumes 2.5 mW of power. Techniques for the noise analysis of comparator-based systems are presented. Nonstationary noise analysis techniques are applied to circuit analysis problems for white noise sources in a framework consistent with the more familiar wide-sense-stationary techniques. The design of a low-noise threshold detection comparator using a preamplifier is discussed. Assuming the preamplifier output is reset between decisions, it is shown that. for a given noise and speed requirement, a band-limiting preamplifier is the lowest power implementation. Noise analysis techniques are applied to the prototype CBSC gain stage to arrive at, a theoretical noise power spectral density (PSD) estimate for the prototype pipeline ADC. Theoretical predictions and measured results of the input referred noise PSD for the prototype are compared showing that the noise contribution of the preamplifier dominates the overall noise performance. Thesis Supervisor: Hae-Seung Lee Title: Professor of Electrical Engineering Thesis Supervisor: Charles G. Sodini Title: Professor of Electrical Engineering Acknowledgments First, I would like to thank my wife Carrie for her patience and understanding. Without her support, I would not have made it. I realize it was not easy having a graduate student for a husband for 6 years. I look forward to our life after graduation. I would, like to thank my research advisors and mentors Prof. Harry Lee and Prof. Charlie Sodini. Their guidance and instruction during my years at MIT made my graduate career challenging, exciting and rewarding. I am indebted to them for their time, patience, and support. I would also like to thank John Fiorenza for listening to me talk about noise for the last 6 years. It has been nice to have at least one person in the office who had some idea of what I was talking about and that I could bounce ideas off of. And in our spare time, I think we may have actually solved some of the worlds problems over coffee... I would like to thank Peter Holloway for his assistance, guidance and many stimulating discussions over the last couple of years of my Ph.D, and Prof. Jim Roberge for taking the time to read my thesis and be on my committee. I would. like to acknowledge the many members of the Sodini group during my tenure at MIT. The group who endured the Ph.D. program with me: Anh Pham, Andy Wang, Lunal Khuon, and Albert Jerng. The many good technical discussions, the dinners out, the homework, the tapeouts, and finally graduation. To the many junior members of the group, some who have come and gone and others who must still carry on: Kevin Ryu, Farinaz Edalat, Nir Matalon, Kartik Lamba, Khoa Nguyen, Ivan Nausieda, Albert Lin, Jit Ken Tan, Matt Powell and Johnna Powell: it has been a pleasure to work with all of you. I also cannot forget to mention those who were senior members when I arrived: Don Hitko, Dan McMahill, Ginger Wang, Iliana Fujimori Chen, and Pablo Acosta Serafini for helping me when I was new. Similarly, I would like to acknowledge the members of the H. S. Lee group: former cube-mate Mark Peng, contemporaries Andrew Chen, Matt Guyton, Albert Chow, fellow Big Ten alum Mark Spaeth for many great technical and non-technical conversations, Lane Brooks for many helpful discussions about CBSC, and the senior members who welcomed me to the group on their way out: Kush Gulati, Ayman Shabra, and Susan Luschas. I have also had the pleasure of meeting many other outstanding individuals during my time at MIT who are to numerous to name, including my colleagues in the MTL community and the students on the second floor of Bldg 38. I would like to acknowledge the MTL Mallards Hockey Team and especially Andy Fan for his efforts to keep the team going and his inspirational pregame emails. Hockey with the Mallards was an important part of my MIT education. I would like thank the administrative assistants Kathy Patenaude, Rhonda Maynard, and Carolyn Collins who always helped to part the MIT red tape. Marilyn Pierce, who has been of great assistance in all departmental and institute matters. She is always looking out for the graduate students. Debb Hodges-Pabon, her enthusiasm is contagious; she has made the MTL a great place to work. I would like to thank the MTL computer and CAD support staff: Mike Hobbs, Bill Maloney, and Mike McIlrath for keeping the computing and CAD infrastructure functioning. I would like to thank my parents for their continued support and encouragement. I would like to thank my brother Scott for letting me vent my frustrations when necessary; it is great to have someone else in the family who really understands the life of a doctoral candidate. The author was funded by the MARCO Focus Center for Circuits and System Solutions (C2S2, www.c2s2.org) contract 2003-CT-888x and the MIT Center for Integrated Circuits and Systems (CICS). The chip fabrication and packing for the prototype in this thesis were donated by National Semiconductor. Dedication I dedicate this thesis to my Grandmother Beulah T. Fleming (January 6, 1912August 11. 2006) who passed away during my final days at MIT. Her letters and phone calls were always a welcome respite from life as a graduate student. I could always count on her being awake at all hours of the night, eager to hear about recent events in my life, and willing to share her thoughts on current events or memories of days gone by.

Single-Event Sensitivity and Hardening of a Pipelined Analog-to-Digital Converter

Abstract: Circuit simulations are used to determine the response of a pipelined analog-to-digital converter (ADC) to radiation-induced single-event transients. The ADC uses a cascade of 9 stages which each resolve 1.5 bits. Digital error correction is used to reassemble the bits and to correct for errors in the comparators and sub-DAC. A Monte-Carlo methodology is used to simulate the single-event vulnerability of the circuit. Circuit simulations are performed using the Spectre circuit simulator. Sensitive cross-sections were derived from an analysis of the simulation results. Sensitive areas were identified and hardening techniques were applied to the circuit. These techniques may be applicable to other mixed-signal and switched-capacitor circuits. A significant reduction in the sensitive cross-section was obtained by application of these hardening techniques

Comparator-based switched capacitor circuit for scaled semiconductor fabrication processes

Abstract: Described is a switched capacitor circuit for performing an analog circuit function. Unlike conventional switched capacitor circuits employing operational amplifiers, the switched capacitor circuit uses a comparator and does not require direct feedback between the input and output of the comparator. The switched capacitor circuit includes a first and a second switched capacitance network, a comparator and a current source. The first switched capacitance network has an input terminal to receive a circuit input voltage during a first phase. The comparator has an input terminal in communication with the first switched capacitance network and an output terminal in communication with the second switched capacitance network through a switched terminal. The current source communicates with the switched capacitance networks and supplies a current to charge the networks during a second phase. The circuit can be used, for example, to provide high gain amplification in integrated circuits.

A low-power/low-noise readout circuit for integrated capacitive sensors

Abstract: A switched-capacitor integrated system is presented in this work that attains sub-fF measurement resolution in integrated capacitive sensors, with 1.5-kHz bandwidth and 50-muW average power consumption in continuous function mode. The proposed design employs a pair of nonoverlapping clocks and an operational transconductance amplifier (OTA) that can be made as simple as a basic differential pair. The system exhibits 0.8% linearity error and 0.01 fF/degC temperature drift. It is appropriate for differential, absolute, and ratiometric capacitance measurements, and shows robustness against interconnection parasitics, transistor dimensional mismatch, and process variations, which are an important feature in the case of sensor-die CMOS postprocessing

Gyrator Realization Based on a Capacitive Switched Cell

Abstract: Efficient power gyrator realization by means of a controlled switch cell is presented. It is shown that a switching cell may be controlled so as to acquire low-frequency gyrative characteristics (on average). A realization suitable for operation with current sources is presented, that employs a switched capacitor. Due to the capacitive input, a gyrator of this nature is suitable for operation with current sources. The main applications of such gyrators are expected in superconductive magnetic energy storage systems and current-fed converters, due to the stiff-current characteristic imposed by a magnetic storage element. Other possible applications include sources with softer i-v characteristics, such as photovoltaic generators and sources of significant output inductance

A Novel Dynamic Capacitor Compensator/Green Plug Scheme for 3Phase-4 Wire Utilization Loads

Abstract: The paper presents a novel effective electric energy conservation device for power quality enhancement as well as damping switching-load transients. The modulated power filter and switched capacitor compensator device (MPFC-Green Plug) is developed by the First Author for the 3 phase, 4 wire utilization loads. A novel Tri loop Dynamic Error driven switching controller is also used. Switching transients and sudden phase load imbalances are effectively reduced. The voltage can be stabilized for even severe load unbalances and the ac supply power factor can be greatly improved, hence an enhanced power/energy utilization. The digital model validation study had been done for different cases of balanced and unbalanced nonlinear loads without and with the new (MPFC-Green plug) capacitor compensator (Patent pending). Digital Simulation study covered short circuit faults as well as open circuit conditions. Digital simulation results are compared without and with the use of the new device.

Peak-Current Mode control of Hybrid Switched Capacitor Converter

Abstract: In this paper analysis and controller design of a peak-current mode controlled higher order buck converter is presented. Various small-signal models valid up-to half of the switching frequencies, are developed using state-space averaging method, and then a step-by-step controller design procedure is described. The results of controller design and closed-loop analysis are illustrated through computer simulations. To validate the controller design and analysis, experimental observations of a prototype hybrid switched-capacitor converter are provided for 28 V applications.

Managing subthreshold leakage in charge-based analog circuits with low-VTH transistors by analog T- switch (AT-switch) and super cut-off CMOS (SCCMOS)

Abstract: The analog T-switch (AT-switch) scheme is introduced to suppress subthreshold-leakage problems in charge-based analog circuits such as switched capacitors and sample-and-hold circuits. A 0.5-V sigma-delta modulator is manufactured in a 0.15-μm FD-SOI process with low V TH of 0.1 V using the concept. The scheme is compared with another leakage-suppression scheme based on super cut-off CMOS (SCCMOS) and the conventional circuit which are also fabricated. The sigma-delta modulator based on AT-switch greatly improves 8.1-dB SNDR through reducing nonlinear leakage effects while the modulator based on SCCMOS improves the dynamic range rather than the SNDR by comparing with the conventional sigma-delta modulator.

Modeling Op Amp Nonlinearity in Switched-Capacitor Sigma-Delta Modulators

Abstract: A system-level methodology for the inclusion of op amp nonlinearity in discrete-time integrators and SigmaDelta modulators is proposed that consists of a hyperbolic tangent model for the input/output characteristic of op amps and a recursive solution of nonlinear integrators. Simulations at different levels of abstraction indicate that the methodology incurs an error of no more than 1.1 dB in the magnitude of harmonics while providing a 50times advantage in the simulation speed with respect to transistor-level implementations