Showing papers on "Switched capacitor published in 2007"

Voltage Scalable Switched Capacitor DC-DC Converter for Ultra-Low-Power On-Chip Applications

Abstract: This paper presents a voltage scalable switched capacitor (SC) DC-DC converter which employs on-chip charge- transfer capacitors. The DC-DC converter makes use of multiple topologies to achieve scalable voltage generation while minimizing conduction loss and a technique called divide-by-3 switching to minimize the loss due to bottom-plate parasitics. It also uses automatic frequency scaling to reduce switching losses. The converter employs an all digital control which consumes no static power. The voltage scalable SC DC-DC converter with integrated on-chip charge-transfer capacitors was implemented in a 0.18 mum CMOS process and achieves above 70% efficiency over a wide range of load powers from 5 muW to 1 mW, while delivering load voltages from 300 mV to 1.1 V. The active area consumed by the converter is 0.57 mm2.

Switched capacitor converters

Abstract: A switched capacitor converter has a supply voltage input, an output circuit with one or more load capacitors, a semiconductor switch network. The switch network is connected at a switch junction point and across the voltage input, and has one or more pairs of said first and second switches. Each pair of switches is associated with one of the load capacitors and each pair is connected in series. The converter also has a charging capacitor network connected across the semiconductor switch network and across the voltage input. The charging capacitor network has one or more charging capacitors and inductances connected between the switch junction point and the output circuit. Each of the charging capacitors and inductances is associated with one of the load capacitors. The load capacitors are each charged by the associated charging capacitor when the associated first switch is closed and the associated second switch is open. And the load capacitors are each discharged by the associated inductance when the associated first switch is closed and the associated second switch is open.

A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE

Abstract: A low-power receiver with a one-tap decision feedback equalization (DFE) was fabricated in 90-nm CMOS technology. The speculative equalization is performed using switched-capacitor-based addition at the front-end sample-hold circuit. In order to further reduce the power consumption, an analog multiplexer is used in the speculation technique implementation. A quarter-rate-clocking scheme facilitates the use of low-power front-end circuitry and CMOS clock buffers. The receiver was tested over channels with different levels of ISI. The signaling rate with BER<10-12 was significantly increased with the use of DFE for short- to medium-distance PCB traces. At 10-Gb/s data rate, the receiver consumes less than 6.0 mW from a 1.0-V supply. This includes the power consumed in all quarter-rate clock buffers, but not the power of a clock recovery loop. The input clock phase and the DFE taps are adjusted externally

Circuit and method for a fully integrated switched-capacitor step-down power converter

Abstract: A circuit and method for providing a fully integrated DC-DC converter using on-chip switched capacitors is disclosed. A switched capacitor matrix is coupled as a digitally controlled transfer capacitor. A pair of non-overlapping, fixed frequency clock signals is provided to a switched capacitor circuit including the switched capacitor matrix and a load capacitor coupled to the output terminal. A DC input voltage supply is provided. A hysteretic feedback loop is used to control the voltage at the output as a stepped-down voltage from the input by digitally modulating the transfer capacitor using switches in the switch matrix to couple more, or fewer, transfer capacitors to the output terminal during a clock cycle. A coarse and a fine adjustment circuit are provided to improve the regulation during rapid changes in load power. A method of operating the regulator is disclosed.

A Robust Chaos-Based True Random Number Generator Embedded in Reconfigurable Switched-Capacitor Hardware

Abstract: This paper presents a new chaos-based True Random Number Generator (TRNG) with decreased voltage supply sensitivity Contrary to the traditionally used sources of randomness it uses well-defined deterministic switched-capacitor circuit that exhibits chaos The whole design is embedded into commercially available mixed-signal PSoC reconfigurable device without any external components Proposed design is optimized for reduction of influence of supply voltage to the quality of generated random bit stream The influence of circuit non-idealities is significantly reduced by the proposed XOR corrector and optimized circuit topology The ultimate output bit rate of proposed TRNG is 60 kbit/s and quality of generated bit-streams is confirmed by passing standard FIPS and correlation statistical tests performed in the full range of PSoC device supply voltages

Protective circuit and method for multi-level converter

Abstract: A protective circuit for a multi-level converter including a DC link capacitor bank includes: an energy absorbing element; switches, wherein at least two of the switches each couple the energy absorbing element to the capacitor bank; and a controller configured to provide control signals to the switches to selectively actuate the switches to enable control of energy dissipation and to enable control of voltage balance on the capacitor bank of the multi-level converter.

A New Switched-Capacitor Boost-Multilevel Inverter Using Partial Charging

Abstract: In this brief, a new switched-capacitor-boost-multilevel (SCBM) inverter is proposed and implemented. This inverter possesses the distinct features of both voltage boost up and near-sinusoidal staircase output voltage. The key is to utilize partial charging in such a way that multiple voltage steps per capacitor can be realized, hence significantly reducing the number of capacitors for a given number of levels. Based on using only two capacitors, a 13-level SCBM inverter is designed and analyzed, with emphasis on assessing its total harmonic distortion. Both simulation and experimental results are given to confirm the theoretical analysis.

Switched capacitor circuit with inverting amplifier and offset unit

Abstract: A switched capacitor circuit includes an amplifier, a charging unit, an offset unit, and an integrating unit. The charging unit is coupled between an input node and a first node, and is for accumulating charge corresponding to an input signal during a sampling mode. The offset unit is coupled between the first node and an input of the amplifier, and is for maintaining the first node to be a virtual ground during an integrating mode. The integrating unit is coupled between the first node and an output of the amplifier, and is for receiving charge from the charging unit during the integrating mode.

Locating Switched Capacitor Using Wavelet Transform and Hybrid Principal Component Analysis Network

Abstract: The transient caused by capacitor switching is one of the important power quality (PQ) problems. In particular, switching on the capacitor may result in an overvoltage to a sensitive load, serious disturbance to an adjustable-speed drive or a resonance in the system. This paper presents a new method to locate the positions of the transient sources with the help of the PQ monitoring system. The discrete wavelet transform is used to extract the features of transients caused by capacitor switching. The fuzzy-c-means is then used to determine the placement of PQ measurement facilities. The signal energies attained by wavelet coefficients serve as inputs to the hybrid principal component analysis neural network for locating the transient sources. The simulation results obtained from an 18-bus distribution system show the applicability of the proposed method

Comments on “Unified Analysis of Switched-Capacitor Resonant Converters”

Abstract: The realization of line and load regulation in switched-capacitor (SC)-based converters is discussed. A duty-cycle control is based on partial charging of the capacitors in the circuit. The influence on the efficiency is pointed out. The use of inductors in SC-based converters is discussed

Fully Integrated High-Q Switched Capacitor Bandpass Filter with Center Frequency and Bandwidth Tuning

Abstract: This paper proposes to study the design of a novel high-Q fully integrated switched capacitor bandpass filter. This circuit, implemented in CMOS technology, allows a tunable high selectivity over a broad frequency band. The proposed architecture is intended to replace passive surface acoustic wave (SAW) filters in low-cost wireless radio-communication applications. To show the feasibility of the proposed filter a prototype has been fabricated and tested. Measurements show quality factors up to 300, and a tunable center frequency range of 290 MHz [240 - 530 MHz] with a bandwidth tuning.

A 10-bit 205-MS/s 1.0- $\hbox{mm}^{2}$ 90-nm CMOS Pipeline ADC for Flat Panel Display Applications

Abstract: This paper describes a 10-bit 205-MS/s pipeline analog-to-digital converter (ADC) for flat panel display applications with the techniques to alleviate the design limitations in the deep-submicron CMOS process. The switched source follower combined with a resistor-switch ladder eliminates the sampling switches and achieves high linearity for a large single-ended input signal. Multistage amplifiers adopting the complementary common-source topology increase the output swing range with lower transconductance variation and reduce the power consumption. The supply voltage for the analog blocks is provided by the low drop-out regulator for a high power-supply rejection ratio (PSRR) under the noisy operation environment. The pipeline stages of the ADC are optimized in the aspect of power consumption through the iterated calculation of the sampling capacitance and transconductance. The ADC occupies an active area of 1.0 mm2 in a 90-nm CMOS process and achieves a 53-dB PSRR for a 100-MHz noise tone with the regulator and a 55.2-dB signal-to-noise-and-distortion ratio for a 30-MHz 1.0-VPP single-ended input at 205 MS/s. The ADC core dissipates 40 mW from a 1.0-V nonregulated supply voltage.

Switched Capacitor Signal Conditioning for Differential Capacitive Sensors

Abstract: A novel switched capacitor signal-conditioning circuit for differential capacitive sensors is proposed. The main advantage of the proffered method lies in the fact that it accepts sensors possessing either linear or inverse characteristics and provides a linear output. Moreover, the output is dependent only on a pair of dc reference voltages and the transformation constant of the sensor. Hence, increased linearity and accuracy is easily achieved by employing precision dc reference voltages. Results from the tests on a prototype elucidate the practicality of the proposed method

Signal conditioning methods and circuits for a capacitive sensing integrated tire pressure sensor

Abstract: A tire pressure monitoring system is provided that includes a switched capacitor circuit having a clock with two non-overlapping clock phases that control a state of analog switches of the switched capacitor circuit. The system uses tire pressure sensor MEMS capacitors that are measured differentially. A capacitance-to-voltage converter is connected to the MEMS sense capacitor, and a sigma-delta converter having a comparator with a first digital output state and a second digital output state is used. The first output state is a sum of reference voltages and the second output state is a difference of the reference voltages. An average value of the capacitance-to-voltage converter output is driven to a zero value and a digital output is provided of the average output states that is equal to a difference between the MEMS capacitors divided by their sum multiplied by a ratio of the reference voltages.

Measured CMOS Switched High-Quality Capacitors in a Reconfigurable Matching Network

Abstract: Switched capacitors are here investigated for use in reconfigurable matching networks, particularly for digital video broadcasting-handheld (DVB-H) frequencies. A 0.13-μm CMOS circuit is evaluated through both simulations and measurements. Source grounded nMOS transistors are used to switch high-quality metal capacitors located above metal layer 8. The quality factor and tuning range depend on frequency, switch voltage, capacitor size, and transistor width. There is a clear tradeoff between quality factor and tuning range, and measurements show quality factors above 50, 100, and 150 at tuning ranges of 3.9, 2.4, and 1.6, respectively. A reconfigurable matching network with the switched capacitors has been realized using external inductors and the measured matching domain for the DVB-H frequency band is shown. The total loss of the network is 1.0 dB, a result of the high-quality switched capacitors.

Output Voltage Control of Resonant Boost Switched Capacitor Converter

Abstract: Conventional switched capacitor converters have an inherent drawback that their efficiency is much decreased as the output current is increased. To solve this problem we presented a novel switched capacitor converter topology that uses a resonant operation instead of the forced charging and discharging operation. Its advantage over a conventional switched capacitor converter is a high efficiency even in a high output current region. In this paper, firstly, the operation analysis and the steady-state characteristics are analyzed for a double boost type switched capacitor converter with synchronous rectifiers under the condition that the switching frequency matches with the resonant frequency. Next, the steady-state characteristics are analyzed when using the output voltage control by changing the switching frequency.

A Novel QR ZCS Switched-Capacitor Bidirectional Converter

Abstract: The proposed quasi-resonant (QR) zero current switching (ZCS) switched-capacitor (SC) converter is a new type of bi-directional power flow control conversion scheme They are able to provide the voltage conversion ratios from 2 versus 1/2 (double-mode/half-mode) to n versus 1/n (n-mode/1/n-mode) by adding a different number of switched-capacitors and power MOSFET switches with a small series connected resonant inductor for forward and reverse schemes The low current stress and balance resonance current are the advantage of the proposed quasi resonant switched-capacitor converter The principle of operation, theoretical analysis of the proposed bi-directional power conversion scheme is described in detail with circuit model analysis Simulation and experimental results are carried out to verify the performance of the new type ZCS SC bi-directional QR converters

Switched-Capacitor Track-and-Hold Amplifiers With Low Sensitivity to Op-Amp Imperfections

Abstract: This paper describes high-precision switched-capacitor (SC) track-and-hold amplifier (THA) stages. They use a novel continuous-time correlated double sampling (CDS) scheme to desensitize the operation to amplifier imperfections. Unlike earlier predictive-CDS amplifiers, the circuits do not need a sampled-and-held input signal for their operation. During the tracking period, an auxiliary continuous-time signal path is established, which predicts the output voltage during the holding period. This allows accurate operation even for low amplifier gains and large offsets over a wide input frequency range. Extensive simulations were performed to compare the performance of the proposed THAs with earlier circuits utilizing CDS. The results verify that their operation is far more robust than that of any previously described SC amplifiers

Multi-tap direct sub-sampling mixing system for wireless receivers

Abstract: A multi-tap direct sub-sampling mixing system for wireless receivers is provided with a dynamically configurable passive switched capacitor filter. A front end amplifier is connected to receive a signal. The passive switched capacitor filter is connected to receive the amplified signal and has an output for providing a filtered signal. The switched capacitor filter has at least two sections that are each operable as a pole, wherein a first section of the at least two sections has sets of at least two stacked capacitors interconnected with a set of switches operable to amplify in input voltage provided to an input of the first section in response to operation of the set of switches; and a back end section connected to the output of the switched capacitor filter to receive the filtered signal.

A Low Power Sigma-Delta Modulator Using Class-C Inverter

Abstract: In switched capacitor sigma-delta (SigmaDelta) analog-to-digital converters (ADCs), an operational transconductance amplifier (OTA) is the main building block and consumes most of power. This paper proposes that the OTAs can be replaced with class-C inverters for low-power consumption without sacrificing the performance. A second order SigmaDelta modulator using class-C inverter technique is fabricated with a 0.35-mum CMOS process, occupies 3024 mum2 , dissipates 5.6-muW under 1.2 V supply-voltage, and provides 63-dB/72-dB/76-dB SNDR/SNR/DR over 8-kHz signal bandwidth.

Behavioral Modeling Methods for Switched-Capacitor $\Sigma \Delta$ Modulators

Abstract: Sigma-delta Modulators (SigmaDeltaMs) are cornerstone elements in oversampled analog-to-digital converters and digital-to-analog converters (DAC). Although transistor-level simulation is the most accurate approach known for these components, this method becomes impractical for complex systems due to its long computational time requirements. Behavioral modeling has become a viable solution to this problem. In this paper, we study styles and issues in the accurate modeling of low-power, high-speed SigmaDeltaMs and introduce two new behavioral models for switched-capacitor (SC) integrators. The first model is based on the SC integrator transient response, including the effects of the amplifier transconductance, output conductance, and the dynamic capacitive loading effect on the settling time. The second model is based on a symbolic node admittance matrix representation of the system. Nonidealities such as jitter, thermal noise, and DAC mismatch are also addressed and included in a dual-band, GSM/WCDMA, second-order, multibit SigmaDeltaM model with individual level averaging. VHDL-AMS and MATLAB Simulink were used as modeling languages. Both models are validated against experimental data, showing competitive results in the signal-to-noise-plus-distortion ratio. A comparative analysis between the proposed and a traditional model is presented, with emphasis on the degrading effects due to the integrator dynamics. Moreover, a general simulation speed analysis of the proposed models is addressed.

Ultra Low Power Capacitive Sensor Interfaces

Abstract: An increasing number of medical diagnostics, comfort, entertainment, and sports applications are making use of capacitive sensor systems in and around the body. These sensor systems should work as small distributed units that can collect data over a long period of time. So, ultra low power electronics are a major challenge in these applications. Ultra Low Power Capacitive Sensor Interfaces describes the design and theory of ultra low power capacitive sensor interfaces. The books major asset is the realization of a very low power generic sensor interface chip, that is adaptable to a broad range of capacitive sensors. The book starts with an overview on the most important design aspects for autonomous sensor systems. The different building blocks are discussed and the modular architecture for the generic sensor interface chip is presented. Furthermore, the design of the analog components, such as capacitance-to-voltage converters, switched capacitor amplifier, Sigma Delta modulator, oscillators and reference circuits, is described in more detail. Finally, the generic sensor interface chip is applied in several state-of-the-art pressure sensor and accelerometer applications. Ultra Low Power Capacitive Sensor Interfaces is essential reading for anybody with an academic or professional interest in semiconductor design.

Design, Modeling, and Characterization of Embedded Capacitor Networks for Core Decoupling in the Package

Abstract: Embedded passives are gaining in importance due to the reduction in size of electronic products. Capacitors pose the biggest challenge for integration in packages due to the large capacitance required for decoupling high performance circuits. Surface mount discrete (SMD) capacitors become ineffective charge providers above 100 MHz due to the increased effect of loop inductance. This paper focuses on the importance of embedded capacitors above this frequency. Modeling, measurements, and model to hardware correlation of these capacitors are shown. Design and modeling of embedded capacitor arrays for decoupling processors in the midfrequency band (100 MHz-2 GHz) is also highlighted in this paper.

Single-Stage Voltage SourceChargePumpElectronic Ballast with Switched-Capacitor DimmerforMultiple Fluorescent Lamps

Abstract: Thispaperpresents a single-stage electronic ballast for drivingmultiple fluorescent lampsinwhichadimming control scheme isproposed toregulate thelampcurrent. A laboratory prototype isbuilt andtested, andit isfoundthatunity powerfactor canremain underindividual lampbrightness control. The experimental results aretherefore shownto verify thefeasibility oftheproposed method. Keywords-Multiple Fluorescent Lamps, Single-Stage Electronic Ballast, Dimming Control

Switched-Capacitor Techniques for High-Accuracy Filter and ADC Design

Abstract: Switched capacitor (SC) techniques are well proven to be excellent candidates for implementing critical analogue functions with high accuracy, surpassing other analogue techniques when embedded in mixed-signal CMOS VLSI Conventional SC circuits are primarily limited in accuracy by a) capacitor matching and b) the accuracy with which a differential amplifier can squeeze charge from one capacitor to another between clock periods In Switched-Capacitor Techniques for High-Accuracy Filter and ADC Design, alternative SC techniques are proposed which allow the achievement of higher intrinsic analogue functional accuracy than previously possible in such application areas as analogue filter and ADC design The design philosophy is to create the required functionality without relying on digital calibration or correction means but instead to develop methods which have reduced dependence on both component matching (especially capacitor matching) and parasitic effects (especially parasitic capacitance) However, the proposed techniques are just as amenable to further digital accuracy enhancement via calibration and/or correction as traditional methods Two popular application areas are explored in the course of this book for exploitation of the proposed techniques, viz SC filters and algorithmic ADCs - both cyclic and pipelined Furthermore, efficient system level design procedures are explored in each of these two areas The validity of the concepts developed and analyzed in Switched-Capacitor Techniques for High-Accuracy Filter and ADC Design has been demonstrated in practice with the design of CMOS SC bandpass filters and algorithmic ADC stages For example, a 107MHz radio IF selectivity filter integrated in standard CMOS, employing the proposed methods, achieves an accuracy greater than ceramic filters Another example is an ADC with better than 12-bit intrinsic accuracy, albeit capacitors with only 9-bits matching accuracy were used in the realization The ADC architecture is also very robust and proven in an embedded digital VLSI application in the very newest 65nm CMOS The power consumptions and silicon areas of the solutions proposed here are lower than other known solutions from the literature

High-Performance and Low-Cost Single-Switch Current-Fed Energy Recovery Circuit for ac Plasma Display Panel

Abstract: A high-performance and low-cost single-switch current-fed energy recovery circuit (ERC) for an alternating current (ac) plasma display panel (PDF) is proposed. Since it is composed of only one power switch compared with the conventional circuit consisting of four power switches and two large energy recovery capacitors, it features a much simpler structure and lower cost. Furthermore, since all power switches can be switched under soft-switching operation, the proposed circuit has desirable merits such as an increased reliability, and low switching loss. Especially, there are no serious voltage notches across the PDP with the aid of gas discharge current compensation, which can greatly reduce the current stress of all inverter switches, and provide those switches with the turn on timing margin. To confirm the validity of the proposed circuit, its operation and performance were verified on a prototype for 7-in test PDP.

Methods and apparatuses for stacked capacitors for image sensors

Abstract: Capacitive circuits and methods of forming capacitive circuits including a first capacitor and a second capacitor connected in parallel to the first capacitor, wherein the first capacitor is positioned at least partially above the second capacitor.

Single-Stage Voltage Source Charge-Pump Electronic Ballast With Switched-Capacitor Dimmer for Multiple Fluorescent Lamps

Abstract: This paper presents a single-stage electronic ballast for driving multiple fluorescent lamps in which a dimming control scheme is proposed to regulate the lamp current. A laboratory prototype is built and tested, and it is found that the unity power factor can remain under individual lamp brightness control. The experimental results are therefore shown to verify the feasibility of the proposed method.

Microelectronic Implementations of Fractional-Order Integrodifferential Operators

Abstract: For practical applications, the fractional order integral and differential operators require to be approximated as stable, causal, minimum-phase integer order systems, which usually leads, in both continuous and discrete domains, to high order transfer functions. Assuming that an approximation of good quality is available for the fractional operator, efficient implementations, in both cost and speed, are required. The fast development of the microelectronics gives us the opportunity of using cheap, accurate, programmable and fast devices for implementing reconfigurable analog and digital circuits. Among these devices, Field Programmable Gate Arrays (FPGAs), Switched Capacitors Circuits (SCCs), and Field Programmable Analog Arrays (FPAAs) are used in this paper for the implementation of a fractional order integrator, previously approximated by the recursive Oustaloup’s method. The fundamentals of the devices, as well as the design procedures are given, and the implementations are compared considering their simulated frequency responses, the design efforts, and other important issues.Copyright © 2007 by ASME

Isolated Boost Converters

Abstract: Two implementations of the isolated boost converter that exhibit no parasitic voltage ringing across all semiconductor devices on the primary and secondary sides of the transformer are introduced Ringing-free operation is achieved by clamping the voltages of the primary switches and rectifiers to the voltage of the primary-side energy-storage capacitor and clamping the voltage across the secondary-side rectifiers to the output filter capacitor The performance of the proposed topology was verified on a dual ac-input, 900-W experimental prototype operating at 67 kHz