Showing papers on "Switched capacitor published in 2009"
TL;DR: A 65 nm system-on-a-chip which demonstrates techniques to mitigate variation, enabling sub-threshold operation down to 300 mV, and a switched capacitor DC-DC converter is integrated on-chip, achieving above 75% efficiency.
Abstract: Aggressive supply voltage scaling to below the device threshold voltage provides significant energy and leakage power reduction in logic and SRAM circuits. Consequently, it is a compelling strategy for energy-constrained systems with relaxed performance requirements. However, effects of process variation become more prominent at low voltages, particularly in deeply scaled technologies. This paper presents a 65 nm system-on-a-chip which demonstrates techniques to mitigate variation, enabling sub-threshold operation down to 300 mV. A 16-bit microcontroller core is designed with a custom sub-threshold cell library and timing methodology to address output voltage failures and propagation delays in logic gates. A 128 kb SRAM employs an 8 T bit-cell to ensure read stability, and peripheral assist circuitry to allow sub-Vt reading and writing. The logic and SRAM function in the range of 300 mV to 600 mV, consume 27.2 pJ/cycle at the optimal V DD of 500 mV, and 1 muW standby power at 300 mV. To supply variable voltages at these low power levels, a switched capacitor DC-DC converter is integrated on-chip and achieves above 75% efficiency while delivering between 10 muW to 250 muW of load power.
293 citations
21 May 2009
TL;DR: A design methodology for Switched-Capacitor DC-DC Converters is presented in this article, along with a design methodology for switching-capacitor-DC-DC converters.
Abstract: A Design Methodology for Switched-Capacitor DC-DC Converters
269 citations
TL;DR: An inverter-based SC circuit and its application to low-voltage, low-power delta-sigma (DeltaSigma) modulators is proposed and the prototype DeltaSigma modulators achieved high power efficiency maintaining sufficient performances for practical applications.
Abstract: An operational transconductance amplifier (OTA) is a major building block and consumes most of the power in switched-capacitor (SC) circuits, but it is difficult to design low-voltage OTAs in scaled CMOS technologies. Instead of using an OTA, this paper proposes an inverter-based SC circuit and its application to low-voltage, low-power delta-sigma (DeltaSigma) modulators. Detailed analysis and design optimizations are also provided. Three inverter-based DeltaSigma modulators are implemented for an implantable pacemaker, a CMOS image sensor, and an audio codec. The modulator-I for an implantable pacemaker achieves 65-dB peak-SNDR for 120-Hz bandwidth consuming 0.73 muW with 1.5 V supply. The modulator-II for a CMOS image sensor implemented with 320-channel parallel ADC architecture achieves 63-dB peak-SNDR for 8-kHz bandwidth consuming 5.6 muW for each channel with 1.2-V supply. The modulator-III for an audio codec achieves 81-dB peak-SNDR with 20-kHz bandwidth consuming 36 muW with 0.7-V supply. The prototype DeltaSigma modulators achieved high power efficiency maintaining sufficient performances for practical applications.
268 citations
TL;DR: Unlike previous methods for battery-storage systems, which include complex circuit detecting and comparing the voltages of capacitor cells, the novel equalizer can realize autonomic voltage equalization without voltage detection and comparison, and it is more efficient with the soft switching method, which is a benefit for high-power applications in EV/HEV.
Abstract: Energy-storage systems (ESSs) play an important role in electric vehicle (EV) and hybrid EV (HEV) applications. In the system, an ultracapacitor is preferred for high power buffer and regenerative braking energy storage because it has the advantages of high power density, long life cycles, and high efficiency. While in the high-voltage application, the ultracapacitors are employed in series, and the voltage unbalance issue must be taken care of. This paper presents a novel circuit for equalizing a series ultracapacitor stack, which is based on a dc-dc converter. The proposed voltage-equalization circuit derives energy from the series ultracapacitor stack and transfers them to the weakest ultracapacitor cell. The equalizer balances the whole stack by sequentially compensating the weak ultracapacitor cells. Unlike previous methods for battery-storage systems, which include complex circuit detecting and comparing the voltages of capacitor cells, the novel equalizer can realize autonomic voltage equalization without voltage detection and comparison, and it is more efficient with the soft switching method, which is a benefit for high-power applications in EV/HEV. The simulation and experiment results validate the feasibility of the proposed equalization circuits.
173 citations
06 Nov 2009
TL;DR: The quasi-resonant technique for multilevel modular switched-capacitor circuit (MMSCC) to achieve zero-current-switching (ZCS) without increasing cost and sacrificing reliability is presented, leading to reliable and high efficiency advantages over traditional MMSCC.
Abstract: This paper presents a quasi-resonant technique for multilevel modular switched-capacitor circuit (MMSCC) to achieve zero-current-switching (ZCS) without increasing cost and sacrificing reliability. This zero-current-switching multilevel modular switched-capacitor circuit (ZCS-MMSCC) employs the stray inductance existing in the circuit as the resonant inductor to resonate with the capacitor and provide low dv/dt and low switching loss for the device. The ZCS-MMSCC does not utilize any additional components to achieve ZCS and solves the current and voltage spike problem during the switching transition, thus leading to reliable and high efficiency advantages over traditional MMSCC. Furthermore, the ZCS-MMSCC reduces the capacitance needed the circuit; in this case, the bulky capacitors present in traditional MMSCC to attain high efficiency is not necessary any more. A 150 W four-level ZCS-MMSCC prototype has been built. Simulation and experimental results are given to demonstrate the validity and features of the soft switching switched-capacitor circuit.
131 citations
TL;DR: This paper proposes a combination of neural network and a bandless hysteresis controller, for a switched capacitor active power filter (SCAPF), to improve line power factor and to reduce line current harmonics.
Abstract: This paper proposes a combination of neural network and a bandless hysteresis controller, for a switched capacitor active power filter (SCAPF), to improve line power factor and to reduce line current harmonics. The proposed active power filter controller forces the supply current to be sinusoidal, in phase with line voltage, and has low current harmonics. Two main controls are proposed for it: neural network detection of harmonics and bandless digital hysteresis switching algorithm. A mathematical algorithm and a suitable learning rate determine the filter's optimal operation. A digital signal controller (TMS320F2812) verifies the proposed SCAPF, implementing the neural network and bandless hysteresis algorithms. A laboratory SCAPF system is built to test its feasibility. Simulation and experimental results are provided to verify performance of the proposed SCAPF system.
129 citations
06 Nov 2009
TL;DR: In this article, a generic modeling methodology that analyzes the losses in Switched Capacitors Converters (SCC) was developed and verified by simulation and experiments, covering both hard and soft switched SCC topologies.
Abstract: A generic modeling methodology that analyzes the losses in Switched Capacitors Converters (SCC) was developed and verified by simulation and experiments. The proposed analytical approach is unified, covering both hard and soft switched SCC topologies. The major advantage of the proposed model is that it expresses the losses as a function of the currents passing through each flying capacitor. Since these currents are linearly proportional to the output current, the model is also applicable to SCC with multiple capacitors. The proposed model provides an insight into the expected losses in SCC and the effects of their operational conditions such as duty cycle. As such, the model can help in the optimization of SCC systems and their control to achieve desired regulations.
96 citations
06 Nov 2009
TL;DR: In this paper, a flying capacitor is added to the three level buck converter to reduce the MOSFET voltage stress by half allowing for the use of low voltage devices, doubling the effective switching frequency, and decreasing the inductor size.
Abstract: The three level buck converter can offer high efficiency and high power density in VR and POL applications. The gains are made possible by adding a flying capacitor that reduces the MOSFET voltage stress by half allowing for the use of low voltage devices, doubles the effective switching frequency, and decreases the inductor size by reducing the volt-second across the inductor. To achieve high efficiency and power density the flying capacitor must be balanced at half of the input voltage and the circuit must be started up without the MOSFETs seeing the full input voltage for protection purposes. This paper provides a new novel control method to balance the flying capacitor with the use of current control and offers a simple startup solution to protect the MOSFETs during start up. Experimental verification shows the efficiency gains and inductance reduction.
94 citations
TL;DR: A new multi-loop delta-sigma modulator which overcomes the necessity of high DC gain opamps that were needed in previous multi- Loop modulators and combines stability advantage of the multi- loop structure with relaxed circuit requirement of the single-loop modulator.
Abstract: This paper presents a new multi-loop delta-sigma modulator which overcomes the necessity of high DC gain opamps that were needed in previous multi-loop modulators. Enabling the use of low gain opamps also allows low-voltage operation due to the reduced number of transistors between the power supply rails. In addition, all the digital filters are removed from the output of this modulator to minimize the overall system requirement. Instead, an in-loop digital addition facilitates the desired noise transfer functions of both loops. This combines stability advantage of the multi-loop structure with relaxed circuit requirement of the single-loop modulator. A fourth order modulator is implemented in a 0.18 mum CMOS technology to demonstrate this concept. Measurement results show that, with open-loop opamp gain of less than 35 dB, the implemented prototype IC achieves over 74 dB SNDR at an oversampling ratio of 16. The sampling frequency is 20 MHz and the total power dissipation is 3.2 mW at 1.2 V supply.
87 citations
Dissertation•
01 Jan 2009
TL;DR: A new startup technique is presented that allows CMOS circuits to interface directly with and extract power out of thermoelectric generators without the need for an external battery, clock or reference generators.
Abstract: Portable electronics have fueled the rich emergence of new applications including multi-media handsets, ubiquitous smart sensors and actuators, and wearable or implantable biomedical devices. New ultra-low power circuit techniques are constantly being proposed to further improve the energy efficiency of electronic circuits. A critical part of these energy conscious systems are the energy processing and power delivery circuits that interface with the energy sources and provide conditioned voltage and current levels to the load circuits. These energy processing circuits must maintain high efficiency and reduce component count for the final solution to be attractive from an energy, size and cost perspective. The first part of this work focuses on the development of on-chip voltage scalable switched capacitor DC-DC converters in digital CMOS processes. The converters are designed to deliver regulated scalable load voltages from 0.3V up to the battery voltage of 1.2V for ultra-dynamic voltage scaled systems. The efficiency limiting mechanisms of these on-chip DC-DC converters are analyzed and digital circuit techniques are proposed to tackle these losses. Measurement results from 3 test-chips implemented in 0.18μm and 65nm CMOS processes will be provided. The converters are able to maintain >75% efficiency over a wide range of load voltage and power levels while delivering load currents up to 8mA. An embedded switched capacitor DC-DC converter that acts as the power delivery unit in a 65nm subthreshold microcontroller system will be described. The remainder of the thesis deals with energy management circuits for battery-less systems. Harvesting ambient vibrational, light or thermal energy holds much promise in realizing the goal of a self-powered system. The second part of the thesis identifies problems with commonly used interface circuits for piezoelectric vibration energy harvesters and proposes a rectifier design that gives more than 4X improvement in output power extracted from the piezoelectric energy harvester. The rectifier designs are demonstrated with the help of a test-chip built in a 0.35μm CMOS process. The inductor used within the rectifier is shared efficiently with a multitude of DC-DC converters in the energy harvesting chip leading to a compact, cost-efficient solution. The DC-DC converters designed as part of a complete power management solution achieve efficiencies of greater than 85% even in the micro-watt 3 power levels output by the harvester. The final part of the thesis deals with thermal energy harvesters to extract electrical power from body heat. Thermal harvesters in body-worn applications output ultra-low voltages of the order of 10’s of milli-volts. This presents extreme challenges to CMOS circuits that are powered by the harvester. The final part of the thesis presents a new startup technique that allows CMOS circuits to interface directly with and extract power out of thermoelectric generators without the need for an external battery, clock or reference generators. The mechanically assisted startup circuit is demonstrated with the help of a test-chip built in a 0.35μm CMOS process and can work from as low as 35mV. This enables load circuits like processors and radios to operate directly of the thermoelectric generator without the aid of a battery. A complete power management solution is provided that can extract electrical power efficiently from the harvester independent of the input voltage conditions. With the help of closed-loop control techniques, the energy processing circuit is able to maintain efficiency over a wide range of load voltage and process variations. Thesis Supervisor: Anantha P. Chandrakasan Title: Professor of Electrical Engineering and Computer Science
75 citations
06 Nov 2009
TL;DR: In this paper, an algebraic model that describes the operation of binary Switched-Capacitor Converters (SCC) was developed and generalized to any radix case.
Abstract: An algebraic model that describes the operation of binary Switched-Capacitor Converters (SCC) was developed and generalized to any radix case. The proposed approach reduces the power loss by increasing the number of target voltages. In the binary case, the flying capacitors are automatically kept charged to binary weighted voltages and consequently, the resolution of the possible target voltages is binary. The paper presents the underlining theory of the proposed SCC and two new control methods to regulate the output voltage. It is shown that the theoretical formulation of the new number systems can describe many SCC circuits on the market and can help design new SCC with a larger number of target voltages. The theoretical results were verified for the binary case by simulation and experimentally. Excellent agreement was found between the theory and experimental results. The down side of the proposed SCC schemes is the relatively large number of switches which makes the approach more suitable for low power applications.
TL;DR: The practical effectiveness of the proposed soft-switching dc-dc converter is demonstrated by the experimental results from an 800 W - 55 kHz prototype, and the feasibility of the dc-DC converter topology is proved from the viewpoints of the high efficiency and high power density.
Abstract: This paper presents a novel soft-switching half-bridge dc-dc converter with high-frequency link. The newly proposed soft-switching dc-dc converter consists of a single-ended half-bridge inverter controlled by an asymmetrical pulsewidth-modulation scheme and a center-tapped diode rectifier. In order to attain the wide range of soft commutation under constant switching frequency, the single active edge-resonant snubber cell composed of a lossless inductor and a switched capacitor is employed for the half-bridge inverter leg, providing and assisting zero-current-switching operations in the switching power devices. The practical effectiveness of the proposed soft-switching dc-dc converter is demonstrated by the experimental results from an 800 W - 55 kHz prototype. In addition, the feasibility of the dc-dc converter topology is proved from the viewpoints of the high efficiency and high power density.
Patent•
19 Jun 2009
TL;DR: In this article, a switched capacitor notch filter for sampling an input signal using multiple sampling capacitors and multiple non-overlapping time periods was proposed, where the charge from the sampling capacitor is averaged and transferred to the filter output during another non-off-the-shelf time period.
Abstract: A switched capacitor notch filter for sampling an input signal using multiple sampling capacitors and multiple non-overlapping time periods. The charge from the sampling capacitors is averaged and transferred to the filter output during another non-overlapping time period.
TL;DR: The (SC) circuits theory is revisited, and a new approach of modeling, which gives an accurate nonlinear description of their operation is discussed, and the resulting solution shows that a nonlinear approach can deliver an improved performance in the dynamic and steady-state behavior.
Abstract: Switched-capacitor (SC) converters are a type of variable structure systems. The conventional approach of maintaining regulation in these converters is a feedback control developed from linear systems theory, and it is based on the approximate small-signal linearized models of these circuits. However, the simplicity of such an approach sacrifices performance (poor transient response and sometimes steady-state instability are the result of a design based on the use of an approximate linearization) for convenience and cost. This paper discusses the (SC) converters from the viewpoint of nonlinear systems, and based on this, takes a variable structure feedback approach. The (SC) circuits theory is revisited, and a new approach of modeling, which gives an accurate nonlinear description of their operation is discussed. Based on the principle of energy balance applied to the output filter capacitor, an exact relationship between the instantaneous output and input currents in the charging and discharging phases is derived, leading to the derivation of a unique large-signal dynamic model for both alternative operating phases. Together with a defined switching function, it forms the proposed variable structure model. The resulting solution shows that a nonlinear approach can deliver an improved performance in the dynamic and steady-state behavior. Experimental results performed on a two-phase (SC) converter verify the theory.
TL;DR: In this paper, a second-order delta-sigma (DeltaSigma) modulator is presented, which utilizes a common-mode feedback circuit to balance the pull-up current and the pulldown current in the ramp generator.
Abstract: In this brief, a fully differential comparator-based switched-capacitor (CBSC) second-order delta-sigma (DeltaSigma) modulator is presented. To ensure differential operation, the CBSC DeltaSigma modulator utilizes a common-mode feedback circuit to balance the pull-up current and the pull-down current in the ramp generator. This modulator has been fabricated in a standard 0.18-mum CMOS process. The active area is 0.21 mm2, and the power consumption, excluding output buffers, is 0.42 mW from a 1.8-V supply. This modulator achieves 65.3-dB signal-to-noise-plus-distortion ratio and an input dynamic range of 71 dB when sampled at 2.56 MS/s (OSR = 64).
01 Nov 2009
TL;DR: A resonant switched-capacitor converter for voltage balancing of several capacitor or battery modules connected in series is described, resulting in a reduction of power loss and EMI and a phase-shift control method enables to improve its voltage-regulation performance.
Abstract: This paper describes a resonant switched-capacitor converter (RSCC) for voltage balancing of several capacitor or battery modules connected in series This voltage balancing circuit transfers electric charge between the capacitor modules with a soft switching operation, resulting in a reduction of power loss and EMI Moreover, a phase-shift control method enables to improve its voltage-regulation performance Its current loops are analyzed in a circuit configuration which has more than three capacitor modules Based on the analysis, a new controller is designed to improve the transient response Experimental results confirm the validity and effectiveness of the proposed control method
TL;DR: A modified switched-capacitor (SC) feedback DAC technique, with a variable switched series resistor (SR), which has the additional benefit of reducing the typically high SC DAC output peak currents, resulting in reduced slew-rate requirements for the loop-filter integrators.
Abstract: The performance of traditional continuous-time (CT) delta-sigma (DeltaSigma) analog-to-digital converters (ADCs) is limited by their large sensitivity to feedback pulse-width variations caused by clock jitter in their feedback digital-to-analog converters (DACs). To mitigate that effect, we propose a modified switched-capacitor (SC) feedback DAC technique, with a variable switched series resistor (SR). The architecture has the additional benefit of reducing the typically high SC DAC output peak currents, resulting in reduced slew-rate requirements for the loop-filter integrators. A theoretical investigation is carried out which provides new insight into the synthesis of switched-capacitor with switched series resistor (SCSR) DACs with a specified reduction of the pulse-width jitter sensitivity and minimal power consumption and complexity. To demonstrate the concept and to verify the reduced pulse-width jitter sensitivity a 5 mW, 312 MHz, second order, low-pass, 1-bit, CT DeltaSigma modulator with SCSR feedback was implemented in a 1.2 V, 90 nm, RF-CMOS process. An SNR of 66.4 dB and an SNDR of 62.4 dB were measured in a 1.92 MHz bandwidth. The sensitivity to wideband clock phase noise was reduced by 30 dB compared to a traditional switched-current (SI) return-to-zero (RZ) DAC.
IBM1
TL;DR: A wideband LC PLL in 45-nm SOI CMOS technology is presented that has a center frequency of 12.4 GHz and 1.2 octave locking range and has a power consumption of 25 mW at the highest oscillation frequency.
Abstract: A wideband LC PLL in 45-nm SOI CMOS technology is presented that has a center frequency of 12.4 GHz and 1.2 octave locking range. The wideband operation is achieved by switching mutual inductances within the inductor coil of the LC oscillator. To minimize resistive switching losses, the inductor coil consists of a non-switchable primary coil and two isolated secondary coils with series switches. When the switches are closed, the overall inductance reduces because of the switched mutual inductances. Three inductor bands, each consisting of 16 switched capacitor sub-bands, span a frequency range from 7.3 to 17.5 GHz. The in-band phase noise measured after a 1/4 divider is better than -107 dBc/Hz at 1 MHz offset frequency in the entire locking range. The PLL is fully differential and its core has a power consumption of 25 mW at the highest oscillation frequency.
24 May 2009
TL;DR: This silicon neuron is presented which is based on a modified version of the Mihalas-Niebur neural model and has low complexity and reliable matching and can thus be easily integrated into more complex neuromorphic systems.
Abstract: In this paper we present the circuits and simulation results for a silicon neuron which is based on a modified version of the Mihalas-Niebur neural model [1]. This silicon neuron produces 15 of the 20 known neural spiking and bursting behaviors. It has low complexity and reliable matching and can thus be easily integrated into more complex neuromorphic systems. Implemented in a 0.15um 1.5V CMOS process, each neuron consumes about 7.5nW of power at 1kHz and occupies an area of 70um by 70um.
TL;DR: In this paper, the authors proposed a low-ripple and dual-phase charge pump circuit regulated by switched-capacitor-based bandgap reference, which can reduce the output voltage ripple by means of only one closed-loop regulation.
Abstract: This paper proposes a low-ripple and dual-phase charge pump circuit regulated by switched-capacitor-based bandgap reference. Due to design of a buffer stage, a system can have better bandwidth and phase margin, and thus, the transient response and driving capability can be improved. Besides, the dual-phase control can reduce the output voltage ripple by means of only one closed-loop regulation in order to improve the power conversion efficiency. Besides, the proposed automatic body switching (ABS) circuit can efficiently drive the bulk of the power p-type MOSFETs to avoid leakage and potential latch-up. Usually, the regulated charge pump circuit needs a bandgap reference circuit to provide a temperature-independent reference voltage. The switched-capacitor-based bandgap reference circuit is utilized to regulate the output voltage. This chip was fabricated by Taiwan Semiconductor Manufacturing Company (TSMC) 0.35 mum 3.3 V/5 V 2P4M CMOS technology. The input voltage range varies from 2.9 to 5.5 V, and the output voltage is regulated at 5 V. Experimental results demonstrate that the charge pump can provide 48 mA maximum load current without any oscillation problems.
Patent•
07 May 2009
TL;DR: In this article, the output of a voltage source which provides the other bias voltage for the capacitive transducer may be filtered by a low pass filter, which may be a switched capacitor filter circuit.
Abstract: A capacitive transducer circuit comprises a capacitive transducer having first and second electrodes. The first and second electrodes are biased by respective first and second bias voltages. An amplifier is connected to receive a first analogue signal on an input terminal, the first analogue signal being generated by the capacitive transducer, and to generate a second analogue signal on an output terminal. A digital feedback circuit is connected between the output terminal of the amplifier and the input terminal of the amplifier. The digital feedback circuit is configured to provide one of said first or second bias voltages. The output of a voltage source which provides the other bias voltage for the capacitive transducer may be filtered by a low pass filter. The low pass filter may comprise a switched capacitor filter circuit.
TL;DR: Compared with previous analog techniques, the proposed digital implementation achieves a 91% reduction in quiescent power consumption with improved tolerance to process-voltage-temperature (PVT) variation and tuning capability for obtaining the optimal switching threshold.
Abstract: On-chip resonant supply noise in the mid-frequency range (i.e., 50-300 MHz) has been identified as the dominant supply noise component in modern microprocessors. To overcome the limited efficiency of conventional decoupling capacitors in reducing the resonant supply noise, this paper proposes a low-power digital switched decoupling capacitor circuit. By adaptively switching the connectivity of decaps according to the measured supply noise, the amount of charge provided by the decaps is dramatically boosted leading to an increased damping of the on-chip supply network. Analysis on the charge transfer during the switching events shows a 6-13X boost of effective decap value. Simulations verify the enhanced noise decoupling performance as well as the effective suppression of the first-droop noise. A 0.13 mum test chip including an on-chip resonance generation circuit and on-chip supply noise sensors was built to demonstrate the proposed switched decap circuit. Measurements confirm an 11X boost in effective decap value and a 9.8 dB suppression in supply noise using the proposed circuit. Compared with previous analog techniques, the proposed digital implementation achieves a 91% reduction in quiescent power consumption with improved tolerance to process-voltage-temperature (PVT) variation and tuning capability for obtaining the optimal switching threshold.
TL;DR: A 0.6-V 34-muW delta-sigma modulator implemented by using a standard 0.13-mum complementary metal-oxide-semiconductor technology and a high-performance low-quiescent amplifier architecture is developed for the modulator, which achieves a dynamic range of 83 dB, a peak signal-to-noise ratio of 82 dB, and a peak Signal-To-Noise-plus-distortion ratio of 81 dB.
Abstract: A 0.6-V 34-muW delta-sigma modulator implemented by using a standard 0.13-mum complementary metal-oxide-semiconductor technology is presented. This brief analyzes a subthreshold-leakage current problem in switched-capacitor circuits and proposes subthreshold-leakage suppression switches to solve the problem. To verify the operation of the subthreshold-leakage suppression switches, two different fifth-order delta-sigma modulators are implemented with conventional switches and new switches. The input feedforward architecture is used to reduce the voltage swings of the integrators. A high-performance low-quiescent amplifier architecture is developed for the modulator. The modulator, with new switches, achieves a dynamic range of 83 dB, a peak signal-to-noise ratio of 82 dB, and a peak signal-to-noise-plus-distortion ratio of 81 dB in a signal bandwidth of 20 kHz. The power consumption is 34 muW for the modulator, and the core chip size is 0.33 mm2 .
TL;DR: In this article, an RF energy scavenging circuit implementing a power matched Villard voltage doubler followed by a switched capacitor DC-DC converter for scavenging ultra-low RF power levels (20 dBm) is presented.
Abstract: An RF energy scavenging circuit implementing a power matched Villard voltage doubler followed by a switched capacitor DC-DC converter for scavenging ultra-low RF power levels (20 dBm) is presented. Measurement results for the circuit, fabricated in a 130 nm CMOS process, show that 1 V can be generated across a 5 M load from as little as 25.5 Bm of input RF energy at 2.2 GHz. This represents a 9.5 dB improvement, over the measured sensitivity of our RF energy scavenging circuit without the use of a switched capacitor DC-DC converter stage.
TL;DR: A reconfigurable sigma-delta modulator, which is able to support the predictable standards for the fourth generation (4G) of mobile communication systems, is presented in this paper.
TL;DR: Model techniques for accurate estimation of settling errors in switched-capacitor (SC) circuits built with Miller-compensated operational transconductance amplifiers (OTAs) are presented and design procedures for dimensioning SC building blocks are presented whose targets are system-level specifications (such as ENOB and SNDR) instead of OTA specifications.
Abstract: We present modeling techniques for accurate estimation of settling errors in switched-capacitor (SC) circuits built with Miller-compensated operational transconductance amplifiers (OTAs). One distinctive feature of the proposal is the computation of the impact of signal levels (on both the model parameters and the model structure) as they change during transient evolution. This is achieved by using an event-driven behavioral approach that combines small- and large-signal behavioral descriptions and keeps track of the amplifier state after each clock phase. Also, SC circuits are modeled under closed-loop conditions to guarantee that the results remain close to those obtained by electrical simulation of the actual circuits. Based on these models, which can be regarded as intermediate between the more established small-signal approach and full-fledged simulations, design procedures for dimensioning SC building blocks are presented whose targets are system-level specifications (such as ENOB and SNDR) instead of OTA specifications. The proposed techniques allow to complete top-down model-based designs with 0.3-b accuracy.
TL;DR: In this paper, a dual-branch 1.8 V to 3.3 V voltage doubler with an embedded low dropout regulator is presented, where the power switches are individually controlled by their phase signals using a phase-delayed gate drive scheme, and are turned on and off in proper sequence to eliminate both short-circuit and reversion currents during phase transitions.
Abstract: A dual-branch 1.8 V to 3.3 V regulated switched-capacitor voltage doubler with an embedded low dropout regulator is presented. For the power stage, the power switches are individually controlled by their phase signals using a phase-delayed gate drive scheme, and are turned on and off in proper sequence to eliminate both short-circuit and reversion currents during phase transitions. For the regulator, the two branches operate in an interleaving fashion to achieve continuous output regulation with small output ripple voltage. Dual-loop feedback capacitor multiplier is adopted for loop compensation and a P-switch super source follower with high current sinking capability is inserted to drive switching capacitive load, and push the pole at the gate of the output power transistor to high frequency for better stability. The regulated doubler has been fabricated in a 0.35 mum CMOS process. It operates at a switching frequency of 500 kHz with an output capacitor of 2 muF , and the maximum output voltage ripple is only 10 mV for a load current that ranges from 10 mA to 180 mA. The load regulation is 0.0043%/mA, and the load transient is 7.5 mus for a load change of 160 mA to 10 mA, and 25 mus for a load change of 10 mA to 160 mA.
10 May 2009
TL;DR: The design and the performance of several key elements are detailed and the deployment of the front-end electronics on the first time projection chamber where the final tests before installation on-site are being conducted.
Abstract: The tracker of the near detector in the T2K neutrino oscillation experiment comprises three time projection chambers based on micro-pattern gaseous detectors. A new readout system is being developed to amplify condition and acquire in real time the data produced by the 124,000 detector channels. The cornerstone of the system is a 72-channel application specific integrated circuit which is based on a switched capacitor array. Using analog memories combined to digitization deferred in time enables reducing the initial burstiness of traffic from 50 Tbps to 400 Gbps in a practical manner and with a very low power budget. Modern field programmable gate arrays coupled to commercial digital memories are the next elements in the chain. Multi-gigabit optical links provide 140 Gbps of aggregate bandwidth to carry data outside of the magnet surrounding the detector to concentrator cards that pack data and provide the interface to commercial PCs via a standard Gigabit Ethernet network. We describe the requirements and constraints for this application and justify our technical choices. We detail the design and the performance of several key elements and show the deployment of the front-end electronics on the first time projection chamber where the final tests before installation onsite are being conducted.
Proceedings Article•
01 Jan 2009
TL;DR: In this paper, a dual-branch 1.8 V to 3.3 V voltage doubler with an embedded low dropout regulator is presented, which operates at a switching frequency of 500 kHz with an output capacitor of 2 μF.
Abstract: A dual-branch 1.8 V to 3.3 V regulated switched-capacitor voltage doubler with an embedded low dropout regulator is presented. For the power stage, the power switches are individually controlled by their phase signals using a phase-delayed gate drive scheme, and are turned on and off in proper sequence to eliminate both short-circuit and reversion currents during phase transitions. For the regulator, the two branches operate in an interleaving fashion to achieve continuous output regulation with small output ripple voltage. Dual-loop feedback capacitor multiplier is adopted for loop compensation and a P-switch super source follower with high current sinking capability is inserted to drive switching capacitive load, and push the pole at the gate of the output power transistor to high frequency for better stability. The regulated doubler has been fabricated in a 0.35 μm CMOS process. It operates at a switching frequency of 500 kHz with an output capacitor of 2 μF, and the maximum output voltage ripple is only 10 mV for a load current that ranges from 10 mA to 180 mA. The load regulation is 0.0043%/mA, and the load transient is 7.5 μs for a load change of 160 mA to 10 mA, and 25 μs for a load change of 10 mA to 160 mA.
24 May 2009
TL;DR: To improve control performance and avoid the use of small-signal linearization in the control design, a large-signals approach is adopted for modeling the converter, allowing for a design of a sliding mode control.
Abstract: The switched-capacitor converters are ideal switching-mode power supplies for portable electronic consumers due to their light weight, small size, and high power density. However, they suffer from a discontinuous input current waveform with large di/dt, what leads to significant electromagnetic interference (EMI) emission. This paper proposes a configuration of switched-capacitor converters connected in parallel with their inputs and outputs interleaved. The interleaving times are calculated by taking into account the fast capacitor-charging characteristic, and the need to have the nominal operating point on its linear part for increasing the regulation range at changes in the input voltage and load. To improve control performance and avoid the use of small-signal linearization in the control design, a large-signal approach is adopted for modeling the converter, allowing for a design of a sliding mode control.