Showing papers on "Switched capacitor published in 2010"

Fractional Order Systems: Modeling and Control Applications

Abstract: Fractional Order Systems Fractional Order PID Controller Chaotic Fractional Order Systems Field Programmable Gate Array, Microcontroller and Field Programmable Analog Array Implementation Switched Capacitor and Integrated Circuit Design Modeling of Ionic Polymeric Metal Composite

Charge Pump Circuits: An Overview on Design Strategies and Topologies

Abstract: Due to the continuous power supply reduction, charge pumps circuits are widely used in integrated circuits (ICs) devoted to several kind of applications such as smart power, nonvolatile memories, switched capacitor circuits, operational amplifiers, voltage regulators, SRAMs, LCD drivers, piezoelectric actuators, RF antenna switch controllers, etc. The main focus of this tutorial manuscript is to provide a deep understanding of the charge pumps behavior, to present useful models and key parameters and to organically and in details discuss the optimized design strategies. Finally, an overview of the main different topologies is also included.

Application of the DRS chip for fast waveform digitizing

Abstract: The high demands of modern experiments in fast waveform digitizing led to the development of a whole family of switched capacitor arrays (SCA), called the Domino Ring Sampler (DRS). The most recent version, DRS4, is produced in a radiation hard 0.25 μm CMOS process, and is capable of digitizing 9 differential input channels at sampling rates of up to 6 Giga-samples per second (GSPS) with an analogue bandwidth of 950 MHz (−3 dB). The channel depth can be configured between 1024 and 8192 cells, and the signal-to-noise ratio allows a resolution equivalent to more than 11 bits. Using an interleaved sampling technique, sampling rates up to 48 GSPS are possible. Compared with the previous versions, the DRS4 chip contains several improvements such as an on-chip PLL for sampling-frequency stabilization and various mechanisms to reduce the read out dead-time. The high bandwidth, low power consumption and short readout time make this chip attractive for many experiments, replacing traditional ADCs and TDCs. This includes time-of-flight detectors, cosmic gamma ray observatories, PET scanners and industrial applications.

A Fully-Integrated Switched-Capacitor Step-Down DC-DC Converter With Digital Capacitance Modulation in 45 nm CMOS

Abstract: Implementing efficient and cost-effective power regulation schemes for battery-powered mixed-signal SoCs is a key focus in integrated circuit design. This paper presents a fully-integrated switched-capacitor DC-DC converter in 45 nm digital CMOS technology. The proposed implementation uses digital capacitance modulation instead of traditional PFM and PWM control methods to maintain regulation against load current changes. This technique preserves constant frequency switching while also scaling switching and bottom-plate losses with changes in load current. Therefore, high efficiency can be achieved across different load current levels while maintaining a predictable switching noise behavior. The converter occupies only 0.16 mm2, and operates from 1.8 V input. It delivers a programmable sub-1 V power supply with efficiency as high as 69% and load current between 100 μA and 8 mA. Measurement results confirm the theoretical basis of the proposed design.

A 32nm fully integrated reconfigurable switched-capacitor DC-DC converter delivering 0.55W/mm 2 at 81% efficiency

Abstract: With the rising integration levels used to increase digital processing performance, there is a clear need for multiple independent on-chip supplies in order to support per-IP or block power management. Simply adding multiple off-chip DCDC converters is not only difficult due to supply impedance concerns, but also adds cost to the platform by increasing motherboard size and package complexity. There is therefore a strong motivation to integrate voltage conversion blocks on the silicon chip.

A fully-integrated switched-capacitor 2∶1 voltage converter with regulation capability and 90% efficiency at 2.3A/mm 2

Abstract: A switched-capacitor DC-DC voltage converter in 45nm SOI CMOS leverages on-chip trench capacitors to achieve 90% efficiency at an output of 2.3A/mm2 for 2V-to-0.95V conversion at 100MHz. Operation in step-up and step-down modes is demonstrated. Combined with stacked voltage domains, self-regulation capability enables further efficiency improvement.

Generalized multi-cell switched-inductor and switched-capacitor Z-source inverters

Abstract: High performance voltage and current-source inverters (VSI and CSI) are widely required in various industrial applications such as servo-motor drives, special power supplies, distributed power systems and hybrid electric vehicles. However, the traditional VSI and CSI have been seriously restricted due to their narrow obtainable output voltage range, short-through problems caused by misgating and some other theoretical difficulties due to their bridge-type structures. The Z-source inverter was proposed to overcome the problems associated with the traditional inverters, in which the functions of the traditional dc-dc boost converter and the bridge-type inverter have been successfully combined. To further widen the operational range or gain of the Z-source inverter in both the voltage and current type configurations, the generalized switched-inductor and switched-capacitor impedance networks are proposed hereon. Both simulation and experimental testing have been conducted for validating the extra boosting introduced with some representative results captured and presented near the end of the paper.

Zero-Current-Switching Multilevel Modular Switched-Capacitor DC–DC Converter

Abstract: This paper presents a quasi-resonant technique for multilevel modular switched-capacitor dc-dc converter (MMSCC) to achieve zero-current switching (ZCS) without increasing cost and sacrificing reliability. This ZCS-MMSCC employs stray inductance distributed in the circuit as the resonant inductor to resonate with the capacitor and provide low dv /dt and di /dt switching transition for the device. The ZCS-MMSCC does not utilize any additional components to achieve ZCS and meanwhile solves the current and voltage spike problem during the switching transition, thus leading to reliable and high-efficiency advantages over traditional MMSCC. Furthermore, the ZCS-MMSCC reduces the capacitance needed in the circuit to attain high efficiency. In this case, the bulky capacitor bank with high capacitance in a traditional MMSCC to reduce voltage difference and achieve high efficiency is no longer necessary. A 150-W four-level ZCS-MMSCC prototype has been built. Simulation and experimental results are given to demonstrate the validity and features of the proposed soft-switching switched-capacitor circuit.

Design and Application for PV Generation System Using a Soft-Switching Boost Converter With SARC

Abstract: In order to improve the efficiency of energy conversion for a photovoltaic (PV) system, a soft-switching boost converter using a simple auxiliary resonant circuit, which is composed of an auxiliary switch, a diode, a resonant inductor, and a resonant capacitor, is adopted in this paper. The conventional boost converter decreases the efficiency because of hard switching, which generates losses when the switches are turned on/off. During this interval, all switches in the adopted circuit perform zero-current switching by the resonant inductor at turn-on, and zero-voltage switching by the resonant capacitor at turn-off. This switching pattern can reduce the switching losses, voltage and current stress of the switching device. Moreover, it is very easy to control. In this paper, we have analyzed the operational principles of the adopted soft-switching boost converter, and it is designed for PV generation system. Simulation and experimental results are presented to confirm the theoretical analysis.

A comparative analysis of Switched-Capacitor and inductor-based DC-DC conversion technologies

Abstract: This paper compares the performance of Switched-Capacitor (SC) and inductor-based DC-DC conversion technologies. A metric to compare between the two topologies is discussed, and is used to compare switch utilization. Fundamental limits on utilization of reactive elements developed in the literature for all DC-DC converters are also reviewed and discussed, and this analysis shows that popular SC and inductor-based converters achieve the limits of utilization for reactive components. These limits are stated in terms of the ratio of output power to required stored energy in reactive elements. A detailed analysis of available surface mount discrete components and on-die devices reveals that capacitors have substantially higher energy and power density than their magnetic counterparts. The challenging regulation task for SC converters is also discussed, with a promising strategy outlined. The SC converter is evidently a promising candidate for future high power density integrated DC-DC converters.

A family of zero current switching switched-capacitor dc-dc converters

Abstract: This paper presents a new zero current switching (ZCS) technique for a family of switched-capacitor dc-dc converters. Compared to the traditional ZCS switched-capacitor dc-dc converters by inserting a magnetic core in the circuit, these new ZCS switched-capacitor dc-dc converters employ the stray inductance present in the circuit as the resonant inductor and provide soft switching for the devices. These ZCS switched-capacitor dc-dc converters do not utilize any additional components to minimize switching loss and reduce the current and voltage spike, thus leading to high efficiency and reliable benefit over traditional switched-capacitor dc-dc converters. Moreover, the bulky capacitor bank existing in traditional switched-capacitor circuits for high power high current application to achieve high efficiency was reduced significantly. Small size, low capacitance, low ESR, high current rating and high temperature rating ceramic capacitors can be employed. Therefore, by using proposed ZCS technique, small size, high power density, high efficiency, high temperature rating, and high current rating switched-capacitor dc-dc converter could be built. Simulation and experimental results are given to demonstrate the validity and features of the soft switching switched-capacitor dc-dc converters.

Flying-Capacitor-Based Chopper Circuit for DC Capacitor Voltage Balancing in Diode-Clamped Multilevel Inverter

Abstract: This paper proposes a flying-capacitor-based chopper circuit for dc capacitor voltage equalization in diode-clamped multilevel inverters. Its important features are reduced voltage stress across the chopper switches, possible reduction in the chopper switching frequency, improved reliability, and ride-through capability enhancement. This topology is analyzed using three- and four-level flying-capacitor-based chopper circuit configurations. These configurations are different in capacitor and semiconductor device count and correspondingly reduce the device voltage stresses by half and one-third, respectively. The detailed working principles and control schemes for these circuits are presented. It is shown that, by preferentially selecting the available chopper switch states, the dc-link capacitor voltages can be efficiently equalized in addition to having tightly regulated flying-capacitor voltages around their references. The various operating modes of the chopper are described along with their preferential selection logic to achieve the desired performances. The performance of the proposed chopper and corresponding control schemes are confirmed through both simulation and experimental investigations.

A Novel Control Technique for a Switched-Capacitor-Converter-Based Hybrid Electric Vehicle Energy Storage System

Abstract: This paper presents the analysis and novel controller design for a hybrid switched-capacitor bidirectional dc/dc converter. Features of voltage step-down, step-up, and bidirectional power flow are integrated into a single circuit. The novel control strategy enables simpler dynamics compared to a standard buck converter with an input filter, good regulation capability, low electromagnetic interference, lower source current ripple, ease of control, and continuous input current waveform in both modes of operation (buck and boost modes).

Power Reduction in Continuous-Time Delta-Sigma Modulators Using the Assisted Opamp Technique

Abstract: The opamp in the first integrator of a high resolution single-bit continuous-time modulator has stringent slew rate requirements, which increases power dissipation. We introduce the “assisted opamp” integrator, which is a way of achieving low distortion operation with low power consumption. We present circuit implementations of our technique for single-bit modulators using NRZ and switched-capacitor-resistor (SCR) feedback DACs. Audio modulators designed in a 0.18 μm CMOS technology are used as vehicles to demonstrate the effectiveness of our techniques. The modulator with an NRZ DAC achieves a dynamic range of 92.5 dB in a 24 kHz bandwidth and dissipates 110 μW from a 1.8 V supply. A second design, which employs an SCR-DAC, achieves a dynamic range of 91.5 dB and dissipates 122 μW. The figures of merit (FOM) of these modulators, 175.9 dB and 174.4 dB respectively, are comparable with those of state-of-the-art multibit designs.

The Switch-Mode Flying-Capacitor DC–DC Converters With Improved Natural Balancing

Abstract: This paper presents investigations of voltage-sharing stabilization with the use of passive RLC circuit in switch-mode flying capacitor DC-DC converters. Practical and simulation results and also a mathematical analysis of the balancing process in boost and buck-boost converters are presented. Analyzed converters use additional capacitors (flying capacitors), charged to proper value, for decreasing the voltage on switches and increasing the inductor-current frequency. Such advantages are achieved under proper voltage sharing on the flying capacitors. The voltages are stabilized in a natural way by the load current and with the use of external RLC circuit to force the current that flows through the converters' capacitors under unbalance state. This paper focuses on the analysis of the balancing phenomenon with the use of the external RLC circuit in these topologies. The balancing booster improves the balancing process in these converters, making it independent of the load. It can also reduce oscillations that arise in the converters in transient states.

A 3-V, 6-Bit C-2C Digital-to-Analog Converter Using Complementary Organic Thin-Film Transistors on Glass

Abstract: A 3-V, 6-bit DAC is designed using complementary organic thin-film transistors on a glass substrate. The p-channel and n-channel transistors utilize dinaphthothienothiophene (DNTT) and hexadecafluorocopperphthalocyanine (F16CuPc) as the organic semiconductors, respectively. A low-temperature process compatible with flexible plastic substrates is used to fabricate the circuit. The DAC utilizes switched capacitors to circumvent the large transistor-current variations, and a C-2C structure to avoid the large capacitances that would otherwise be required in the thin-film process. With calibration, the DAC achieves DNL and INL of less than 1 LSB at a conversion rate of 100 Hz.

A 0.16mm 2 completely on-chip switched-capacitor DC-DC converter using digital capacitance modulation for LDO replacement in 45nm CMOS

Abstract: Reducing power consumption through V DD scaling is a major trend in nanometer CMOS circuits. In modern wireless SoCs, multiple power domains operate below 1.2V and draw less than 10mA of current. Currently, these domains are powered from a 1.8V rail through a low drop-out linear regulator (LDO). The 1.8V rail is obtained from a Li-ion battery using a switching regulator with off-chip passives. It is highly inefficient to power circuit blocks that operate below 1.2V through LDOs. Switched-capacitor (SC) DC-DC converters are a viable solution to replace LDOs in some on-chip power domains but they currently occupy a large on-chip area [1]. Also, the voltage regulation schemes employed by current SC converters are either unsuitable in wireless systems or do not provide high efficiencies in on-chip use cases due to the dominance of bottom-plate and switching losses [2]. In this paper, a completely on-chip SC DC-DC converter that uses a digital capacitance modulation scheme to achieve voltage regulation is presented. The converter occupies only 0.16mm2 in total area and provides up to 8mA of current to output voltages between 0.8V to 1V from a 1.8V input while switching at 30MHz.

Multiphase multilevel modular DC-DC converter for high current high gain TEG application

Abstract: This paper presents a high efficiency zero current switching (ZCS) switched-capacitor (SC) dc-dc converter for high current high voltage gain TEG application. Compared with the traditional hard switching switched-capacitor circuits, the proposed circuit achieves ZCS for all the switches, thus minimizing the switching loss and EMI noise. The electrolytic capacitor present in the hard switching circuit to reduce the voltage ripple and achieve high efficiency is replaced with the low capacitance ceramic capacitors. Different from other ZCS SC circuits by inserting a magnetic core, the proposed circuit utilizes stray inductance present in the circuit, thus leading to small size, low cost and high reliability features. The proposed circuit also features continuous input current and low output voltage ripple. So the power loss related to the input capacitor can be minimized. High efficiency and high power density SC dc-dc converters could be made for high current and high voltage gain application by using the proposed topology. Simulation and experimental results are given to demonstrate the validity and features of the proposed topology.

Analysis of the Switched-Capacitor Dual-Slope Capacitance-to-Digital Converter

Abstract: A dual-slope capacitance-to-digital converter (CDC) that operates on the elements of a differential capacitive sensor and provides a digital output that is linearly proportional to the physical quantity being sensed by the sensor is presented and analyzed in this paper. The converter topology is so chosen that a linear digital output is obtained for not only a sensor possessing linear input-output characteristics but also a sensor possessing inverse characteristics. The digital output in the proposed converter is dependent only on, apart from the sensitivity of the sensor, a dc reference voltage. Hence, high accuracy and linearity are easily obtained by employing a precision dc reference. Since the proposed CDC is based on the popular dual-slope analog-to-digital converter structure, it possesses all the advantages (resolution, accuracy, and immunity to noise and component parameter variations) and limitations (requirement of auto-zero and low conversion speed) applicable to the dual-slope technique. A prototype built and tested for a typical differential capacitive sensor with a nominal capacitance value of 250 pF gave a worst-case error of less than 0.05%.

Enhanced Self-Lift Cûk Converter for Negative-to-Positive Voltage Conversion

Abstract: This letter introduces a new step-up dc-dc converter that provides a negative-to-positive voltage-conversion path for the negative dc-voltage source. Compared with the classical Cuk and buck-boost converters, the proposed converter increases the voltage boost ability significantly using the switched capacitor and self-lift techniques. It is featured with single power switch operation, common ground, transformerless structure, and clear energy delivery process; therefore, the relative simple structure is beneficial to potential industrial applications in future. A detailed theoretical analysis for the continuous and discontinuous conduction modes is given, and the main general aspects for circuit design are derived. A preliminary system modeling based on the flow graph is also presented for reference. Both simulation and experimental results are provided to validate the analysis results.

On Two-Phase Switched-Capacitor Multipliers With Minimum Circuit Area

Abstract: This paper compares the performance among two-phase switched-capacitor multipliers to identify the optimum topology with the smallest circuit area. The optimum number of stages is calculated for every multiplier to minimize the circuit area under the condition that a certain current is outputted with a given output voltage. Then, the circuit areas of the serial-parallel, linear (LIN), Fibonacci, and 2N multipliers are compared. Results show that the LIN cell is the best for integration because of the smallest total capacitor area and the highest current efficiency under the assumption that the parasitic capacitance is not smaller than 10% of the multiplier capacitance, and the Fibonacci cell is the best for discrete application because of the minimum number of capacitor components with moderate current efficiency under the assumption that the parasitic capacitance is not larger than 1% of the multiplier capacitance.

A differential 4-path highly linear widely tunable on-chip band-pass filter

Abstract: A passive switched capacitor RF band-pass filter with clock controlled center frequency is realized in 65nm CMOS. An off-chip transformer which acts as a balun, improves filter-Q and realizes impedance matching. The differential architecture reduces clock-leakage and suppresses selectivity around even harmonics of the clock. The filter has a constant −3dB bandwidth of 35MHz and can be tuned from 100MHz up to 1GHz. IIP3 is better than 19dBm, P 1dB =2dBm and NF≪5.5dB at P diss =2mW to 16mW.

Switched-capacitor bi-directional converter performance comparison with and without quasi-resonant zero-current switching

Abstract: The proposed quasi-resonant (QR) zero-current switching (ZCS) switched-capacitor (SC) converter is a new type of bi-directional power flow control conversion scheme. This device provides voltage conversion ratios from 2 against 1/2 (double-mode/half-mode) to n against 1/n (n-mode/1/n-mode) by adding a different number of SCs and power multi-oxide-semiconductor field-effect-transistor (MOSFET) switches with a small series-connected resonant inductor for forward and reverse schemes. The proposed QR SC converter presents low current stress and balanced resonant current advantages. The operating principle and theoretical analysis of the proposed bi-directional power conversion scheme are described in detail with circuit model analysis. The proposed device is compared with the conventional SC converter. Simulations and experimental verification are carried out to verify and compare the proposed QR ZCS SC bi-directional converter performance with the conventional device. At maximum efficiency, the proposed device can achieve 96% and 93% for the forward and reverse power flow control schemes, respectively.

Design and Analysis of an Interleaved Flyback–Forward Boost Converter With the Current Autobalance Characteristic

Abstract: An interleaved flyback-forward boost converter is proposed in this paper. The switched capacitors are used to realize the controllable voltage source function and balance the currents of the interleaved two phases without an additional current-sharing module. Voltage lift function of the switched capacitor also reduces the turns ratio of the transformers and alleviates the voltage stresses of the output diodes. As the transformers operate in flyback and forward modes alternately, part of the output energy is stored in the switched capacitors; therefore, the size of magnetic components can be reduced. Since the current falling rates of the clamping and output diodes, when they turn off, are controlled by the leakage inductance, the diode reverse-recovery problem is alleviated. Active clamp circuits are applied for the interleaved two phases to recycle the leakage energy and absorb the voltage spikes caused by the leakage inductance. The experimental results based on a 1 kW 48 to 380 V dc/dc prototype verify the effectiveness of the theoretical analysis.

Placement Optimization for Yield Improvement of Switched-Capacitor Analog Integrated Circuits

Abstract: Capacitor mismatch can generally result from two sources of error: random mismatch and systematic mismatch. Random mismatch is caused by process variation, while systematic mismatch is mainly due to an asymmetrical layout and processing gradients. A common centroid structure may be used to reduce systematic mismatch errors, but not random mismatch errors. Based on the spatial correlation model, this paper formulates the placement optimization problem of analog circuits using switched-capacitor techniques. A placement with higher correlation coefficients of the unit capacitors results in a higher acceptance rate, or chip yield. This paper proposes a heuristic algorithm that quickly and automatically derives the placement of the unit capacitors with the highest, or near-highest, correlation coefficients for yield improvement. Results show that the resultant placement derived from the proposed algorithm achieves better yield improvement than that from a common centroid approach. The proposed heuristic algorithm can be applied for any arbitrary capacitor ratios, i.e., more than two capacitors.

High step-up boost converter with coupled inductor and switched capacitor

Abstract: Many industrial applications require non-isolated high step-up single-phase DC/DC converters. Some existed conventional DC/DC converters have the disadvantages of large duty cycle, high switch voltage stress and high peak current. The proposed converter can provide very high voltage gain without extreme duty cycle due to the voltage doubler cell, which is composed of a coupled inductor, a switched capacitor and an additional diode. The converter with active clamp scheme can recycle the leakage energy. Unfortunately, it increases the topology complexity. The presented converter, which employs the passive lossless clamp circuit instead of the active clamp circuit, can achieve the similar functions and show better performance than its active-clamp counterpart. High efficiency and high power density is achieved due to the leakage energy recycle and output diode reverse-recovery alleviation.

Continuous-Time Input Pipeline ADCs

Abstract: Two continuous-time input pipeline ADC architectures are introduced. The continuous-time input approach overcomes many of the challenges associated with a pure switched-capacitor architecture. The resistive input load of the two new architectures provides a benign interface to external drive circuitry. The switched-capacitor sampling function is moved to the second stage input which greatly eases the sampling distortion requirements and obviates the need for an explicit front-end sample-and-hold function. The second ADC presented additionally provides inherent anti-alias filtering, allowing the possibility of eliminating costly anti-alias filters. This second architecture also eases the jitter requirements of the ADC clock when compared to switched capacitor pipeline ADCs. Measured results obtained from two proof of concept test chips fabricated in a 0.18 μm CMOS process validate the effectiveness of the proposed techniques.

Switched-capacitor band-pass filter of a discrete-time type, in particular for cancelling offset and low-frequency noise of switched-capacitor stages

Abstract: A band-pass filter made up by an operational amplifier and by an input circuit. The input circuit is formed by a capacitive filtering element, connected to the input of the operational amplifier; a coupling switch, coupled between an input node and the capacitive filtering element; a capacitive sampling element, coupled between the input of the filter and the input node; and a sampling switch, coupled between the input node and a reference-potential line. The coupling switch and the input sampling switch close in phase opposition according to a succession of undesired components sampling and sensing steps, so that the capacitive sampling element forms a sampler for sampling the undesired component in the undesired components sampling step, in the absence of the component of interest, and forms a subtractor of the undesired components from the input signal in the sensing step.

High-efficiency self-adjusting switched capacitor dc-dc converter with binary resolution

Abstract: Switched-Capacitor Converters (SCC) suffer from a fundamental power loss deficiency which make their use in some applications prohibitive. The power loss is due to the inherent energy dissipation when SCC operate between or outside their output target voltages. This drawback was alleviated in this work by developing two new classes of SCC providing binary and arbitrary resolution of closely spaced target voltages. Special attention is paid to SCC topologies of binary resolution. Namely, SCC systems that can be configured to have a no-load output to input voltage ratio that is equal to any binary fraction for a given number of bits. To this end, we define a new number system and develop rules to translate these numbers into SCC hardware that follows the algebraic behavior. According to this approach, the flying capacitors are automatically kept charged to binary weighted voltages and consequently the resolution of the target voltages follows a binary number representation and can be made higher by increasing the number of capacitors (bits). The ability to increase the number of target voltages reduces the spacing between them and, consequently, increases the efficiency when the input varies over a large voltage range. The thesis presents the underlining theory of the binary SCC and its extension to the general radix case. Although the major application is in step-down SCC, a simple method to utilize these SCC for step-up conversion is also described, as well as a method to reduce the output voltage ripple. In addition, the generic and unified model is strictly applied to derive the SCC equivalent resistor, which is a measure of the power loss. The theoretical predictions are verified by simulation and experimental results.

Switched capacitor charge pump reduces hysteresis of piezoelectric actuators over a large frequency range

Abstract: Piezoelectric actuators exhibit large hysteresis between the applied voltage and their displacement A switched capacitor charge pump is proposed to reduce hysteresis and linearize the movement of piezoelectric actuators By pumping the same amount of charges into the piezoelectric actuator quantitatively, the actuator will be forced to change its length with constant step Compared with traditional voltage and charge driving, experimental results demonstrated that the piezoelectric stack driven by the charge pump had less hysteresis over a large frequency range, especially at ultralow frequencies A hysteresis of less than 201% was achieved over a frequency range of 001–20 Hz using the charge pump driver