Showing papers on "Switched capacitor published in 2013"
TL;DR: In this article, the authors provide a perspective on progress toward realization of efficient, fully integrated dc-dc conversion and regulation functionality in CMOS platforms, and provide a comparative assessment between inductor-based and switched-capacitor approaches.
Abstract: This paper provides a perspective on progress toward realization of efficient, fully integrated dc-dc conversion and regulation functionality in CMOS platforms. In providing a comparative assessment between the inductor-based and switched-capacitor approaches, the presentation reviews the salient features in effectiveness in utilization of switch technology and in use and implementation of passives. The analytical conclusions point toward the strong advantages of the switched-capacitor (SC) approach with respect to both switch utilization and much higher energy densities of capacitors versus inductors. The analysis is substantiated with a review of recently developed and published integrated dc-dc converters of both the inductor-based and SC types.
286 citations
TL;DR: In this paper, a class of distributed power converters for photovoltaic (PV) energy optimization is discussed, which operate in a parallelladder architecture, enforcing voltage ratios among strings of cells at terminals normally connected to bypass diodes.
Abstract: This paper discusses the theory and implementation of a class of distributed power converters for photovoltaic (PV) energy optimization. Resonant switched-capacitor converters are configured in parallel with strings of PV cells at the sub-module level to improve energy capture in the event of shading or mismatch. The converters operate in a parallel-ladder architecture, enforcing voltage ratios among strings of cells at terminals normally connected to bypass diodes. The balancing function extends from the sub-module level to the entire series string through a dual-core cable and connector. The parallel configuration allows converters to handle only mismatch power and turn off if there is no mismatch in the array. Measurement results demonstrate insertion loss below 0.1% and effective conversion efficiency above 99% for short-circuit current mismatch gradients up to 40%. The circuit implementation eliminates large power magnetic components, achieving a vertical footprint less than 6 mm. The merits of a resonant topology are compared to a switched-capacitor topology.
261 citations
TL;DR: In this paper, a generic modeling methodology that analyzes the losses in switched capacitor converters (SCC) operating in open loop was developed and verified by simulation and experiments, which can help in the optimization of SCC systems and their control to achieve high efficiency and the desired regulations.
Abstract: A generic modeling methodology that analyzes the losses in switched capacitor converters (SCC) operating in open loop was developed and verified by simulation and experiments. The proposed analytical approach is unified, covering both hard- and soft-SCC topologies that include active switches and/or diodes. An important feature of the proposed model is that it expresses the losses as a function of the average currents passing through each flying capacitor during each switching phase. Since these currents are linearly proportional to the output current, the model is also applicable to SCC with multiple capacitors if it can be assumed that each of the subcircuits of the modeled SCC can be described or approximated by a first-order system. The proposed model can be used to assess the effect of the operational conditions of the SCC, such as switching frequency and duty cycle, on the expected losses. As such, the model can help in the optimization of SCC systems and their control to achieve high efficiency and the desired regulations.
143 citations
TL;DR: In this article, the state-of-the-art of integrated switched-capacitor and inductive power converters is surveyed and compared in terms of the main specifications and performance metrics, thereby allowing a categorization and providing applicationoriented design guidelines.
Abstract: This paper surveys and discusses the state-of-the-art of integrated switched-capacitor and inductive power converters. After introducing applications that drive the need for integrated switching power converters, implementation issues to be addressed for integrated switched-capacitor and inductive converters are given, as well as design examples. At the end of this paper, a comprehensive set of integrated power converters are compared in terms of the main specifications and performance metrics, thereby allowing a categorization and providing application-oriented design guidelines.
135 citations
28 Mar 2013
TL;DR: High efficiency conversion is achieved by combining the Fe-Caps with multi-gain setting converter in a reconfigurable architecture with dynamic gain selection and achieving a peak efficiency of 90%.
Abstract: Dynamic Voltage Scaling (DVS) has become one of the standard techniques for energy efficient operation of systems by powering circuit blocks at the minimum voltage that meets the desired performance [1]. Switched Capacitor (SC) DC-DC converters have gained significant interest as a promising candidate for an integrated energy conversion solution that eliminates the need for inductors [2,3]. However, SC converters efficiency is limited by the conduction loss, bottom plate parasitic capacitance, gate drive loss in addition to the overhead of the control circuit. Reconfigurable SC converters supporting multi-gain settings have been proposed to allow efficient operation across wide output range [2,4]. Also, High density deep trench capacitors with low bottom plate parasitic capacitance have been utilized in [5] achieving a peak efficiency of 90%. In this work, we exploit on-chip ferroelectric capacitors (Fe-Caps) for charge transfer owing to their high density and extremely low bottom plate parasitic capacitance [6]. High efficiency conversion is achieved by combining the Fe-Caps with multi-gain setting converter in a reconfigurable architecture with dynamic gain selection.
122 citations
TL;DR: A switched-capacitor power amplifier that realizes an envelope elimination and restoration/polar class-G topology is introduced and a novel voltage-tolerant switch enables the use of two power supply voltages which increases efficiency and output power simultaneously.
Abstract: A switched-capacitor power amplifier (SCPA) that realizes an envelope elimination and restoration/polar class-G topology is introduced. A novel voltage-tolerant switch enables the use of two power supply voltages which increases efficiency and output power simultaneously. Envelope digital-to-analog conversion in the polar transmitter is achieved using an SC RF DAC that exhibits high efficiency at typical output power backoff levels. In addition, high linearity is achieved and no digital predistortion is required. Implemented in 65 nm CMOS, the measured peak output power and power-added efficiency (PAE) are 24.3 dBm and 43.5%, respectively, whereas when amplifying 802.11g 64-QAM OFDM signals, the average output power and PAE are 16.8 dBm and 33%, respectively. The measured EVM is 2.9%.
113 citations
TL;DR: In this paper, the authors address the energy efficiency issue of switched-capacitor converters by dividing the analysis of the entire efficiency problem into two parts, and propose some design rules useful for developing high-efficiency switch-capACC converters.
Abstract: The energy-efficiency issue of switched-capacitor converters is still a controversial topic that requires a more in-depth discussion. In this paper, we address the issue by dividing the analysis of the entire efficiency problem into two parts. In the first part, the efficiency of a capacitor-charging RC circuit under different aspects (partial charging, full charging, at zero capacitor voltage, at nonzero capacitor voltage, etc.) will be conducted. The efficiency analysis of a capacitor-discharging RC circuit with a resistor, capacitor, and paralleled resistor-capacitor loads will be covered. A complete evaluation of the overall efficiency is then performed in terms of both the charging and discharging efficiencies. Based on the analysis, some design rules useful for developing high-efficiency switched-capacitor converters is suggested. Additionally, it is shown that the belief that quasi-switched-capacitor converters are more lossy than switched-capacitor converters is a common misconception.
109 citations
TL;DR: An 8 channel energy-efficient neural stimulator for generating charge-balanced asymmetric pulses and a novel charge balancing method which has a low level of accuracy on a single pulse and a much higher accuracy over a series of pulses is presented.
Abstract: This paper presents an 8 channel energy-efficient neural stimulator for generating charge-balanced asymmetric pulses. Power consumption is reduced by implementing a fully-integrated DC-DC converter that uses a reconfigurable switched capacitor topology to provide 4 output voltages for Dynamic Voltage Scaling (DVS). DC conversion efficiencies of up to 82% are achieved using integrated capacitances of under 1 nF and the DVS approach offers power savings of up to 50% compared to the front end of a typical current controlled neural stimulator. A novel charge balancing method is implemented which has a low level of accuracy on a single pulse and a much higher accuracy over a series of pulses. The method used is robust to process and component variation and does not require any initial or ongoing calibration. Measured results indicate that the charge imbalance is typically between 0.05%-0.15% of charge injected for a series of pulses. Ex-vivo experiments demonstrate the viability in using this circuit for neural activation. The circuit has been implemented in a commercially-available 0.18 μm HV CMOS technology and occupies a core die area of approximately 2.8 mm2 for an 8 channel implementation.
94 citations
TL;DR: In this paper, a stacked switched capacitor (SSC) energy buffer architecture and some of its topological embodiments is presented, which when used with longer life film capacitors overcome this limitation while achieving effective energy densities comparable to electrolytic capacitors.
Abstract: Electrolytic capacitors are often used for energy buffering applications, including buffering between single-phase ac and dc. While these capacitors have high energy density compared to film and ceramic capacitors, their life is limited. This paper presents a stacked switched capacitor (SSC) energy buffer architecture and some of its topological embodiments, which when used with longer life film capacitors overcome this limitation while achieving effective energy densities comparable to electrolytic capacitors. The architectural approach is introduced along with design and control techniques. A prototype SSC energy buffer using film capacitors, designed for a 320 V dc bus and able to support a 135 W load, has been built and tested with a power factor correction circuit. It is shown that the SSC energy buffer can successfully replace limited-life electrolytic capacitors with much longer life film capacitors, while maintaining volume and efficiency at a comparable level.
90 citations
TL;DR: In this paper, the authors proposed a new control strategy for the single switched capacitor (SSC) cell balancing and proposed a novel procedure to improve the SSC balancing system performance.
Abstract: Battery management systems (BMS) are a key element in electric vehicle energy storage systems. The BMS performs several functions concerning to the battery system, its key task being balancing the battery cells. Battery cell unbalancing hampers electric vehicles’ performance, with differing individual cell voltages decreasing the battery pack capacity and cell lifetime, leading to the eventual failure of the total battery system. Quite a lot of cell balancing topologies have been proposed, such as shunt resistor, shuttling capacitor, inductor/transformer based and DC energy converters. The shuttling capacitor balancing systems in particular have not been subject to much research efforts however, due to their perceived low balancing speed and high cost. This paper tries to fill this gap by briefly discussing the shuttling capacitor cell balancing topologies, focusing on the single switched capacitor (SSC) cell balancing and proposing a novel procedure to improve the SSC balancing system performance. This leads to a new control strategy for the SSC system that can decrease the balancing system size, cost, balancing time and that can improve the SSC balancing system efficiency.
89 citations
28 Mar 2013
TL;DR: Ultra-low power microsystems are gaining more popularity due to their applicability in critical areas of societal need, and the small form factors of such systems rule out the use of external inductors, making switched-capacitor (SC) DC-DC converters the favored topology.
Abstract: Ultra-low power microsystems are gaining more popularity due to their applicability in critical areas of societal need. Power management in these microsystems is a major challenge as a relatively high battery voltage (e.g., 4V) must be down-converted to several low supplies, such as 0.6V for near-threshold digital circuits and 1.2V for analog circuits [1]. Furthermore, the small form factors of such systems rule out the use of external inductors, making switched-capacitor (SC) DC-DC converters the favored topology [2-4].
TL;DR: A prototype 25 GHz VCO based on transconductance linearization of the active devices is integrated in a dual-path PLL and achieves superior performance compared to the state of the art.
Abstract: This paper describes a new approach to low-phase-noise LC VCO design based on transconductance linearization of the active devices. A prototype 25 GHz VCO based on this linearization approach is integrated in a dual-path PLL and achieves superior performance compared to the state of the art. The design is implemented in 32 nm SOI CMOS technology and achieves a phase noise of $-$ 130 dBc/Hz at a 10 MHz offset from a 22 GHz carrier. Additionally, the paper introduces a new layout approach for switched capacitor arrays that enables a wide tuning range of 23%. More than 1500 measurements of the PLL across PVT variations were taken, further validating the proposed design. Phase noise variation across 55 dies for four different frequencies is $\sigma . Also, phase noise variation across supply voltages of 0.7–1.5 V is 2 dB and across 60 $^{\circ}{\rm C}$ temperature variation is 3 dB. At the 25 GHz center frequency, the VCO $FOM_{T}$ is 188 dBc/Hz. Additionally, a digitally assisted autonomic biasing technique is implemented in the PLL to provide a phase noise and power optimized VCO bias across frequency and process. Measurement results indicate the efficacy of the autonomic biasing scheme.
28 Mar 2013
TL;DR: Relaxation oscillators are suitable candidates to generate on-chip reference clock generators for low-cost low-power area-efficient SoCs, such as implantable biomedical devices and microcomputers but the poor phase noise performance and large long-term variation limit their application.
Abstract: There is a growing interest in implementing on-chip reference clock generators for low-cost low-power area-efficient SoCs, such as implantable biomedical devices and microcomputers. Relaxation oscillators are suitable candidates to generate such reference clocks due to their compact size, low power consumption and wide frequency tuning range. However, the poor phase noise performance and large long-term variation are two major problems that limit their application.
TL;DR: In this article, the authors proposed a new ac-ac static power converter based on the switched-capacitor (SC) principle, intended to replace the conventional autotransformer in commercial and residential applications.
Abstract: This paper proposes a new ac-ac static power converter based on the switched-capacitor (SC) principle, intended to replace the conventional autotransformer in commercial and residential applications The principle of operation, a qualitative and quantitative analysis, the design methodology, and an example are described in this paper The main advantages of the proposed ac-ac converter are the absence of magnetic elements, the stress voltages in all components being equal to half of the high-side voltage, the common reference between input and output voltages, the employment of a single SC leg, the ability to be bidirectional, the high efficiency, and the high power density In order to demonstrate the performance of this converter in the laboratory, a prototype of 1-kW, 220-Vrms high-side voltage, 110-Vrms low-side voltage, and switching frequency of 100 kHz was designed and fabricated The relevant experimental results are reported herein The maximum and rated power efficiencies obtained in the laboratory were 98% and 96%, respectively
17 Mar 2013
TL;DR: In this article, the design and implementation of on-chip switched capacitor converters in deep submicron technologies is described, and the measured performance of a 2 : 1 voltage conversion ratio switched capacitor converter implemented in 32nm SOI CMOS technology with 1.8V input voltage results in a power density of 4.6W/mm2 at 86% efficiency when operated at a switching frequency of 100MHz.
Abstract: The future trends in microprocessor supply current requirements represent a bottleneck for next generation high-performance microprocessors since the number of supply pins will constitute an increasingly larger fraction of the total number of package pins available. This leaves few pins available for signaling. On-chip power conversion is a means to overcome this limitation by increasing the input voltage - thereby reducing the input current - and performing the final power conversion on the chip itself. This paper details the design and implementation of on-chip switched capacitor converters in deep submicron technologies. High capacitance density deep trench capacitors with a low parasitic bottom plate capacitor ratio available in the technology facilitate high power density and efficiency in on-chip switched capacitor converter implementations. The measured performance of a 2 : 1 voltage conversion ratio on-chip switched capacitor converter implemented in 32nm SOI CMOS technology with 1.8V input voltage results in a power density of 4.6W/mm2 at 86% efficiency when operated at a switching frequency of 100MHz.
TL;DR: This study shows that the SC converter can outperform the buck converter, and thus, the scope of SC converter application can and should be expanded.
Abstract: The traditional inductor-based buck converter has been the default design for switched-mode voltage regulators for decades. Switched capacitor (SC) dc-dc converters, on the other hand, have traditionally been used in low-power ( 80% over a load range of 5 mA to 1 A) than surveyed competitive buck converters, while requiring less board area and less costly passive components. The topology and controller enable a wide input range of 7.5-13.5 V. Controls based on feedback and feedforward provide tight regulation under worst case line and load step conditions. This study shows that the SC converter can outperform the buck converter, and thus, the scope of SC converter application can and should be expanded.
TL;DR: In this article, the authors proposed a multi-input converter based on switched-capacitor instead of magnetic components, where the number of inputs can be any figure and the output voltage level of the converter is the summation of its multiple input levels which share with a common neutral.
Abstract: This study is to propose a multi-input converter which is designed based on switched-capacitor instead of magnetic components. The number of its inputs can be any figure. The output voltage level of the converter is the summation of its multiple input levels which share with a common neutral. There is no need to have any level-shift or boost-strap for adjusting the inputs. The number of active switches and capacitors required both are equal to the number of input sources. Only a pair of complementary pulse signals is needed to control all of these switches. The converter is operated under high frequency. Non-resonant version does not require resonant inductors and therefore they are of small size and simple structure. Small resonant inductor is also added in the resonant version to realise soft-switching and improve the conversion efficiency. The circuit analysis, design method and experimental verification are shown.
TL;DR: This paper presents the design and experimental results of advanced analog blocks manufactured in a printed complementary organic TFT technology on flexible foil that demonstrates the performance of the adopted technology in analog circuit implementations.
Abstract: This paper presents the design and experimental results of advanced analog blocks manufactured in a printed complementary organic TFT technology on flexible foil. Operational transconductance amplifiers exhibiting open-loop gain from 40 to 50 dB and gain-bandwidth product from 55 Hz to 1.5 kHz have been implemented by using different circuit topologies. An extensive amplifier characterization in both time and frequency domain (i.e., gain, gain-bandwidth product, phase margin, settling time, harmonic distortion) has been carried out, which demonstrates the performance of the adopted technology in analog circuit implementations. Finally, a 40-dB 1.5-kHz amplifier has been employed in a switched capacitor comparator that proved fully functionality up to input frequency of 50 Hz.
TL;DR: A family of single-stage-switched-capacitor-inductor converters with different voltage conversion features and similar structures is presented, which can meet the high efficiency requirement and simple structure.
Abstract: A family of single-stage-switched-capacitor–inductor converters with different voltage conversion features and similar structures is presented in this paper. Unlike conventional switched-capacitor/switched-inductor converters that are produced by cascade operation, all of the proposed converters are operated in single-stage mode. Though each of the proposed converters employs two energy transfer components, i.e., one switched capacitor and one inductor, energy flowing though the two components both directly come from the input power sources and then is directly released to output terminal. This design can meet the high efficiency requirement and simple structure. A small resonant inductor is also used in these converters to limit the current peak caused by switched capacitors and to improve efficiency. The detailed analysis of circuit operation and design consideration is given. Simulation and experimental results are also provided to verify the performance of the new family of converters.
20 Jun 2013
TL;DR: The results show that the efficiency of the ESC-buck converter is higher than that of a single buck converter for large-voltage-gain applications.
Abstract: This paper presents a family of exponential voltage step-down switched-capacitor (ESC) converters. Considering the demand of large-voltage-gain step-down converters in the market, it is difficult to achieve the step-down requirement with good efficiency for a single-stage buck converter. The two-stage converter has been an effective solution for high-voltage-step-down applications. In this paper, making use of the large-voltage-gain conversion property of the ESC converter, a two-stage ESC-buck converter is proposed. A mathematical tool for the accurate calculation of efficiency is developed. The efficiency characteristic of the proposed ESC converter is established. Experimental efficiency measurements are carried out using the ESC converter proposed and two different types of commercially available buck converter ICs. The results show that the efficiency of the ESC-buck converter is higher than that of a single buck converter for large-voltage-gain applications.
04 Aug 2013
TL;DR: In this paper, a resonant switched capacitor converter with high efficiency over a wide and continuous conversion ratio is introduced, where the efficiency of the topology depends primarily on the conduction losses and is decoupled, to a large extent, from the voltage conversion ratio.
Abstract: A resonant switched capacitor converter with high efficiency over a wide and continuous conversion ratio is introduced. The efficiency of the topology depends primarily on the conduction losses and is decoupled, to a large extent, from the voltage conversion ratio. This is an advantage over classical switched capacitor converters in which the efficiency is strongly related to the conversion ratio. The operation principle applies three zero current switching (ZCS) states to charge, discharge and balance the remaining charge of the flying capacitor. This results in a Gyrator-behaved voltage-dependent current source with a wide voltage conversion ratio (smaller as well as greater than unity) as well as bidirectional power flow capabilities. The analytical expressions for conversion ratio and expected efficiency are provided and validated by simulation and experiments. The experimental verification of the converter demonstrates peak efficiency of 96%, and above 90% efficiency over a wide range of voltage gains and loading conditions. In addition, the system was found to be highly efficient at the extreme cases of both light and heavy loads.
13 Jun 2013
TL;DR: In this article, the SPWM technique is implemented using multicarrier wave signals to reduce the number of switches in a 7-level cascaded multilevel inverter and the effect of the harmonic spectrum is analyzed.
Abstract: A multilevel inverter is a power electronic device that is used for high voltage and high power applications and has many advantages like, low switching stress, low total harmonic distortion (THD). Hence, the size and bulkiness of passive filters can be reduced. This paper proposes two new topologies of a 7-level cascaded multilevel inverter with reduced number of switches than that of conventional type which has 12 switches. The topologies consist of circuits with 9 switches and 7 switches for the same 7-level output. Therefore with less number of switches, there will be a reduction in gate drive circuitry and also very few switches will be conducting for specific intervals of time. The SPWM technique is implemented using multicarrier wave signals. Level Shifted triangular waves are used in comparison with sinusoidal reference to generate Sine PWM switching sequence. The number of level shifted triangular waves depends on the number of levels in the output. i.e. for n levels, n-1 number of carrier waves. This paper uses 1 KHz SPWM pulses with a modulation index of 0.8. The circuits are simulated using SPWM technique and the effect of the harmonic spectrum is analyzed. A comparison is made for the topologies with 9 switches and 7 switches and an effective reduction in THD has been observed for the circuits with less number of switches. The THD for 9 switches is 14% and the THD for 7 switches is 12.5%. The circuits are modeled and simulated with the help of MATLAB/SIMULINK.
Patent•
18 Mar 2013
TL;DR: In this article, a cascade multiplier switched capacitor network has capacitors, each of which electrically connects to a stack node and to a phase node, and a controller causes the network to transition between first and second operation modes, in which at least one capacitor is isolated from a charge transfer path of the reconfigurable switched capacitor power converter.
Abstract: An apparatus for converting a first voltage into a second voltage includes a reconfigurable switched capacitor power converter having a selectable conversion gain. converter includes a cascade multiplier switched capacitor network having capacitors, each of which electrically connects to a stack node and to a phase node. A controller causes the network to transition between first and second operation modes. In the first mode, at least one capacitor is isolated from a charge transfer path of the reconfigurable switched capacitor power converter. Consequently, in the first mode of operation, the power converter operates with a first gain. In the second mode, the power converter operates with a second conversion gain. Meanwhile, a third voltage across the at least one capacitor is free to assume any value.
TL;DR: In this article, a dual power-mode and multi-band power amplifier (PA) for handset applications that improves the efficiency in low-power regions is presented, in conjunction with a boosted supply modulator for envelope tracking (ET) operation not only in the high power mode, but also in the low power mode.
Abstract: This paper presents a dual power-mode and multi-band power amplifier (PA) for handset applications that improves the efficiency in low-power regions. This PA operates in two modes through path control by a shunt switched capacitor. The proposed control method provides efficient mode control without any efficiency degrading and bandwidth (BW) limiting. The proposed PA, in conjunction with a boosted supply modulator for envelope tracking (ET) operation not only in the high-power mode, but also in the low-power mode, delivers good performance at all average output power levels. The linearity is improved by ET through a proper envelope-shaping method. For demonstrative purposes, the PA and supply modulator are implemented using an InGaP/GaAs heterojunction bipolar transistor and AIGaAs/InGaAs enhancement/depletion-mode pseudomorphic high electron-mobility transistor process and a 0.18- $\mu$ m CMOS process, respectively. The ET PA is tested across the range of 1.7–2.0 GHz using a long-term evolution signal with 16 quadrature amplitude modulation, a 7.5-dB peak-to-average power ratio, and 10-MHz BW. The proposed dual power-mode multi-band ET PA delivers good performance for high- and low-power modes, indicating that the architecture is promising for handset PA applications.
TL;DR: In this article, a developing CMOS manufacturing process using a 4H SiC substrate has been used to fabricate a range of simple logic and analogue circuits and is intended for power control and mixed signal sensor interface applications.
Abstract: Silicon Carbide devices are capable of operating as a semiconductor at high temperatures and this capability is being exploited today in discrete power components, bringing system advantages such as reduced cooling requirements [1]. Therefore there is an emerging need for control ICs mounted on the same modules and being capable of operating at the same temperatures. In addition, several application areas are pushing electronics to higher temperatures, particularly sensors and interface devices required for aero engines and in deep hydrocarbon and geothermal drilling. This paper discusses a developing CMOS manufacturing process using a 4H SiC substrate, which has been used to fabricate a range of simple logic and analogue circuits and is intended for power control and mixed signal sensor interface applications [2]. Test circuits have been found to operate at up to 400°C. The introduction of a floating capacitor structure to the process allows the use of switched capacitor techniques in mixed signal circuits operating over an extended temperature range.
23 Jun 2013
TL;DR: In this article, a formal analysis method for switched-capacitor (SC) dc-dc converters in soft-charging operation is proposed to determine whether softcharging is at all possible and if so, the required capacitor sizes to achieve softcharging.
Abstract: This paper formulates a formal analysis method for switched-capacitor (SC) dc-dc converters in soft-charging operation Through soft-charging, the charging/discharging loss of a SC converter can be minimized or even eliminated by allowing the output voltage to vary to a greater extent Usually a soft-charging SC converter is followed by a magnetic converter for ripple reduction and better regulation For any given two-phase switched-capacitor topology, the proposed method can be used to determine whether soft-charging is at all possible and if so, the required capacitor sizes to achieve soft-charging The proposed method also gives the resultant output voltage ripple due to soft-charging operation A number of different topologies are analyzed, including Dickson, Series-parallel, Ladder, Fibonacci and Doubler configurations The analysis gives insights regarding the expected improvement in performance when these topologies are cascaded by a magnetic converter Through comparison to simulated results and existing work, the validity of the proposed method is confirmed
TL;DR: The paper discusses the handling of circuit non-idealities for the CRAFT design: their significance, modeling, and circuit techniques for their mitigation that enable this implementation to achieve a large dynamic range even at high speeds.
Abstract: This work describes the design of a 16 point analog domain FFT using a Charge Re-use Analog Fourier Transform (CRAFT) engine. The circuit relies on charge re-use to achieve 47 dB average output SNDR on an instantaneous input bandwidth of 5 GHz, and consumes only 3.8 mW (12.2 pJ/conv.). The CRAFT engine is used as a wide-band, low power RF front-end channelizer for software defined radio (SDR) applications. The paper also discusses the handling of circuit non-idealities for the CRAFT design: their significance, modeling, and circuit techniques for their mitigation. These techniques enable this implementation to achieve a large dynamic range even at high speeds.
TL;DR: In this article, a multiphase quasi-resonant (QR) zero-current switching (ZCS) switched capacitor (SC) bidirectional dc-dc converter structure is proposed to reduce current ripple and switching loss, and significantly increase converter efficiency and power density.
Abstract: A multiphase quasi-resonant (QR) zero-current switching (ZCS) switched capacitor (SC) bidirectional dc-dc converter structure is proposed to reduce current ripple and switching loss, and significantly increase converter efficiency and power density This approach provides a more precise output voltage to obtain voltage conversion ratios from the double-mode versus half-mode to n-mode versus 1/n mode This is accomplished by adding a different number of switched capacitors and power MOSFET switches with a small series connected resonant inductor for forward and reverse schemes The size and cost can be reduced when the proposed converter is designed with coupled inductors Simulation and experimental results demonstrate four-phase with and without coupled inductor interleaved QR ZCS SC converter performance for bidirectional power flow control applications A battery energy storage system for a bidirectional power flow control application is demonstrated
TL;DR: This paper reports the first analog integrated spatio-spectral beamforming front-end that allows for accurate beam steering of signals with large fractional bandwidths, thus minimizing beam squinting, and simultaneous and independent steering of multi-carrier signals.
Abstract: This paper reports the first analog integrated spatio-spectral beamforming front-end. The proposed front-end allows for accurate beam steering of signals with large fractional bandwidths, thus minimizing beam squinting, and simultaneous and independent steering of multi-carrier signals. Different spatio-spectral beamforming strategies are discussed and compared. As a proof of concept, an 8 GHz 2-channel, 4-frequency phased-array beamformer is designed and implemented in 65 nm CMOS. The IF signal on each channel is frequency split using an all passive 4-point analog FFT. The orthogonal frequency outputs are then beam-steered using an all passive I-Q vector-combiner. The RF circuit draws 22.8 mA from a 1.2 V supply while the analog baseband consumes 135 μW at 120 MS/s (9 pJ/conv.).
Patent•
20 Jun 2013TL;DR: In this paper, the authors present a multilevel power converter with a flying capacitor nesting circuit, with the switches of the inverter core and the switched capacitor circuit being gated using selected redundant switching states to control the voltage of the switched capacitors.
Abstract: Nested neutral point clamped (NNPC) multilevel power converter stages and systems are presented, in which the converter stage includes an NPC inverter core circuit with a flying (switched) capacitor nesting circuit, with the switches of the NPC core and the switched capacitor circuit being gated using selected redundant switching states to control the voltage of the switched capacitors to achieve a multilevel output voltage having equally spaced voltage step values. Multiple inverter stages can meet cascaded or connected in various configurations to implement single or multiphase power conversion systems, and higher output voltages can be achieved by forming to converter stages into an H-bridge configuration, and connecting multiple H-bridge stages in series with one another.