Showing papers on "Switched capacitor published in 2015"
TL;DR: To integrate the advantages of the high voltage gain of a switched-capacitor (SC) converter and excellent output regulation of a switching-mode dc-dc converter, a method of combining the two types of converters is proposed in this paper.
Abstract: In a photovoltaic (PV)- or fuel-cell-based grid-connected power system, a high step-up dc-dc converter is required to boost the low voltage of a PV or fuel cell to a relatively high bus voltage for the downstream dc-ac grid-connected inverter. To integrate the advantages of the high voltage gain of a switched-capacitor (SC) converter and excellent output regulation of a switching-mode dc-dc converter, a method of combining the two types of converters is proposed in this paper. The basic idea is that when the switch is turned on, the inductor is charged, and the capacitors are connected in series to supply the load, and when the switch is turned off, the inductor releases energy to charge multiple capacitors in parallel, whose voltages are controlled by a pulsewidth modulation technique. Thus, a high voltage gain of the dc-dc converter can be obtained with good regulation. Based on this principle, a series of new topologies are derived, and the operating principles and voltage gains of the proposed converters are analyzed. Finally, the design of the proposed converter is given, and the experiment results are provided to verify the theoretical analysis.
331 citations
TL;DR: In this paper, the authors show that resonant and soft-charging operations of SC converters are closely related, and a technique will be proposed, which achieves either operation by adding a single inductor to existing SC topologies.
Abstract: Traditionally, switched-capacitor (SC) converters have suffered from high transient currents, which limit both the efficiency and power density of such converters. Soft-charging operation can be employed to eliminate the current transients and greatly improve the power density of SC converters. In this approach, a second-stage magnetic converter is cascaded with the SC stage to act as a controlled current load. Another approach is to use resonant SC converters with zero-current switching. This paper shows that resonant and soft-charging operations of SC converters are closely related, and a technique will be proposed, which achieves either operation by adding a single inductor to existing SC topologies. In addition, since most preexisting resonant or soft-charging SC converters were devised in an ad-hoc manner, this paper formulates an analytical method that can determine whether an existing conventional SC converter topology is compatible with the proposed approach. A number of common SC topologies are analyzed, including Dickson, series-parallel, ladder, Fibonacci, and doubler configurations. Through comparison to simulated results, as well as experimental work, the proposed method is validated and a family of high-performance SC converters is obtained.
210 citations
TL;DR: In this article, an active-switched-capacitor/switchedinductor quasi-Z -source inverter (ASC/SL-qZSI) is proposed, which is based on a traditional qZSI topology.
Abstract: This paper proposes a new topology named the active-switched-capacitor/switched-inductor quasi- Z -source inverter (ASC/SL-qZSI), which is based on a traditional qZSI topology. Compared to other qZSI-based topologies under the same operating conditions, the proposed ASC/SL-qZSI provides higher boost ability, requires fewer passive components such as inductors and capacitors, and achieves lower voltage stress across the switching devices of the main inverter. Another advantage of the topology is its expandability. If a higher boosting rate is required, additional cells can easily be cascaded at the impedance network by adding one inductor and three diodes. Both the simulation studies and the experimental results obtained from a prototype built in the laboratory validate proper operation and performance of the proposed ASC/SL-qZSI.
171 citations
TL;DR: In this article, the authors proposed a multicell switched inductor/ switched-capacitor combined active network converters (MSL/SC-ANC) which combines the advantages of SL/SC unit and active network structure.
Abstract: High step-up voltage gain dc/dc converters are widely used in renewable energy power generation, uninterruptible power system, etc. In order to avoid the influence of leakage inductor in coupled inductors based converters, switched-inductor boost converter (SL-boost), switched-capacitor boost converter (SC-boost) and active-network converter (ANC) have been developed. With the transition in series and parallel connection of the inductors and capacitors, high step-up voltage conversion ratio can be achieved. This paper discusses the characteristics of the switched inductor and switched-capacitor cell; makes some comparisons between the ANC and boost converter. Based on the aforementioned analysis, this paper proposed the multicell switched-inductor/ switched-capacitor combined active network converters (MSL/SC-ANC). The proposed converters combine the advantages of SL/SC unit and active-network structure. Compared with previous high step-up converters, the novel converter provides a higher voltage conversion ratio with a lower voltage/current stress on the power devices, moreover, the structure of proposed SL/SC-ANC is very flexible, which means the quantity of SL and SC cells can be adjusted according to required voltage gain. A 20 times gain prototype is designed as an example to show the design procedure. Theoretical analysis and experimental results are presented to demonstrate the feature of the proposed converter.
128 citations
TL;DR: In this paper, a two-phase, nominally 2:1 step-down topology was proposed for a chip-scale ReSC converter that can deliver over 4 W at 0.6 W/mm2 with 85% efficiency.
Abstract: There is an increasing need for power management systems that can be fully integrated in silicon to reduce cost and form factor in mobile applications, and provide point-of-load voltage regulation for high-performance digital systems. Switched-capacitor (SC) converters have shown promise in this regard due to relatively high energy-density of capacitors and favorable device utilization figures of merit. Resonant switched-capacitor (ReSC) converters show similar promise as they benefit from many of the same architectures and scaling trends, but also from ongoing improvements in mm-scale magnetic devices. In this study, we explore the design and optimization of 2:1 step-down topologies, based on representative capacitor technologies, CMOS device parameters, and air-core inductor models. We compare the SC approach to the ReSC approach in terms of efficiency and power density. Finally, a chip-scale ReSC converter is presented that can deliver over 4 W at 0.6 W/mm2 with 85% efficiency. The two-phase, nominally 2:1 converter supports input voltages from 3.6–6.0 V, and is implemented in 180-nm bulk CMOS with die-attached air-core solenoid inductors.
114 citations
TL;DR: In this article, the authors proposed a dc-dc converter configuration, which successfully integrates two technologies, including a switched capacitor and a switched coupled inductor, into one converter, and achieved a voltage gain of up to 11.2%.
Abstract: This paper presents a novel dc–dc converter configuration, which successfully integrates two technologies, including a switched capacitor and a switched coupled inductor, into one converter. By adopting a coupled inductor to charge a switched capacitor, the voltage gain can be effectively increased, and the turns ratio of the coupled inductor can be also reduced. Not only lower conduction losses but also higher power conversion efficiency is benefited from a lower part count and lower turns ratios. The proposed converter is simply composed of six components, which can be further derived to varied converters for different purposes, such as a bidirectional converter. The operating principle and steady-state analysis are discussed in this paper. A 250-W laboratory hardware prototype is completed and verified. The voltage gain is up to 11. The highest efficiency is 97.2%, and the full-load efficiency is kept at 93.6%.
113 citations
TL;DR: In this article, a series-parallel switched-capacitor (SC) power converter is reconfigured as a new voltage equalization circuitry for series-connected batteries or supercapacitors.
Abstract: A series–parallel switched-capacitor (SC) power converter is reconfigured as a new voltage equalization circuitry for series-connected batteries or supercapacitors in this paper. The model of the new voltage equalizer is derived and successfully used to analyze the equalization speed and the energy loss. It is a very useful tool to analyze and design the SC-based equalization systems to meet different balancing speed requirements. The analysis and modeling methods can be extended to other SC-based voltage-balancing systems. A prototype is built and the experimental results are provided to confirm the theoretical analysis and the modeling method.
110 citations
TL;DR: In this paper, a two-Switch boosting switching capacitors (TBSC) is introduced, which distinguishes itself from the prior arts by symmetrically interleaved operation, reduced output ripple, low yet even voltage stress on components, and systematic expandability.
Abstract: A family of “Two-Switch Boosting Switched-Capacitor Converters (TBSC)” is introduced, which distinguishes itself from the prior arts by symmetrically interleaved operation, reduced output ripple, low yet even voltage stress on components, and systematic expandability. Along with the topologies, a modeling method is formulated, which provokes the converter regulation method through duty cycle and frequency adjustment. In addition, the paper also provides guidance for circuit components and parameter selection. A 1-kW 3X TBSC was built to demonstrate the converter feasibility, regulation capability via duty cycle and frequency, which achieved a peak efficiency of 97.5% at the rated power.
97 citations
TL;DR: The value of a merged two-stage architecture to provide substantial design benefits in high-input voltage, low-power step down conversion applications, including both wide-range-input dc-dc and line-input ac-dc systems is demonstrated.
Abstract: This paper presents a merged-two-stage circuit topology suitable for either wide-range dc input voltage or ac line voltage at low-to-moderate power levels (e.g., up to 30 W). This two-stage topology is based on a soft-charged switched-capacitor preregulator/transformation stage and a high-frequency magnetic regulator stage. Soft charging of the switched capacitor circuit, zero voltage switching of the high-frequency regulator circuit, and time-based indirect current control are used to maintain high efficiency, high power density, and high power factor. The proposed architecture is applied to an LED driver circuit, and two implementations are demonstrated: a wide input voltage range dc-dc converter and a line interfaced ac-dc converter. The dc-dc converter shows 88%-96% efficiency at 30-W power across 25-200-V input voltage range, and the ac-dc converter achieves 88% efficiency with 0.93 power factor at 8.4-W average power. Contributions of this paper include: 1) demonstrating the value of a merged two-stage architecture to provide substantial design benefits in high-input voltage, low-power step down conversion applications, including both wide-range-input dc-dc and line-input ac-dc systems; 2) introduction of a multimode soft-charged SC stage for the merged architecture that enables compression of an 8:1 input voltage range into a 2:1 intermediate range, along with its implementation, loss considerations, and driving methods; and 3) merging of this topology with an resonant transition discontinuous-mode inverted buck stage and pseudocurrent control to enable step-down power conversion (e.g., for LED lighting) operating at greatly increased frequencies and reduced magnetics size than with more conventional approaches.
94 citations
TL;DR: An improved auto-zero scheme that eliminates the gain error caused by the parasitic capacitance across the auto- zero switch is introduced and a comparator-less pipeline ADC structure takes advantage of the characteristics of the ring-amplifier to replace the sub-ADC in each pipeline stage.
Abstract: The ring amplifier is an energy efficient and high output swing alternative to an OTA for switched-capacitor circuits However, the conventional ring amplifier requires external biases, which makes the ring amplifier less practical when we consider process, supply voltage, and temperature (PVT) variation This paper presents a self-biased ring amplifier scheme that makes the ring amplifier more practical and power efficient while maintaining the benefits of efficient slew-based charging and an almost rail-to-rail output swing We introduce an improved auto-zero scheme that eliminates the gain error caused by the parasitic capacitance across the auto-zero switch Furthermore, a comparator-less pipeline ADC structure takes advantage of the characteristics of the ring-amplifier to replace the sub-ADC in each pipeline stage The prototype ADC has measured SNDR, SNR and SFDR of 566 dB (911 b), 575 dB and 647 dB, respectively, for a Nyquist frequency input sampled at 100 MS/s, and consumes 246 mW
94 citations
12 Jul 2015
TL;DR: It is shown that multimode operation, including previously published resonant and dynamic off-time modulation, form a single set of techniques that can be used to extend high efficiency over a wide power density range.
Abstract: Multi-level converter architectures have been explored for a variety of applications including high-power DC-AC inverters and DC-DC converters. In this work, we explore flying-capacitor multi-level (FCML) DC-DC topologies as a class of hybrid switched-capacitor/inductive converter. Compared to other candidate architectures in this area (e.g. Series-Parallel, Dickson), FCML converters have notable advantages such as the use of single-rated low-voltage switches, potentially lower switching loss, lower passive component volume, and enable regulation across the full V DD -V OUT range. It is shown that multimode operation, including previously published resonant and dynamic off-time modulation, form a single set of techniques that can be used to extend high efficiency over a wide power density range. Some of the general operating considerations of FCML converters, such as the challenge of maintaining voltage balance on flying capacitors, are shown to be of equal concern in other soft-switched SC converter topologies. Experimental verification from a 24V:12V, 3-level converter is presented to show multimode operation with a nominally 2:1 topology. A second 50V:7V 4-level FCML converter demonstrates operation with variable regulation. A method is presented to balance flying capacitor voltages through low frequency closed-loop feedback.
TL;DR: In this article, a resonant switched capacitor converter with high efficiency over a wide and continuous conversion ratio range is introduced, where the efficiency of the topology depends primarily on the conduction losses and is decoupled, to a large extent, from the voltage conversion ratio.
Abstract: A resonant switched capacitor converter with high efficiency over a wide and continuous conversion ratio range is introduced. The efficiency of the topology depends primarily on the conduction losses and is decoupled, to a large extent, from the voltage conversion ratio. This is an advantage over classical switched capacitor converters, for which the efficiency is strongly related to the conversion ratio. The operation principle applies three zero current switching states to charge, discharge, and balance the remaining charge of the flying capacitor. This results in a gyrator, i.e., a voltage-dependent current source, with a wide range of voltage conversion ratios (smaller as well as greater than unity) as well as bidirectional power flow capabilities. The analytical expressions for the conversion ratio and expected efficiency are provided and validated through simulations and experiments. The experimental verifications of the converter demonstrate peak efficiency of 96% and above 90% efficiency over a wide range of voltage gains and loading conditions. In addition, the system was found to be highly efficient at the extreme cases of both light and heavy loads.
19 Mar 2015
TL;DR: Reducing the supply voltage of digital circuits to the sub- or near-threshold regions minimizes dynamic power consumption and achieves better efficiency, and is especially beneficial for wirelessly powered devices such as wearable electronics, biomedicai implants and smart sensor networks.
Abstract: Reducing the supply voltage of digital circuits to the sub- or near-threshold regions minimizes dynamic power consumption and achieves better efficiency [1]. This technique is widely used in energy-efficient applications, and is especially beneficial for wirelessly powered devices such as wearable electronics, biomedicai implants and smart sensor networks. Such devices have long standby times and battery-less operation is highly desirable. As shown in Fig. 20.5.1, for a typical wireless power transmission system, there is a gap between the rectified V IN (>2V) and the low supply voltage V OUT ( out/ V IN ) and high efficiency are needed. However, a low M results in low efficiency for linear regulators and fully integrated buck converters. On the other hand, fully integrated switched-capacitor power converters (SCPCs) are good alternatives that can achieve high efficiency at low M in low power applications [2-5].
12 Jul 2015
TL;DR: In this article, a quantitative method that can serve as a guide to compare and design multilevel topologies for large voltage conversion ratio applications is presented, which keeps the conduction loss and switching loss the same across the different converters and employs the passive component volume as the single performance metric.
Abstract: This work investigates the use of multilevel conversion in dc-dc applications that involve a large voltage conversion ratio. A quantitative method that can serve as a guide to compare and design multilevel topologies for large conversion ratio applications is presented. The proposed method keeps the conduction loss and switching loss the same across the different converters and employs the passive component volume as the single performance metric. As examples, flying capacitor multilevel converters (FCMC) and hybrid switched-capacitor (SC) converters are compared to conventional two-level buck converters, and are shown analytically to have significantly reduced passive component size. Three converter prototypes are implemented, based on the presented methodology to experimentally validate the method as well as demonstrate the advantages of multilevel converters.
19 Mar 2015
TL;DR: Compared to more traditional buck and boost topologies, the SC approach provides better utilization of active and passive components, and is especially favorable when using submicron or deep-submicron CMOS technology because low-voltage devices can be configured in cascaded or hierarchical structures to interface across wide conversion ratios.
Abstract: Switched-capacitor (SC) converters have shown significant promise for monolithic integration in a variety of mobile computing applications due to the relatively high energy-densities of modern capacitor technologies and the emergence of deep-trench technology [1-4]. Compared to more traditional buck and boost topologies, the SC approach provides better utilization of active and passive components, and is especially favorable when using submicron or deep-submicron CMOS technology because low-voltage devices can be configured in cascaded or hierarchical structures to interface across wide conversion ratios [5].
TL;DR: A modified Dickson converter to achieve wide input range capacitive DC-DC converters and a Bootstrapped Gate Boost Converter is proposed which uses a bootstrapping technique to generate a floating rail for the flying switches, whose terminal voltages vary by large amounts depending on input voltage and VCR.
Abstract: This paper presents a modified Dickson converter to achieve wide input range capacitive DC-DC converters. Several implementations are carefully studied and compared, which shows that the folding Dickson converter is the best choice, not only for its reduced dynamic losses, but also for its very regular structure and operation. Folding is achieved by merging the terminals of two or more flying capacitors, creating one equivalent flying capacitor. In this design, a four stage folding Dickson converter is implemented to achieve four different voltage conversion ratios. A Bootstrapped Gate Boost Converter (BGBC) is proposed which uses a bootstrapping technique to generate a floating rail for the flying switches, whose terminal voltages vary by large amounts depending on input voltage and VCR. The inherent operation of the Dickson topology is used by copying the voltage of the flying capacitors on a grounded capacitor in one phase, which can then be used to generate a floating 1.2 V in the second phase. The converter has been implemented in a 90 nm technology, achieving a maximum output power of 50 mW, peak efficiency of 76.6% in the 2:1 conversion mode, and an average efficiency above 60% over the entire Vin and Pout range.
TL;DR: This work presents a resonant switched capacitor (ReSC) topology that addresses some of these challenges by introducing a small amount of inductance in series with the flying capacitor, eliminating charge-sharing losses and thus allowing efficient operation in a low-cost process option.
Abstract: In recent years, there has been a push towards high-density and monolithic DC-DC converters to support applications such as performance and mobile computing, consumer electronics, and renewable energy. Switched capacitor (SC) converters have started to gain traction for a number of these applications, but are still subject to fundamental limitations that drive them towards expensive process options and high switching frequencies. Variable regulation is challenging with the SC approach, and comes at the cost of lower power density and efficiency. This work presents a resonant switched capacitor (ReSC) topology that addresses some of these challenges by introducing a small amount of inductance in series with the flying capacitor, eliminating charge-sharing losses and thus allowing efficient operation in a low-cost process option. The three-phase interleaved topology can deliver up to 7.7 W at 85% efficiency (power density of 0.91 W/mm $^{2}$ or 6.4 kW/in $^{3}$ ) using a bootstrapped n-channel power train and single-digit nH inductors embedded in a flip-chip assembly. We also present the first implementation of efficient, fully-variable conversion ratios in a silicon ReSC integrated circuit without reconfiguration or gain-hopping .
TL;DR: In this article, a new non-isolated high step-up DC-DC converter which is derived from Z-source converter and provides highervoltage gain compared with its conventional counterpart is presented.
Abstract: Z-source converter has several advantages such as high-voltage gain, clamped switch voltage and positive output voltage polarity. This study presents a new non-isolated high step-up DC–DC converter which is derived from Z-source converter and provides higher-voltage gain compared with its conventional counterpart. Owing to its high-voltage conversion ratio, the proposed converter is a proper choice for photovoltaic applications. Furthermore, reverse-recovery problems caused by the output diode are reduced in the proposed converter which reduces the switching losses. In addition, the leakage energy is recycled so the conversion efficiency is improved. Analysis and operating principles of the proposed converter are discussed and design guidelines are presented. Moreover, the effect of non-ideal elements on the proposed converter performance is analysed. A 100 W laboratory prototype to convert 20–300 V is implemented and experimental results are presented to verify theoretical analysis.
TL;DR: A reconfigurable switched-capacitor DC-DC regulator to simultaneously generate two different regulated output voltages for low-power applications and a sub-harmonic adaptive-on-time (SHAOT) control scheme is developed to regulate both outputs.
Abstract: This paper presents a reconfigurable switched-capacitor (SC) DC-DC regulator to simultaneously generate two different regulated output voltages for low-power applications. With capacitor and power switch sharing in the power stage, the area efficiency of the proposed regulator is improved. The proposed power stage can also be configured to provide different conversion ratios in order to maintain high power efficiency of the regulator in different input voltages. A sub-harmonic adaptive-on-time (SHAOT) control scheme is developed to regulate both outputs. The adaptive-on-time control automatically adjusts the durations of charge transfer to both outputs to reduce output voltage ripples under different input voltages. Switching power transistors at the fundamental or sub-harmonics of the system clock frequency can provide predictable noise spectrum to both regulated outputs and improve the light-load regulator power efficiency. The cross regulation between both outputs can also be minimized by the proposed SHAOT scheme. Implemented in a standard 0.35 μm CMOS process, the proposed regulator provides two regulated outputs of 2 V and 3 V and delivers up to 12 mA at each output. The proposed regulator achieves a maximum power efficiency of 89.5%. Both power efficiency and output ripple can be improved by 10% and ~ 4 times, respectively, over a wide input range from 1.1 V to 1.8 V by using the proposed reconfigurable power stage and adaptive-on-time scheme.
TL;DR: A dynamic voltage and frequency scaling scheme with SC converters is proposed that achieves high converter efficiency by allowing the output voltage to ripple and having the processor core frequency track the ripple.
Abstract: Integrating multiple power converters on-chip improves energy efficiency of manycore architectures. Switched-capacitor (SC) dc-dc converters are compatible with conventional CMOS processes, but traditional implementations suffer from limited conversion efficiency. We propose a dynamic voltage and frequency scaling scheme with SC converters that achieves high converter efficiency by allowing the output voltage to ripple and having the processor core frequency track the ripple. Minimum core energy is achieved by hopping between different converter modes and tuning body-bias voltages. A multicore processor model based on a 28-nm technology shows conversion efficiencies of 90% along with over 25% improvement in the overall chip energy efficiency.
TL;DR: A bidirectional three-phase direct ac-ac converter, with only capacitors and switches in its power circuit and with its operation based on the switched-capacitor principle, suitable to replace the conventional three- phase autotransformer in industrial, commercial, and residential applications.
Abstract: This paper proposes a bidirectional three-phase direct ac–ac converter, with only capacitors and switches in its power circuit and with its operation based on the switched-capacitor principle. The converter presents fixed gain, it keeps the frequencies of the output and input voltages equal, and it operates in open loop with constant switching frequency and duty cycle. The main advantages of the proposed converter are the absence of magnetic elements in the power circuit, the higher efficiency, the higher power density, the higher specific power, the lower cost, and the fact that it can convert ac–ac voltages within a wide frequency range, including dc voltage. Therefore, it is suitable to replace the conventional three-phase autotransformer in industrial, commercial, and residential applications, and it can be designated as a magnetic-less three-phase solid-state autotransformer. The principle of operation, a qualitative and quantitative analysis, the design methodology, and a fabricated example are described in this paper. In order to verify the converter in the laboratory, a prototype with the following characteristics was designed and fabricated: 6 kW, 1.35 kW/kg, 380/110 V, and switching frequency of 100 kHz. The measured efficiency at rated power was 96.3%, and other relevant experimental results are reported herein.
TL;DR: Several approaches are studied that overcome the exposed modeling difficulties in the modeling of dc-dc converters with switched capacitors, addressing ideal and nonideal cases and using dynamic equations that are valid in a large-signal domain.
Abstract: In this paper, we review relevant problems in the modeling of dc–dc converters with switched capacitors. We study several approaches that overcome the exposed modeling difficulties, addressing ideal and nonideal cases and using dynamic equations that are valid in a large-signal domain.
17 May 2015
TL;DR: In this article, a 0.1-0.7GHz switched-capacitor RF front end features tunable center frequency and programmable filter order as well as very high tolerance for out-of-band (OB) blockers.
Abstract: A 0.1–0.7GHz switched-capacitor RF front end features tunable center frequency and programmable filter order as well as very high tolerance for out-of-band (OB) blockers. RF input impedance matching, N-path filtering, down-conversion, and high order IIR filtering are implemented using highly linear switches and capacitors only. The 3.24mm2 40nm CMOS front-end prototype consumes 38.5–76.5mA, achieves 24dBm OB-IIP3 and 14.7dBm B1dB for a 30MHz offset, 6.8 to 9.7dB NF, and >66dB calibrated harmonic rejection ratio.
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08 Jan 2015TL;DR: In this article, a converter controller is housed along with a current limit series transistor and fault detection circuitry, which is controlled to limit the in-rush current to a predetermined maximum level during start-up.
Abstract: To reduce in-rush currents into a switched capacitor DC/DC converter and detect voltage and current faults, a converter controller is housed along with a current limit series transistor and fault detection circuitry. The series transistor is controlled to limit the in-rush current to a predetermined maximum level during start-up. If the duration of the current limit level, or the time for Vout to achieve a target voltage, exceeds a first threshold time, a first fault detector in the package shuts off the series transistor. During steady state operation, if the input current reaches the limit for a second threshold time or if Vout extends outside a certain range for the second threshold time, a second fault detector in the package shuts off the series transistor.
TL;DR: An invasive-attack-resistant physical unclonable function (PUF) with strong reliability is presented and the failed outside invasive attack efforts verify the anti-invasive-attack property of the PUF unit.
Abstract: An invasive-attack-resistant physical unclonable function (PUF) with strong reliability is presented The mismatch of capacitor ratios in real fabrication is sampled by a switched-capacitor (SC) circuit and further amplified by a latch-styled sense amplifier Transmission lines connected to the sampling capacitors are used to cover and protect the whole chip from outside invasive attacks The proposed SC PUF is fabricated using HJ standard 018 $\mu{\rm m}$ CMOS process Simulation results show that the invasive-attack-resistant sensitivity is less than 256 fF The failed outside invasive attack efforts verify the anti-invasive-attack property of the PUF unit Besides, measured results show that the proposed SC PUF circuit with 3 V/18 V-VDD achieves an error rate 1x-55x lower than other PUF implementations An error correction block is also presented to achieve a nearly zero error rate The measured average error rate, bias, average intra-die HD and average inter-die HD of the 3 V/18 V-VDD SC PUF with error correction block is 0%, 4672%, 0%, and 4984% respectively
01 Jan 2015
TL;DR: In this paper, a new method combined the conventional DC-DC converter and switched-capacitor(SC) converter was proposed on the basis of the respectively advantages, and the operation principles and voltage gain of the proposed converters were analyzed.
Abstract: The output voltage of photovoltaic(PV) source and fuel cells is generally low. In the grid-connected power system, high step-up and high-efficiency DC-DC converters are needed due to the relatively high bus voltage of the grid-connected inverter. In this paper, a new method combined the conventional DC-DC converter and switched-capacitor(SC) converter was proposed on the basis of the respectively advantages. The basic principle is that during the switch is turned off, and energy released by the inductor can be used to charge the multiple capacitors in parallel whose voltages are controlled by pulse width modulation(PWM) technique. When the switch is turned on, the capacitors are in series to supply the load. Thus the voltage gain of DC-DC converter is increased. Based on this, a series of new topologies were derived. The operation principles and voltage gain of the proposed converters were analyzed. In the end, design process of the proposed converter, and experiment results were given to verify the correct of the theoretical analysis.
15 Mar 2015
TL;DR: In this paper, a resonant, 1-to-4 voltage conversion ratio Dickson SC converter is proposed, which achieves a switching frequency of 1.2 MHz and a peak efficiency of 92 %.
Abstract: Switched-capacitor (SC) converters have generated interest in the research community due to the possibility of achieving high power densities at high voltage conversion ratios. This work proposes a resonant, 1-to-4 voltage conversion ratio Dickson SC converter. A single inductor is utilized to achieve zero current switching of all transistors, which allows for high switching frequency and high conversion efficiency. A split-phase control scheme is used in order to eliminate the current transients associated with the Dickson SC converter and the resultant power loss. Employing these techniques, a 25 V to 100 V Dickson SC converter prototype is implemented with GaN transistors. The converter achieves a switching frequency of 1.2 MHz and a peak efficiency of 92 %. The power stage of the converter is able to achieve a power density of a 1011 W/in3 at 263 W.
17 Jun 2015
TL;DR: This work demonstrates a RISC-V vector microprocessor implemented in 28nm FDSOI with fully-integrated non-interleaved switched-capacitor DCDC (SC-DCDC) converters and adaptive clocking that generates four on-chip voltages between 0.5V and 1V using only 1.0V core and 1.8V IO voltage inputs.
Abstract: This work demonstrates a RISC-V vector microprocessor implemented in 28nm FDSOI with fully-integrated non-interleaved switched-capacitor DCDC (SC-DCDC) converters and adaptive clocking that generates four on-chip voltages between 0.5V and 1V using only 1.0V core and 1.8V IO voltage inputs. The design pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80–86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices.
19 Mar 2015
TL;DR: This paper presents a graphics core supplied by a fully integrated and digitally controlled hybrid low-drop-out (LDO)/switched-capacitor voltage regulator (SCVR) with fast droop response that delivers the power required by the core at a high VOUT with 84% LDO efficiency, while extending to a low VOUT of 0.38V with 52% SCVR efficiency from a 1.05V VIN.
Abstract: A graphics execution core in 22nm improves energy efficiency across a wide DVFS range, from the near-threshold voltage (NTV) region, where circuit assist lowers intrinsic V M!N , to the turbo region, where adaptive clocking reduces the voltage-droop guard-band [1]. When powered with a shared rail, however, energy is wasted in the core if other blocks demand higher voltage and performance. Alternately, a per-core fully-integrated voltage regulator (VR) provides a cost-effective means to realize autonomous DVFS [2-4].
17 Jun 2015
TL;DR: A switched-capacitor (SC) PMIC is presented that achieves up to a 6.6-bit resolution with only 5 flying capacitors for inductive PMIC replacement.
Abstract: A switched-capacitor (SC) PMIC is presented that achieves up to a 6.6-bit resolution with only 5 flying capacitors for inductive PMIC replacement. The flying capacitors are reused in a frequency-scaled gear train as well as charge-feedback SC topologies to attain a 2.4× reduction in capacitors number compared to prior art. In 0.25μm bulk, the PMIC operates from an input voltage of 2.5–5V, can generate an output voltage ranging from 0.2–2V, and features an average efficiency of 90.2% across the entire range and a peak efficiency of 95.5%.