Synchronous serial communication

About: Synchronous serial communication is a research topic. Over the lifetime, 464 publications have been published within this topic receiving 4917 citations.

Guaranteeing synchronous message deadlines with the timed token medium access control protocol

Abstract: We study the problem of guaranteeing synchronous message deadlines in token ring networks where the timed token medium access control protocol is employed. Synchronous bandwidth, defined as the maximum time for which a node can transmit its synchronous messages every time it receives the token, is a key parameter in the control of synchronous message transmission. To ensure the transmission of synchronous messages before their deadlines, synchronous capacities must be properly allocated to individual nodes. We address the issue of appropriate allocation of the synchronous capacities. Several synchronous bandwidth allocation schemes are analyzed in terms of their ability to satisfy deadline constraints of synchronous messages. We show that an inappropriate allocation of the synchronous capacities could cause message deadlines to be missed, even if the synchronous traffic is extremely low. We propose a scheme, called the normalized proportional allocation scheme, which can guarantee the synchronous message deadlines for synchronous traffic of up to 33% of available utilization. >

Addressable shadow port and protocol for serial bus networks

Abstract: A protocol and associated circuitry operable for efficiently extending serial bus capability in system environments is described. The protocol is designed to coexist and be fully compatible with existing serial bus approaches, and in particular an example of application of the invention to a backplane system utilizing the 1149.1 IEEE standard serial bus is detailed. The circuitry and protocol required to couple any one of the boards on the backplane to the serial bus master without modifying the existing serial bus protocol, without adding additional signals, and without affecting the throughput rate of the serial bus is described. The invention advantageously allows the serial bus master to select, communicate with, and deselect backplane boards so that high level test functions may be simultaneously executed and monitored. Additional preferred embodiments are also described.

Serial Interface to Flash-Memory Chip Using PCI-Express-Like Packets and Packed Data for Partial-Page Writes

Abstract: A serial flash-memory chip has a serial-bus interface to an external controller. A flash-memory block in the serial flash-memory chip can be read by the external controller sending a read-request packet over the serial bus to the serial flash-memory chip, which reads the flash memory and sends the data back in a data-payload field in a completion packet. Data in a write-request packet is written to the flash memory, and a message packet sent back over the serial bus. The serial bus can be a Peripheral Component Interconnect (PCI) Express bus with bi-directional pairs of differential lines. Packets have modified-PCI-Express headers that define the packet type and data-payload length. Vendor-defined packets can send flash commands such as reset, erase, or responses after operations such as program or erase. A serial engine and microcontroller or state machine are on the serial flash-memory chip.