Synchronous Serial Interface
About: Synchronous Serial Interface is a research topic. Over the lifetime, 117 publications have been published within this topic receiving 862 citations. The topic is also known as: SSI.
Papers published on a yearly basis
03 Apr 1989
TL;DR: In this paper, a debug peripheral is coupled to a central processing unit and memory via an internal communications bus, and the debug peripheral assumes control of the CPU by providing an interrup signal to the CPU, and thereby causing the CPU to fetch instructions directly from the debug peripherals.
Abstract: A data processing system having a debug peripheral is provided. The debug peripheral is coupled to a central processing unit and memory via an internal communications bus. The debug peripheral is a single-word dual port memory with parallel read-write write access on one side, and synchronous, full-duplex serial read-write access on the other side. The serial side of the debug peripheral is connected to external emulation hardware by means of a three-pin synchronous serial interface. The parallel access is via a connection to a core central processing unit (CPU) internal communications bus. The debug peripheral is addressed at sixteen adjacent locations in the CPU memory space. During a debug interlude, the debug peripheral assumes control of the CPU by providing an interrup signal to the CPU, and thereby causing the CPU to fetch instructions directly from the debug peripheral. The debug peripheral receives instructions from the external emulation hardware, and provides the debug instructions to the CPU, in response to an instruction address provided by the CPU.
•09 Sep 1997
TL;DR: In this paper, a low power reduced size serial device protocol translator including a slave controller and detection circuit for detecting start and stop conditions on serial data (SDA) and serial clock (SCL) lines in a serial communication system is described.
Abstract: A low power reduced size serial device protocol translator including a slave controller (26) and detection circuit (27, 28) for detecting start and stop conditions on serial data (10) (SDA) and serial clock (11) (SCL) lines in a serial communication system is described. The start and stop condition detector includes two flip-flops (27, 28); which are only enabled and clocked when either a start or stop condition is occurring. A master device resides on a first printed circuit board (PCB) and communicates with slave devices on a second PCB having more than one type of serial communication protocol. The translator resides on the same PCB as the slave devices thus requiring that only the serial buses corresponding to the master device protocol type to be physically coupled across the two PCB's interconnection interface.
•03 Dec 1984
TL;DR: In this article, a ring network is comprised of slave devices (96) (98), (100) and (102) that are interconnected on a ring-networks, and a clock is generated by the controller (120) and transmitted to each of the slave devices through a node (1188) to provide an asynchronous clock with respect thereto.
Abstract: A ring network is comprised of slave devices (96) (98), (100) and (102) that are interconnected on a ring network. The slave device (96) is interfaced with a test/maintenance controller (120) through a serial transmission line (106). The slave device (96) is interfaced with the slave device (98) through a serial transmission line (108). The slave device (98) is interfaced with the slave device (100) through a line (110) and the slave device (102) is interfaced with the slave device (100) through a line (112) with the slave device (102) being interfaced with the controller (120) through a line (114). A clock is generated by the controller (120) and transmitted to each of the slave devices through a node (1188) to provide an asynchronous clock with respect thereto. Each of the slave devices has an internal synchronizing circuit (130) for synchronizing the internal operation of the devices with respect to the controller (120). In addition, a data line select circuit (121) is provided to determine direction of transmission on the bus. The controller selects the position of the devices on the bus by transmitting a unique identifier which is recognized by a slave device as a select signal therefor as a function of its relative position on the bus with respect to the point from which the data was transmitted. The controller (120) can transmit from either direction on the bus and receive data from either direction.
•29 Sep 2008
TL;DR: In this article, a method and system for operating a NAND memory device is presented, where serial peripheral interface signals are transmitted from a host to a memory device without modifying the signals into a standard NAND format.
Abstract: A method and system is disclosed for operating a NAND memory device. The NAND memory device is operated by transmitting serial peripheral interface signals from a host to a NAND memory device, whereby the signals are communicated to a NAND memory in the NAND memory device without modifying the signals into a standard NAND memory format. Similarly, a method and system is disclosed for receiving signals from the NAND memory device without modifying the signals from a standard NAND format into a serial format. The system also incorporates error detection and correction techniques to detect and correct errors in data stored in the NAND memory device.
•30 Jun 1987
TL;DR: In this article, an improved parallel-to-serial-data interface-adaptor is proposed for the master and slave data processors with a data input/output (I/O) bus and an address bus.
Abstract: An improved parallel-to-serial-data interface-adaptor that is generally m up of master and slave data processors having master and slave microprocessors, master and slave multibit latches, and separate pairs of read only and random access memories for both the master and slave processors. A data input/output (I/O) bus and an address bus are provided for interconnecting various elements of either the master or slave processors. An interface advantageously interconnects the slave data I/O bus with the master data I/O bus. The master microprocessor advantageously functions to selectively process the master parallel data input when received so that it is compatible with a serial data processor when the selectively processed parallel data input is converted to serial format by a parallel-to-serial-data converter. The master processor further functions by way of the interface to convert a slave parallel data input previously processed by the slave processor to a serial form when the master processor is not busy in processing a parallel data input. The improved master/slave adaptor preferably handles two separate 32-bit parallel data inputs with either input being selectively processed and readily converted by the improved adaptor to a 32-bit serial format that is compatible with a serial data processor.