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System bus

About: System bus is a research topic. Over the lifetime, 19315 publications have been published within this topic receiving 199426 citations.


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Patent
31 Jan 1989
TL;DR: In this paper, a system for and a method of providing an expandable home automation controller is disclosed which supports multiple numbers and multiple different types of data communications with both appliances and subsystems within the home as well as systems external to the home.
Abstract: A system for and a method of providing an expandable home automation controller is disclosed which supports multiple numbers and multiple different types of data communications with both appliances and subsystems within the home as well as systems external to the home. The system is based upon a central processor, such as a microprocessor-based computer, and is connected by means of a data bus to control the various products and subsystems within a home or commercial building, such as lighting systems, security systems, various sensors, multiple external terminals, as well as to allow for the input of commands by a variety of means such as touchscreens, voice recognition systems, telephones, custom switches or any device capable of providing an input to a computer system. The system functions can be readily controlled by the user utilizing a high resolution graphics display and associated touchscreen interface.

1,080 citations

Book
01 Mar 1995
TL;DR: In this article, the authors describe the methods employed in the floating-point area of the System/360 Model 91 to exploit the existence of multiple execution units and register tagging schemes.
Abstract: This paper describes the methods employed in the floating-point area of the System/360 Model 91 to exploit the existence of multiple execution units Basic to these techniques is a simple common data busing and register tagging scheme which permits simultaneous execution of independent instructions while preserving the essential precedences inherent in the instruction stream The common data bus improves performance by efficiently utilizing the execution units without requiring specially optimized code Instead, the hardware, by 'looking ahead' about eight instructions, automatically optimizes the program execution on a local basis The application of these techniques is not limited to floating-point arithmetic or System/360 architecture It may be used in almost any computer having multiple execution units and one or more 'accumulators' Both of the execution units, as well as the associated storage buffers, multiple accumulators and input/output buses, are extensively checked

784 citations

Journal ArticleDOI
TL;DR: The methods employed in the floating-point area of the System/360 Model 91 to exploit the existence of multiple execution units are described, which permits simultaneous execution of independent instructions while preserving the essential precedences inherent in the instruction stream.
Abstract: This paper describes the methods employed in the floating-point area of the System/360 Model 91 to exploit the existence of multiple execution units. Basic to these techniques is a simple common data busing and register tagging scheme which permits simultaneous execution of independent instructions while preserving the essential precedences inherent in the instruction stream. The common data bus improves performance by efficiently utilizing the execution units without requiring specially optimized code. Instead, the hardware, by 'looking ahead' about eight instructions. automatically optimizes the program execution on a local basis. The application of these techniques is not limited to floating-point arithmetic or System/360 architecture. It may be used in almost any computer having multiple execution units and one or more 'accumulators.' Both of the execution units, as well as the associated storage buffers, multiple accumulators and input /output buses, are extensively checked.

597 citations

Patent
05 Jan 1995
TL;DR: In this paper, a CEBus-based energy management and building automation system including a local area network or home automation data bus such as the CEBus is described. But the second microcomputer serves as an input/output terminal, allowing the customer to set parameters and query the system as to power usage, displaying reports requested by the customer and messages transmitted by the utility company and by either microcomputer.
Abstract: An energy management and building automation system including a local area network or home automation data bus such as the CEBus. Each load is connected to the bus via a control module which may contain a circuit breaker to disconnect the load from the mains upon command or upon occurrence of a power outage. Current monitoring control modules measure load current and power monitor modules monitor power consumed by selected loads, both modules transmitting bus messages indicating load status and status changes. A first microcomputer preferably is external to the customer premises, adjacent the electric utility power meter. A second microcomputer preferably is inside the customer premises. The two microcomputers communicate with each other and with the various modules via the network/data bus. The first microcomputer communicates with the utility company via any appropriate communications link. The second microcomputer serves, in part, as an input/output terminal for the system, allowing the customer to set parameters and query the system as to power usage, displaying reports requested by the customer and messages transmitted by the utility company and by either microcomputer. The first microcomputer acts as a master controller and/or network server, communicating with the world outside the premises, as a communications gateway between voice, video and data services, and being the primary data collector and operator of load control modules; the second microcomputer provides certain backup functions. The utility company can access selected utilization data and control at least some loads via messages to the first microcomputer.

595 citations

Patent
Michael Farmwald1, Mark Horowitz1
16 Apr 1991
TL;DR: In this article, the authors present a memory subsystem comprising at least two semiconductor devices (15, 16, 17), including at least one memory device connected to a bus (18), where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address.
Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices (15, 16 , 17), including at least one memory device (15, 16 or 17), connected to a bus (18), where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices (15, 16 or 17), where the control information includes device-select information and the bus (18) has substantially fewer bus lines than the number of bits in a single address, and the bus (18) carries device-select information without the need for separated device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus (18) and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices (15, 16, 17). The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an Address Valid bus line carry address, data and control information for memory addresses up to 40 bits wide.

552 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202312
202229
202147
2020197
2019246
2018245