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Showing papers on "Systems architecture published in 1975"


Journal ArticleDOI
TL;DR: Current fault-tolerance practices in system architecture are reviewed and their relevance to software systems is discussed.
Abstract: Two complementary methods which are employed in order to assure reliable computing are fault-intolerance and fault-tolerance. Fault-intolerance depends on the elimination of the causes of unreliability prior to the start of the computing process while fault-tolerance employs protective redunuancy during the computing process in order to detect and to correct unreliable functioning. A balanced allocation of reliability resources between the two methods appears to offer the best practical solution. The paper reviews current fault-tolerance practices in system architecture and discusses their relevance to software systems.

78 citations


Patent
28 Apr 1975
TL;DR: In this article, the authors describe an architecture which makes possible the transmission and storage of data in an efficient and rapid manner by using a plurality of communication sites and computer sites which interact with each other by means of matrices having special properties.
Abstract: Communications and computer systems are described utilizing an architecture which makes possible the transmission and storage of data in an efficient and rapid manner. The system architecture embodies a plurality of communication sites and computer sites which interact with each other by means of matrices having special properties which permit the control, transmission and storage of data in many time and space saving ways. The matrices also serve as a means of governing the activities of the system. A plurality of computer sites act upon the data in the matrices by transforming, processing and transferring data for the communications network and processing loops. The processing loops provide the basic processing for the system and contain processing units which act independently and respond to the matrices. The matrices contain both the data which is to be operated upon and tutors (instructions) for directing the activities of the processing units. The system provides simultaneous services to a large number of users. The system does not contain a central processing unit (CPU) and its associated programs and does not require fetch, put and interrupt actions inherent in CPU programs. The system architecture, by virtue of the hardware and its special configuration, the matrices and their operation, and the response of the hardware to the matrices, confers great flexibility on the system's operations from both the communications and the computer standpoints.

38 citations


Proceedings ArticleDOI
01 Jan 1975
TL;DR: The paper reviews current fault-tolerance practices in system architecture and discusses their relevance to software systems.
Abstract: Two complementary methods which are employed in order to assure reliable computing are fault-intolerance and fault-tolerance. Fault-intolerance depends on the elimination of the causes of unreliability prior to the start of the computing process while fault-tolerance employs protective redunuancy during the computing process in order to detect and to correct unreliable functioning. A balanced allocation of reliability resources between the two methods appears to offer the best practical solution. The paper reviews current fault-tolerance practices in system architecture and discusses their relevance to software systems.

34 citations


Journal ArticleDOI
01 Nov 1975
TL;DR: In this article, a virtual machine system prototype has been constructed for the Digital Equipment Corporation PDP-11/45 and a case study of interactions between hardware and software developments is presented, together with conclusions motivated by that experience.
Abstract: At UCLA, a virtual machine system prototype has been constructed for the Digital Equipment Corporation PDP-11/45. In order to successfully implement that system, a number of hardware changes have been necessary. Some overcome basic inadequacies in the original hardware for this purpose, and others enhance the performance of the virtual machine software. Steps in the development of the modified hardware architecture, as well as relevant aspects of the software structure, are discussed. In addition, a case study of interactions between hardware and software developments is presented, together with conclusions motivated by that experience.

22 citations


Journal ArticleDOI
01 Nov 1975
TL;DR: A formal model of hardware/software architectures is developed and applied to Virtual Machine Systems and results are derived on the sufficient conditions that a machine architecture must verify in order to support VM systems.
Abstract: A formal model of hardware/software architectures is developed and applied to Virtual Machine Systems Results are derived on the sufficient conditions that a machine architecture must verify in order to support VM systems The model deals explicitly with resource mappings (protection) and with I/O devices Some already published results are retrieved and other ones, more general, are obtained

15 citations


Journal ArticleDOI
01 Nov 1975
TL;DR: A computer system design incorporating ideas of distributed processing and multiprocessing computer architectures is proposed, along with its impact on memory management and process control aspects of the system's operating system.
Abstract: The development of microprocessors has suggested the design of distributed processing and multiprocessing computer architectures. A computer system design incorporating these ideas is proposed, along with its impact on memory management and process control aspects of the system's operating system. The key design feature is to identify system processes with microprocessors and interconnect them in a hierarchy constructed to minimize intercommunication requirements.

11 citations


Journal ArticleDOI
J.H. Wensley1
TL;DR: The availability of mass storage devices with access times several orders of magnitude less than rotating-device memories will have varying impacts on computer system architectures, including architectures for transaction-based computing, real-time computing with nonresident programs, and more flexible structures for time-shared computers.
Abstract: The availability of mass storage devices with access times several orders of magnitude less than rotating-device memories will have varying impacts on computer system architectures. These effects will range from simple changes such as direct substitution for disks, where significant productivity increases can be easily achieved, through more radical changes where both hardware and software are changed in structure to exploit the potential of these new devices. Such changes include architectures for transaction-based computing, real-time computing with nonresident programs, and more flexible structures for time-shared computers.

11 citations


Journal ArticleDOI
TL;DR: It is shown that a very versatile and almost universal DAFCS can be configured to meet the general and peculiar needs associated with each aircraft application.
Abstract: Functional partitioning, redundancy structure, internal communications, and software modularization define the architecture of a digital automatic flight control system (DAFCS). Selection of a suitable system architecture for commercial transports involves such factors as the functional scope, growth provision and flexibility requirements, sensor interfaces, the aircraft's actuator and control surface redundancy, and the dispatch reliability requirements. Trade-offs concerning these various factors are discussed, and it is shown that a very versatile and almost universal DAFCS can be configured to meet the general and peculiar needs associated with each aircraft application. Specific results associated with this system's recent demonstration flights in the DC-10 aircraft, as well as examples from several other transport aircraft applications of the same DAFCS architecture, are used to illustrate the design concepts.

7 citations


Journal ArticleDOI
01 Nov 1975
TL;DR: The layering concepts and process concepts defining the system architecture of the MOSS Operating System are described and an overview of the specific functions and processes of the system are presented.
Abstract: Architecture is receiving increasing recognition as a major design factor for operating systems development which contributes to the clarity, and modifiability of the completed system. The MOSS Operating System uses an architecture based on hierarchical levels of system functions overlayed dynamically by asynchronous cooperating processes carrying out the system activities.Since efficient operation in a real time environment requires that the number of processes and process switches be kept to a minimum, the MOSS system uses processes only where a truly asynchronous activity is identified. The layers of the MOSS Operating System do not represent a hierarchical structure of virtual machine processes, but rather a hierarchy of functions used to create the processes.This paper describes the layering concepts and process concepts defining the system architecture. It also presents an overview of the specific functions and processes of the MOSS Operating System.

3 citations


Proceedings ArticleDOI
E. Douglas Jensen1
01 Jan 1975
TL;DR: In a distributed computer, processors may function as: special purpose components (e.g., decimal processing unit) in a larger processor; dedicated support processors; or multiple main (i.e., central) processors.
Abstract: It has recently become both technologically and economically feasible to produce a complete, general purpose, stored program process or on a small number of LSI circuits. This development has already begun to influence computer system architecture in the direction of distributed processing—the construction of a larger machine from a multiplicity of smaller ones. Critical issues in this effort appear to be process partitioning and assignment, interprocess communication, and processor interconnection. In a distributed computer, processors may function as: special purpose components (e.g., decimal processing unit) in a larger processor; dedicated support (e.g., I/O) processors; or multiple main (i.e., “central”) processors.

3 citations


Journal ArticleDOI
TL;DR: The ICL2900 hardware architecture is compared with that of the B6700/B7700, which is based on similar principles and is similar in overall design but has independent origins and differ in many important details.
Abstract: The ICL2900 hardware architecture is compared with that of the B6700/B7700. The two systems are based on similar principles and are similar in overall design. However, although the ICL2900 postdates the B6700 by seven years, the machines have independent origins and differ in many important details.

Journal ArticleDOI
TL;DR: An immproved solution to the problem of software design is offered, and its impact on traditional and future problem areas is outlined.
Abstract: Previous digital design experiences provide guidance and offer solutions for one of the newest digital technology applications: The commercial transport AFCS. In addition to facing well-documented problems of software control and maintainability, operational safety adds a new dimension to the requirements for software reliability. After a general discussion of the problems encountered in past digital system programs, this paper addresses the specific requirements of the commercial transport system and their implications in terms of system architecture and software development. An immproved solution to the problem of software design is offered, and its impact on traditional and future problem areas is outlined. A description of a prototype digital AFCS under development is presented. The experiences to date with this system reinforce the correctness of techniques and approaches used in its development.

Journal ArticleDOI
TL;DR: This paper was presented to the ARINC Avionics Engineering Seminar on DAFCS, Washington, D.C., May 1975 and discussed briefly in this paper.
Abstract: This paper was presented to the ARINC Avionics Engineering Seminar on DAFCS, Washington, D.C., May 1975. There has been a rapid growth in the use of digital avionics computers over the last decade. The digital inertial navigation computer, the digital ADC, and the digital headup display are now commonplace. The next generation of systems will be much more ambitious. They will move towards greater complexity such as that in the military DAIS system; they will include flight control systems and other applications where safety of flight is critical. A digital computer is often physically small in comparison with the total equipment in a system. However, its impact on the design and development of any system and on the certification of high integrity systems is out of proportion to its size. The source of this impact lies in the introduction of programmability into the systems. Introducing programmability has two effects. First, it introduces an activity and an end product (programming and programs) which are implicit in an analog system but impossible to identify independently. It therefore exposes readily identifiable nonrecurring costs which have previously been hidden. These costs and the activities can now be treated in the same way as any other engineering feature of the system; i.., controlled, documented, and subjected to quantifiable design trade-offs. The second effect of programmability is to complicate the failure characteristics of the system. In an analog electronic system, functional modules are wired together. Operations proceed in sequence through the system in an order determined by the module interwiring. This sequencing is controlled by the program in a digital computer system. A single error in either the program or its execution can \"scramble\" the following program sequences. The effect of the error is equivalent to a random rewiring of the analog modules. Failure effects in digital computers can be more diverse and more serious than in analog systems. Both effects of programmability must be clearly recognized and properly dealt with in engineering digital systems. Each is discussed briefly in this paper.

Proceedings ArticleDOI
22 Sep 1975
TL;DR: Practical experience in structuring a large amount of data (about 1000 reels of 7-track 556 binary code decimal magnetic tapes of 1970 census data) and the database architecture finally chosen is described.
Abstract: This paper describes practical experience in structuring a large amount of data (about 1000 reels of 7-track 556 binary code decimal magnetic tapes of 1970 census data). The hardware and software systems were given. The goal was to structure the database for online devices and to make the retrieval as efficient as possible. This paper explains only the database architecture finally chosen.

Proceedings ArticleDOI
11 Jun 1975
TL;DR: An instruction set for a special-purpose associative processor, designed for information storage and retrieval applications, is defined in APL/360 and these definitions are then used to test the validity of the system's architecture for the proposed applications.
Abstract: An instruction set for a special-purpose associative processor, designed for information storage and retrieval applications, is defined in APL/360. These definitions are then used to test the validity of the system's architecture for the proposed applications. This is accomplished by writing and simulating the execution of sample programs on a sample data set and selectively observing the corresponding transformations performed on the data set.

Proceedings ArticleDOI
01 Jan 1975
TL;DR: This paper presents a proposed communications method for a set of interconnected micro-processors that provides for a multitude of communication buses and the ability for simultaneous direct communication between all microcomputers connected to the same communication bus, which would be a single wire.
Abstract: From the results of research dealing with the overall system architecture of a nodal processor system, a major problem was the way in which nodes (individual) processors can effectively communicate with each other. This paper presents a proposed communications method for a set of interconnected micro-processors. The proposed communication system provides for a multitude of communication buses and the ability for simultaneous direct communication between all microcomputers connected to the same communication bus, which would be a single wire. Also any microcomputer within this structure can select to communicate over three different orthogonally arranged buses. To make this possible a special transmitter receiver circuit must be associated with each microcomputer. Although only one physical wire makes up an individual communication path, simultaneous direct communication is possible among any combination of microcomputers connected to a bus by phase modulation of individually selected binary orthogonal waveforms (Walsh Functions) generated by the special communications circuit. The information is separated in sequency [