Showing papers on "Systems architecture published in 1988"

Plans and resource-bounded practical reasoning

Abstract: An architecture for a rational agent must allow for means-end reasoning, for the weighing of competing alternatives, and for interactions betwen these two forms of reasoning. Such an architecture must also address the problem of resource boundedness. We sketch a solution of the first problem that points the way to a solution of the second. In particular, we present a high-level specification of the practical-reasoning component of an architecture for a resource-bounded rational agent. In this architecture, a major role of the agent's plans is to constrain the amount of further practical reasoning she must perform.

Smart sensing within a pyramid vision machine

Abstract: A machine is designed, based on a pyramid architecture, that supports smart sensing and related highly efficient processing. Key elements of the design are (a) hierarchical data structures for image representation, (b) fine-to-coarse algorithms for the fast generation of image measures, (c) coarse-to-fine search strategies that rapidly locate objects or events within a scene, and (d) high-level control mechanisms that guide data gathering even as visual information is being interpreted. This system, known as the Pyramid Vision Machine, achieves high performance at modest cost. Design considerations and several applications are described. >

Active database management systems

Abstract: Conventional passive database management systems are inadequate for time-constrained applications, because they either do not provide timely response to critical situations or compromise modularity. Active database management systems attempt to provide both modularity and timely response, by allowing event-condition-action rules to be specified declaratively; when events of interest occur, they efficiently evaluate the corresponding conditions, and if these conditions are satisfied, they trigger the corresponding actions. The development of active database management systems requires the solution of a number of research problems in the areas of knowledge modelling, execution modelling, condition monitoring, scheduling, system architecture, and performance evaluation. This paper describes the principal research issues in each of these areas, surveys the approaches being taken in a number of research projects on active DBMSs, and emphasizes the approaches we are taking in the HiPAC (High Performance ACtive DBMS) project.

A ‘complexity level’ analysis of immediate vision

Abstract: This paper demonstrates how serious consideration of the deep complexity issues inherent in the design of a visual system can constrain the development of a theory of vision. We first show how the seemingly intractable problem of visual perception can be converted into a much simpler problem by the application of several physical and biological constraints. For this transformation, two guiding principles are used that are claimed to be critical in the development of any theory of perception. The first is that analysis at the ‘complexity level’ is necessary to ensure that the basic space and performance constraints observed in human vision are satisfied by a proposed system architecture. Second, the ‘maximum power/minimum cost principle’ ranks the many architectures that satisfy the complexity level and allows the choice of the best one. The best architecture chosen using this principle is completely compatible with the known architecture of the human visual system, and in addition, leads to several predictions. The analysis provides an argument for the computational necessity of attentive visual processes by exposing the computational limits of bottom-up early vision schemes. Further, this argues strongly for the validity of the computational approach to modeling the human visual system. Finally, a new explanation for the pop-out phenomenon so readily observed in visual search experiments, is proposed.

A display system for the Stellar graphics supercomputer model GS1000

Abstract: This paper describes a high performance display system that has been incorporated into the overall architecture of the Stellar Graphics Supercomputer Model GS1000. The display system is tightly coupled to the CPU, memory system and vector processing unit of this supercomputer, and is capable of rendering 150,000 shaded triangles/sec, and 600,000 short vectors/sec. The goal of the architecture is to share hardware resources between the CPU and display system and achieve a high bandwidth connection between them. This coupling of the display system and the processor, the architecture of the rendering processor, and the two ASICs that are used to implement the rendering processor are described.In addition, the display system architecture is contrasted to other approaches to high performance graphics, and design trade-offs and possible extensions are described. The implementation of popular display algorithms on the architecture is discussed, and their performance specified. The reader is advised that Stellar Computer Inc. is seeking patent protection for work described in this paper.

An overview of the Etherphone system and its applications

Abstract: The Etherphone system has been developed to explore methods for extending existing multimedia office environments with the facilities needed to handle the transmission, storage, and manipulation of voice. Based on a hardware architecture that uses microprocessor-controlled telephones to transmit voice over an Ethernet that also supports a voice file server and a voice synthesis server, this system has been used for applications such as directory-based call placement, call logging, call filtering, and automatic call forwarding. Voice mail, voice annotation of multimedia documents, voice editing using standard text-editing techniques, and applications of synthetic voice use the Etherphones for voice transmission. Recent work has focused on the creation of a comprehensive voice system architecture, both to specify programming interfaces for custom uses of voice, and to specify the roles of different system components, so that equipment from multiple vendors could be integrated to provide sophisticated voice services. >

Hypertext and CASE

Abstract: Computer-aided software engineering (CASE) systems require a database system that must let designers logically associate documentation and source code, make annotations to record explanations and assumptions, and manage different versions of the software. The author reports the development of a database, Neptune, which demonstrates that hypertext provides an appropriate data model for CASE systems. Hypertext is a medium-grained, entity-relationship-like data model that lets information be structured arbitrarily and keeps a complete version history of both information and structure. Neptune achieves application independence by using a layered system architecture; at the bottom is a transaction-based server, the Hypertext Abstract Machine, and layered above it are applications and the user interface. The use of Neptune in the Dynamic Design CASE environment is discussed. >

OFMspert: inference of operator intentions in supervisory control using a blackboard architecture

Abstract: The authors proposes an architecture for an expert system that can function as an operator's associate in the supervisory control of a complex dynamic system. Called OFMspert (operator function model (OFM) expert system), the architecture uses the operator function modeling methodology as the basis for the design. The authors put emphasis on the understanding capabilities, i.e. the intent referencing property, of an operator's associate. They define the generic structure of OFMspert, particularly those features that support intent inferencing. They also describe the implementation and validation of OFMspert in GT-MSOCC (Georgia Tech-Multisatellite Operations Control Center), a laboratory domain designed to support research in human-computer interaction and decision aiding in complex, dynamic systems. >

The Horizon supercomputing system: architecture and software

Abstract: Horizon is the name currently being used to refer to a shared-memory Multiple Instruction stream - Multiple Data stream (MIMD) computer architecture under study by independent groups at the Supercomputing Research Center and at Tera Computer Company. Its performance target is a sustained rate of 100 giga (1011) Floating Point Operations Per Second (FLOPS). Horizon achieves this speed with a few hundred identical scalar processors. Each processor has a horizontal instruction set that allows the production of one or more floating point results per cycle without resorting to vector operations. Memory latency is hidden, assuming enough parallelism is available, by allowing processors to switch context on each machine cycle.In this overview, the Horizon architecture is introduced and its performance is estimated. The processor instruction set and a simple programming example are given. Additional details on the processor architecture, interconnection network design, performance analyses, machine simulator, compiler development, and application studies can be found in companion papers.

EXGT-S: A knowledge based system for group technology

Abstract: In this paper a knowledge based system (EXGT-S) for solving the generalized group technology problem is presented. The formulation of the group technology problem involves constraints related to machine capacity, material handling system capabilities, machine cell dimensions and technological requirements. Il has been developed for an automated manufacturing system. EXGT-S is based on the tandem system architecture presented in Kusiak (1987). It considers alternative process plans and multiple machines. EXGT-S takes advantage of the developments in expert systems and optimization. Two basic components of the knowledge based system, namely the expert system and heuristic clustering algorithm are discussed. Each partial solution generated by the clustering algorithm is evaluated by the expert system which modifies search directions of the algorithm.

Tree structured fiber optics MANs

Abstract: A fiber-optic architecture, Tree-Net, is introduced that does not require intermediate processing components and supports a large number of stations. Tree-Net is based on a tree topology, passive station taps, and implicit token protocol. The properties and performance of Tree-Net are evaluated. It is shown that the basic topology and access scheme of Tree-Net can be extended so that a family of tree-structured fiber-optic MANs (metropolitan area networks) can be defined to suit different needs, including data, voice, and video integration. >

Reliability model generator

Abstract: An improved method and system for automatically generating reliability models for use with a reliability evaluation tool is described. The reliability model generator of the present invention includes means for storing a plurality of low level reliability models which represent the reliability characteristics for low level system components. In addition, the present invention includes means for defining the interconnection of the low level reliability models via a system architecture description. In accordance with the principles of the present invention, a reliability model for the entire system is automatically generated by aggregating the low level reliability models based on the system architecture description.

Communication network issues and high-density interconnects in large-scale distributed computing systems

Abstract: The authors discuss the impact of the physical interconnection environment through which the concurrent processes among locally distinct computing nodes of large-scale multicomputer systems are coupled. The communication capabilities implied for massively parallel computing systems by fine-grain task partitioning and by fine-grained communications are discussed in detail. Wafer-scale and hybrid wafer-scale system technologies which would support such communications are described. >

ABE: an environment for engineering intelligent systems

Abstract: The ABE multilevel architecture for developing intelligent systems addresses the key problems of intelligent systems engineering: large-scale applications and the reuse and integration of software components. ABE defines a virtual machine for module-oriented programming and a cooperative operating system that provides access to the capabilities of that virtual machine. On top of the virtual machine, ABE provides a number of system design and development frameworks, which embody such programming metaphors as control flow, blackboards, and dataflow. These frameworks support the construction of capabilities, including knowledge processing tools, which span a range from primitive modules to skeletal systems. Finally, applications can be built on skeletal systems. In addition, ABE supports the importation of existing software, including both conventional and knowledge processing tools. >

A functional approach to integrating database and expert systems

Abstract: A new system architecture shares certain characteristics with database systems, expert systems, functional programming languages, and spreadsheet systems, but is very different from any of these.

The intelligent network and forward-looking technology

Abstract: The authors discuss the Advanced Intelligent Network (AIN), an architecture that includes both IN/1+ and IN/2 and will be introduced in phases, with releases envisioned at two-year intervals. Phase 1 requirements will be released in 1989 and first applications are targeted for deployment in 1991/2. They examine some future technologies and their impact on the AIN. They describe an AIN system architecture that can respond to change, concentrating on the effect of switching-system evolution to narrowband and broadband ISDN. >

Software environment architectures and user interface facilities

Abstract: The authors discuss the demands and constraints on a user interface management system for a software environment, and the relation between the architecture of the environment and the user interface management system. A model for designing user interface management systems for large extensible environments is presented. This model synthesizes several recent advances in user interfaces and specializes them to the domain of software environments. The model can be applied to a wide variety of environment contexts. A prototype implementation is described. >

Adissa: architectural design of information systems based on structured analysis

Abstract: ADISSA is a methodology for Architectural Design of Information Systems and Software, based on Structured Analysis. The architectural design includes: (a) design of a tree-structured menu system, which interfaces between the users and the system-viewed as the "external architecture" of the system; and (b) design of the transactions of the system, composed of various functions which are activated in response to user needs and various events in the universe of discourse-viewed as the "internal architecture" of the system. The menu tree and the transactions are tied up with the other major components of the system architecture: the inputs and outputs, and the database. ADISSA methodology is fully compatible and consistent with Structured Analysis, and therefore the stages of system analysis and design are integrated into one complete process.

AIRBUS and ATR System Architecture and Specification

Abstract: Design diversity is widely used on board of the aircraft for which AEROSPATIALE has the design responsibility. Indeed, all the aircraft currently in production, and all the aircraft designed since the end of the 70’s are using dissimilar software. The current (mid-1986) number of such aircraft is 120 AIRBUS, and 20 ATR.42. A lot of different functions are computerized with dissimilar software. The principal ones are the automatic and electric flight control systems (“automatic pilot” and “Fly by Wire”), and the flight instruments.

CATHEDRAL II—a computer-aided synthesis system for digital signal processing VLSI systems

Abstract: Describes the concepts and the status of the CATHEDRAL-II silicon compiler for digital signal processing systems. It is shown that efficient layout synthesis is possible, starting from a very high-level behavioural description of a system, owing to the careful definition of a target architectural design style and an application domain. An overview is presented of the different synthesis tools which have been or are being developed, both for architectural synthesis and optimisation, and for module and layout generation. With the underlying design methodology, the world of silicon design will become accessible to system engineers.

Very high speed and high capacity packet switching for broadband ISDN

Abstract: The authors discuss and propose a very-high-speed and high-capacity packet-switching (HPS) architecture for a future broadband ISDN (integrated-services digital network). The HPS network accommodates various communication services, such as voice, high-speed data, high-speed still picture, and video services. The proposed architecture has three significant principles: a high-speed oriented simple network protocol, separation of signaling and network control from data transfer, and hardware switching. These principles provide fast- and high-throughput transmission for data packets and reliable transmission and processing for call-control packets. The HPS protocol structure is addressed, which provides high flexibility for various communications services as well as high-speed capability. A 3-Gb/s capacity and building-block-structured packet-switching system architecture, using bus- and loop-type switch fabric, is also presented. >

Optimally universal parallel computers

Abstract: A key property of the von Neumann architecture for sequential computers is efficient universality. It can simulate arbitrary programs written in appropriate high-level languages in time proportional to that which they would take if special-purpose sequential machines were built for each of them. This makes possible standardized languages and transportable software, without which the level of pervasiveness that computers have now reached would be difficult to imagine.

Rosette: An object-oriented concurrent systems architecture

Abstract: A number of concurrent computers have been designed, such as [Ametek 1988] and [NCUBE 1986]. Taking advantage of concurrency on these computers will require new languages, operating systems, and environments to support the programming, monitoring and control of applications. The Rosette project at MCC is developing a system architecture for general-purpose concurrent computation based on the Actor model [Agha 1986]. The aim of the Rosette architecture is to support the use of concurrent computers in solving computationally intensive problems whose structure is not statically determined. The architecture will support variable grain size, dynamic resource management, reflection, and heterogeneity.A number of concurrent language proposals have employed computational models that are limited in their applicability because of assumptions such as granularity of concurrency, static process topology, or inherent communications cost. Others, for example, functional programming, cannot be used to model shared, modifiable objects. The Actor model addresses these issues directly.However, the difficulties of using concurrent computers cannot be addressed solely through programming languages. Traditional operating systems treat each process as an independent entity for the purposes of resource management (i.e., for the run-time allocation of processor, storage, and communication resources.) In the context of concurrent applications, effective operation on a concurrent computer requires that communities of processes be managed together, taking into account the ways in which they interact, and providing for the application itself to guide resource management.For example, consider that programming systems often provide only limited support for the control of resource consumption in search problems in the face of combinatorial explosion; further, it is generally recognized that to optimize search performance, it is useful to vary the resources provided depending on how promising intermediate results of a given path are judged to be. The Rosette architecture will allow the programmer to integrate high-level algorithms within the application for dividing resources dynamically among the sub-computations that are spawned. These algorithms will provide an assessment of the progress of the sub-computations, and will be used to make the large number of low-level resource management decisions that are necessary in carrying out the computation. Thus, operating system functionality will be folded into the application.The Rosette architecture has two major components: an interface layer and a system environment. The interface layer provides mechanisms for the monitoring and control of concurrent applications. It supports a uniform view of the system resources and applications through the use of actors and message-passing semantics. The interface layer includes a set of actors that represent the processing, storage and communication resources across the hardware base. The system environment contains actor communities which implement resource management policies, and support for programming concurrent applications. The environment consists of an extensible set of actors that are organized via a class-based object model. These actors provide monitoring, debugging, resource management system simulation, and compilation/transformation facilities.To demonstrate the effectiveness of the Rosette architecture, as well as to drive its development, two classes of applications are being used. The first class is the Rosette system itself: all of the system components necessary for resource management, monitoring, debugging, and program development are being constructed in the Rosette language and will take full advantage of both concurrency and object-oriented programming support. The second category of applications is chosen to be somewhat independent of the Rosette system so as to ensure adequate feed-back concerning applicability to domains other than software engineering. These applications are in the general area of knowledge-based signal interpretation.The Rosette architecture is implemented via a concurrent object-oriented programming language that provides the following features: Inherent concurrency: A declarative approach is needed which allows fine-grained concurrency to arise naturally from the program. If the programmer is forced to express all of the details of the concurrent execution of an application, it becomes difficult to re-map a given program to different concurrent computers which have varying concurrency characteristics.Dynamic creation/modification of objects: This allows the system to be extensible and reconfigurable.Sharing: The language should support mechanisms such as inheritance so that code, structure, and values need not be replicated.Classes: Objects can be organized into classes to permit more effective management of resources, as for example in a very large database. Classes should be first-class objects and hence it should be possible to create classes dynamically.The Rosette language is a high-level language that is translated into a base language that directly expresses concurrent computations in terms of the semantics of the Actor model. The Rosette language extends the base language with data abstraction facilities and a library of classes, and is used to implement the non-built-in actors of the interface layer, components of the system environment, and applications.Using data abstraction extensions to the base language, the Rosette language organizes actors into classes according to common sets of behaviors and local state. Inheritance is used as a means of sharing code and structure that is common among classes. There is considerable evidence, for example [LaLonde 1986] and [Snyder 1987], that a robust class system should support separate hierarchies that represent what is modeled by a class and how some class of objects are actually implemented. Our approach is to use three different kinds of classes to organize the various kinds of actors in a system and information about these actors: abstract classes specify observable requests, responses, and actions;representation classes specify resource management characteristics of implementations; andbehavior classes contain the actual implementations.Associated with an abstract class is the set of representations that are available to implement the particular abstraction. Each representation is associated with the behavior class that contains the corresponding implementation. The power of this separation is that each of the three kinds of class may be related to others in a class hierarchy. This means that the relationships between abstract classes are not forced to have the same structure as the relationships among implementations. Sharing via inheritance among behavior classes is related to engineering concerns; relations among abstract classes are dictated by external/observable behavior. As an example, an abstract class might specify the operations available over real-matrices. There are several ways of representing a matrix as a community of actors, and each of these would be specified with appropriate representation and behavior classes. There is a well-defined abstract hierarchy of matrices such as invertible, positive, etc. These abstract kinds of matrices are independent of the various implementations, which may be chosen according to application and hardware resource constraints.The Rosette language embodies a reflective model of the interface layer that is similar to that used in ABCL/R, [Watanabe and Yonezawa 1988]. This model is termed the execution model and provides an abstract implementation of an actor in terms of other resource actors. There are three classes of resource actors in the model: container, processor, and mailbox.The container class of resource actor models the storage local to an actor, and is very similar to a frame or unit in knowledge-based systems. A container is a set of slots, where each slot is an association of a key and a value. Both keys and values are just other actors. Slots can be added or deleted from a container. These actions model allocation and deallocation of storage.The basic operation performed by processor resource actors is the execution of a message, which defines how to determine the method for responding to a message. An evaluation context is then created and the method is applied to the context and the message.The third class of resource actors implements the communications interface to an actor. The main function of a mailbox is the buffering of incoming messages until they are requested by a processor. Mailboxes respond to requests that signify message arrivals at the actor and to requests which are used by processors to accept messages.Object-oriented interfaces for each of the three kinds of resource actors are defined and organized in a class hierarchy. For any actor, any combination of these three resource actors may be built-in or not. The possibility of defining new resource actors within the context of the execution model makes the Rosette architecture extensible - allowing new forms of monitoring and control to be defined. Resource management policies are defined in terms of interactions among the resource actors of an application's actor community.

Design and analysis of very high-speed network architectures

Abstract: Communication architectures for very-high-speed networks are dealt with. The use of high communication speed increases the ratio between the end-to-end propagation delay and the packet transmission time. This increase restricts the utilization of the high system bandwidth in broadcast channel-based systems, causing a rapid performance deterioration. A communication system architecture characterized by the use of several parallel channels and design of the nodes' channel interface is presented. The channel-division approach is introduced, showing that for a given system bandwidth the total system capacity will be increased by bandwidth division and parallel communication. An analytic model of this system is developed, from which the proposed system's performance is obtained and performance bounds determined for multichannel slotted finite systems. The results show that the architecture has a potential to improve significantly the system performance compared to conventional single-channel-based systems. Furthermore, for a given network configuration an optimal architecture can be found which simultaneously maximizes the system throughput and minimizes the average packet delay. >

VSAT networks: architectures, protocols, and management

Abstract: VSAT (very-small-aperture terminal) satellite networks, are discussed, focusing on a particular network called STARCOM. The STARCOM system architecture is presented. A multiple-access protocol developed specifically for the STARCOM system is described and its performance is examined. The management capabilities of the STARCOM system are considered in detail. >

A performance study of broadcast information delivery systems

Abstract: The authors consider a videotex system architecture where user requests are processed by a service computer, and the requested information pages are broadcast to all users. Due to the large volume of information that is typically available, a secondary storage device, such as a disk, is used to hold the database. However, a small fraction of the information pages may be kept in main memory. A detailed simulation model is used to study the performance of this system architecture. Features such as scheduling page broadcasts, memory management, and disk scheduling are represented explicitly in the model. Simulation results are presented to show the response-time performance of various memory-management and disk scheduling strategies. >

The Horizon supercomputing system: architecture and software

Abstract: An overview is given of Horizon, a shared-memory multiple-instruction-stream-multiple-data-stream computer architecture currently under study Its performance target is a sustained rate of 100 GFLOPS (billions of floating-point operators per second), using a few hundred identical scalar processors The Horizon architecture is described and its performance is estimated The processor instruction set and a simple programming example are given

The 80960 microprocessor architecture

Abstract: Overview history and methodology the core architecture the numerics architecture the protected architecture bus and external signals the implementation 80960 performance.

TRAM: a design methodology for high-performance, easily testable, multimegabit RAMs

Abstract: An architecture is proposed for multimegabit dynamic RAMs (random-access memories) that achieves higher testability and performance than the conventional four-quadrant RAMs. Applying the principle of divide and conquer, the RAM is partitioned into modules, each appearing as the leaf node of a binary interconnect network. Such a network carries the address/data/control bus, permitting the nodes to communicate among themselves as well as with the outside world. This architecture is shown to be easily testable. Parallelism in testing and partial self-test result in a large savings of testing time; the savings is independent of the test algorithm used. Unlike other testability schemes, this approach promises improved performance with only a small increase in chip area. It is also shown that the architecture is easily partionable and restructurable, with potential for yield and reliability improvement. >