Showing papers on "Systems architecture published in 1989"
TL;DR: The Cydra 5 numeric processor, based on a directed-data-flow architecture, provides consistently high performance on a broader class of numerical computations.
Abstract: The Cydra 5 is a heterogeneous multiprocessor system that targets small work groups or departments of scientists and engineers. The two types of processors are functionally specialized for the different components of the work load found in a departmental setting. The Cydra 5 numeric processor, based on a directed-data-flow architecture, provides consistently high performance on a broader class of numerical computations. The interactive processors offload all nonnumeric work from the numeric processor, leaving it free to spend all its time on the numeric application. The I/O processors permit high-bandwidth I/O transitions with minimal involvement from the interactive or numeric processors. The system architecture and data-flow architecture are described. The numeric processor decisions and tradeoffs are examined, and the main memory system is discussed. Some reflections on the design issues are offered. >
313 citations
01 Jan 1989
TL;DR: Following a brief review of the fundamentals of disk system architecture, the characteristics of the applications that demand high I/O system performance are described and conventional ways to improve disk performance are discussed.
Abstract: Following a brief review of the fundamentals of disk system architecture, the characteristics of the applications that demand high I/O system performance are described. Conventional ways to improve disk performance are discussed. New developments in disk array systems are introduced, and controller architectures are described. >
217 citations
Patent•
07 Jul 1989TL;DR: In this article, a general purpose expert system architecture for diagnosing faults in any one of a plurality of machines includes a machine information database containing information on characteristics of various components of the machines to be diagnosed and a sensory input database which contains vibration data taken at predetermined locations on each machine.
Abstract: A general purpose expert system architecture for diagnosing faults in any one of a plurality of machines includes a machine information database containing information on characteristics of various components of the machines to be diagnosed and a sensory input database which contains vibration data taken at predetermined locations on each of the machines. The system knowledge base contains a plurality of general rules that are applicable to each of the plurality of machines. The generality of diagnosis is accomplished by focusing on components that make up the machine rather than individual machines as a whole. The system architecture also permits diagnosis of machines based on other parameters such as amperage, torques, displacement and its derivatives, forces, pressures and temperatures. The system includes an inference engine which links the rules in a backward chaining structure.
177 citations
TL;DR: A hierarchical functional intelligent autonomous control architecture is introduced here and its functions are described in detail.
Abstract: Autonomous control systems are designed to perform well under significant uncertainties in the system and environment for extended periods of time, and they must be able to compensate for system failures without external intervention. Intelligent autonomous control systems use techniques from the field of artificial intelligence to achieve this autonomy. Such control systems evolve from conventional control systems by adding intelligent components, and their development requires interdisciplinary research. A hierarchical functional intelligent autonomous control architecture is introduced here and its functions are described in detail. The fundamental issues in autonomous control system modelling and analysis are discussed.
149 citations
01 Jan 1989
TL;DR: The authors propose a ring VLSI systolic architecture for implementing artificial neural networks (ANNs) with applications to robotic processing that can accommodate all the useful neural networks for robotic processing.
Abstract: The authors propose a ring VLSI systolic architecture for implementing artificial neural networks (ANNs) with applications to robotic processing. Key design issues concerning algorithms, applications, and architectures are examined. A variety of neural networks is considered, including single-layer feedback neural networks, competitive learning networks, and multilayer feed-forward networks. It is demonstrated that the ANNs are suitable to all three levels of robotic processing applications including task planning, path planning, and path control levels. For these applications, a programmable systolic array is developed than can exploit the strength of VLSI to provide intensive and pipelined computing. Both the retrieving and learning phases are integrated in the design. The proposed architecture, which is more versatile than other existing ANNs, can accommodate all the useful neural networks for robotic processing. >
146 citations
TL;DR: The processor component of the Hewlett-Packard Precision Architecture system is described and its goals, how the architecture addresses the spectrum of general-purpose user information processing needs, and some architectural design tradeoffs are examined.
Abstract: The processor component of the Hewlett-Packard Precision Architecture system is described. The architecture's goals, how the architecture addresses the spectrum of general-purpose user information processing needs, and some architectural design tradeoffs are examined. Extendibility and longevity features are considered. >
137 citations
TL;DR: A massively parallel fine-grained SIMD (single-instruction multi-data-stream) computer for machine vision computations is described, which achieves solution time that is superior or equivalent to that of popular vision architectures such as mesh, tree, pyramid and hypercube for many vision algorithms discussed.
Abstract: A massively parallel fine-grained SIMD (single-instruction multi-data-stream) computer for machine vision computations is described. The architecture features a polymorphic-torus network which inserts an individually controllable switch into every node of the two-dimensional torus such that the network is dynamically reconfigurable to match the algorithm. Reconfiguration is accomplished by circuit switching and is achieved at fine-grained level. Using both the processor coordinate in the torus and the data for reconfiguration, the polymorphic-torus achieves solution time that is superior or equivalent to that of popular vision architectures such as mesh, tree, pyramid and hypercube for many vision algorithms discussed. Implementation of the architecture is given to illustrate its VLSI efficiency. >
133 citations
TL;DR: Signal processing hardware and software that can be used to improve the detection of certain power system faults using computer relays are discussed and the use of a knowledge-based environment to modify protection criteria is suggested.
Abstract: Signal processing hardware and software that can be used to improve the detection of certain power system faults using computer relays are discussed. Integrated systems and architectures for monitoring several fault-sensitive parameters have been investigated. A suggested architecture utilizing several processors is presented. Several fault-sensitive parameters for the detection of arcing faults are presented. A detection methodology based on these parameters is described, and a partial solution to the problem of directionality is discussed. The use of a knowledge-based environment to modify protection criteria is suggested. >
124 citations
TL;DR: An architecture for expert control is described where two concurrent processes are used for the knowledge-based system and the numerical algorithms, and a modular, blackboard-based approach is used.
88 citations
TL;DR: Results of simulations are given which show the stochastic architecture gives results similar to those found using standard analog neural networks or simulated annealing.
Abstract: A digital architecture which uses stochastic logic for simulating the behavior of Hopfield neural networks is described. This stochastic architecture provides massive parallelism (since stochastic logic is very space-efficient), reprogrammability (since synaptic weights are stored in digital shift registers), large dynamic range (by using either fixed- or floating-point weights), annealing (by coupling variable neuron gains with noise from stochastic arithmetic), high execution speed ( approximately=N*10/sup 8/ connections per second), expandability (by cascading of multiple chips to host large networks), and practicality (by building with very conservative MOS device technologies). Results of simulations are given which show the stochastic architecture gives results similar to those found using standard analog neural networks or simulated annealing. >
86 citations
TL;DR: The author presents a knowledge-based approach to enhance and support communication between humans and computers that has an explicit communication channel between the human and the hardware and an implicit communication channelBetween the human's knowledge base and the computer's stored knowledge.
Abstract: The author presents a knowledge-based approach to enhance and support communication between humans and computers. His system architecture has an explicit communication channel between the human and the hardware and an implicit communication channel between the human's knowledge base and the computer's stored knowledge. The author uses two intelligent support systems, Framer and Crack, to illustrate this concept. He concludes with a pragmatic description of lessons learned and problems ahead. >
TL;DR: It is found that patterns can be formulated for quite complex problems in relatively small pattern recognizers, by eschewing generality and concentrating on likely patterns and their redundancies.
01 Oct 1989
TL;DR: The authors describe a fully implemented computational architecture (CONDOR) that controls the Utah-MIT dexterous hand and other complex robots and provides the facilities out of which more powerful utilities such as a multiprocessor pseudo-terminal emulator, a transparent and fast file server, and a flexible symbolic debugger could be constructed.
Abstract: The authors describe a fully implemented computational architecture (CONDOR) that controls the Utah-MIT dexterous hand and other complex robots. The architecture derives its power from the highly efficient real-time environment provided for its control processors, coupled with a development host that allows flexible program development. By mapping the memory of a dedicated group of processors into the address space of a host computer, efficient sharing of system resources between them is possible. The software is characterized by a few simple design concepts but provides the facilities out of which more powerful utilities such as a multiprocessor pseudo-terminal emulator, a transparent and fast file server, and a flexible symbolic debugger could be constructed. >
TL;DR: This paper discusses several issues related to the design and implementation of a system architecture which can serve as the basis for integration of new technologies into manufacturing companies.
Abstract: The advent of sophisticated automation equipment and computer hardware and software is changing the way manufacturing is carried out. To be competitive, manufacturing companies must integrate these new technologies into their existing and future factories. In addition, they must integrate the planning, control and data management methodologies needed to make effective use of these technologies. This paper discusses several issues related to the design and implementation of a system architecture which can serve as the basis for integration. The architecture includes separate architectures for production planning and control, data management and data communications.
11 Dec 1989
TL;DR: In this article, the authors describe the findings of a feasibility study into the means of provisioning a GSM cellular radio environment inside passenger aircraft and discuss the background and capacity estimates for such a system.
Abstract: The author describes the findings of a feasibility study into the means of provision of a GSM cellular radio environment inside passenger aircraft. The background and capacity estimates for such a system are discussed prior to the presentation of a description of proposed system architecture. This description includes topics such as network organisation, handover, transmission delay compensation, signalling, the RF link and the aeronautical transponder implementation.
TL;DR: In this article, a modular approach for shape optimization of three-dimensional solid structures is described, where a hybrid approach based on the material derivative concept is developed to obtain shape sensitivities by post processing finite element results stored on files.
TL;DR: A highly versatile communication architecture, the bisectional interconnection network, is proposed which possesses many attractive features such as small internode distances, ability to do self-routing which is easily extendible to failure conditions, and the capability of maximal fault tolerance.
Abstract: A highly versatile communication architecture, the bisectional interconnection network, is proposed. These networks possess many attractive features such as small internode distances, ability to do self-routing which is easily extendible to failure conditions, and the capability of maximal fault tolerance. The proposed architecture allows optimal implementation of various logical configurations. Furthermore, the authors propose the use of a combinatorial structure, called the symmetric balanced incomplete block design (SBIBD), to partition these networks. This important property of partitioning allows the system's expansion with fault tolerance and is utilized to describe two semidistributed fault-diagnostic strategies which require remarkably low overhead and at the same time identify a large number of faulty nodes. Furthermore, based on SBIBDs, a unique approach for making the diagnostic scheme itself fault tolerant is proposed. >
01 Jan 1989
TL;DR: This paper presents a specification-methodology for distributed computer architectures based on the axiomatic architecture description language AADL, which allows for a modular and concise specification of multiprocessor architectures at levels of abstraction ranging from compiler/operating-system interface down to chip-level.
Abstract: This paper presents a specification-methodology for distributed computer architectures based on the axiomatic architecture description language AADL. AADL allows for a modular and concise specification of multiprocessor architectures at levels of abstraction ranging from compiler/operating-system interface down to chip-level. The specification method is illustrated by several examples taken from an AADL-definition of an abstract view of DOOM, a distributed object oriented machine, currently developed at Philips Research Laboratories, Eindhoven within ESPRIT-project 415.
09 Nov 1989
TL;DR: A system architecture for intelligent implantable biotelemetry instruments is presented, which consists of a modular chip set interconnected by a synchronous serial bus and an advanced telemetry unit that allows bidirectional communication of both data and commands.
Abstract: A system architecture for intelligent implantable biotelemetry instruments is presented. The system consists of a modular chip set interconnected by a synchronous serial bus. A user-programmable microprocessor controls all functions, including data acquisition, actuator control and telemetry. Data acquisition is performed by an eight-channel conditioning chip with programmable gain, bandwidth, and sampling rates. An advanced telemetry unit allows bidirectional communication of both data and commands, while providing an error-detection scheme to ensure integrity. >
TL;DR: The SIMD ‐ vector architecture mapping, the highly vectorized simulator in which it is used, and how the result was a simulator that achieved a level of performance three orders of magnitude faster than the conventional uniprocessor approach are described.
Abstract: A software behavioural simulator for a new massively parallel single-instruction/multiple data (SIMD) architecture has been developed that can accurately simulate the entire 16, 384 bit-serial processor array. The key to this high performance modelling is the exploitation of an inherent mapping that exists between massively parallel SIMD architectures and the vector architectures used in many high performance scientific super-computers. The new SIMD architecture, called BLITZEN, is based on the Massively Parallel Processor (MPP) built for NASA by Goodyear in the late 1970s. By simulating the full-scale machine with very high performance, the simulator allows development of algorithms and high-level software to proceed before realization of the hardware. This paper describes the SIMD - vector architecture mapping, the highly vectorized simulator in which it is used, and how the result was a simulator that achieved a level of performance three orders of magnitude faster than the conventional uniprocessor approach.
01 Mar 1989
TL;DR: The Mosaic C is an experimental fine-grain multicomputer based on single-chip nodes that provides low-overhead and low-latency handling of message packets, and high memory and network bandwidth, and the runtime system, written in C+-, provides automatic process placement and highly distributed management of system resources.
Abstract: The Mosaic C is an experimental fine-grain multicomputer
based on single-chip nodes. The Mosaic C chip includes 64KB of fast dynamic RAM,
processor, packet interface, ROM for bootstrap and self-test, and a two-dimensional selftimed
router. The chip architecture provides low-overhead and low-latency handling of
message packets, and high memory and network bandwidth. Sixty-four Mosaic chips are
packaged by tape-automated bonding (TAB) in an 8 x 8 array on circuit boards that can, in
turn, be arrayed in two dimensions to build arbitrarily large machines. These 8 x 8 boards are
now in prototype production under a subcontract with Hewlett-Packard. We are planning
to construct a 16K-node Mosaic C system from 256 of these boards. The suite of Mosaic
C hardware also includes host-interface boards and high-speed communication cables. The
hardware developments and activities of the past eight months are described in section 2.1.
The programming system that we are developing for the Mosaic C is based on the
same message-passing, reactive-process, computational model that we have used with earlier
multicomputers, but the model is implemented for the Mosaic in a way that supports finegrain
concurrency. A process executes only in response to receiving a message, and may in
execution send messages, create new processes, and modify its persistent variables before
it either exits or becomes dormant in preparation for receiving another message. These
computations are expressed in an object-oriented programming notation, a derivative of
C++ called C+-. The computational model and the C+- programming notation are
described in section 2.2. The Mosaic C runtime system, which is written in C+-, provides
automatic process placement and highly distributed management of system resources. The
Mosaic C runtime system is described in section 2.3.
TL;DR: Using concepts well established in the wider field of information systems science, a framework that characterizes a GIS on the three-fold basis of the problem-processor model, database model and interface model adopted is suggested.
Abstract: Attempts at classifying geographical information systems (GIS) have typically focused on the task-orientation of particular systems. With the application domain now becoming increasingly ephemeral, there is a need to take a more systematic view of the differences between systems. It is suggested here that a useful perspective to take is one that emphasizes system architecture. Using concepts well established in the wider field of information systems science, we suggest a framework that characterizes a GIS on the three-fold basis of the problem-processor model, database model and interface model adopted.
TL;DR: The hierarchical bus architecture (HBA) supports all levels of vision operations with floating-point coprocessors, sufficient memory, rapid I/O, and software tools.
Abstract: A description is given of the hierarchical bus architecture (HBA), its programming environment, and algorithmic benchmarks. For local neighborhood operations the HBA implements the Apply programming model. Apply enables the vision programmer to write image-to-image transformations without regard to the details of parallelism, looping, of boundary conditions. The HBA supports all levels of vision operations with floating-point coprocessors, sufficient memory, rapid I/O, and software tools. >
23 May 1989
TL;DR: A system architecture has been developed to implement real-time large-vocabulary continuous-speech recognition using HMM (hidden Markov model) algorithms and bigram language models and it is shown that the largest bottleneck in such a system is located in the memory access.
Abstract: A system architecture has been developed to implement real-time large-vocabulary continuous-speech recognition using HMM (hidden Markov model) algorithms and bigram language models. It is shown that the largest bottleneck in such a system is located in the memory access. The architecture exploits a variety of techniques, such as partitioning and replication, to cope with this memory bottleneck. The required throughput is achieved with the aid of extensive pipelining (up to thirteen levels deep) and concurrency. The architecture allows extension to larger vocabularies by the addition of more parallel units. Pin count considerations have resulted in the definition of five custom integrated circuits which are currently being tested. Using the proposed approach, the authors are currently designing and debugging a real-time 3000-word continuous-speech recognition system that uses bigram language models. >
TL;DR: The need for an information architecture to integrate the processes and subsequent software used throughout the life of a building is developed and a knowledge-based approach to implementing the information architecture is propsed.
Abstract: Many computer-aided tools have been developed to assist designers, engineers, and managers with specific well-defined functions, yet they are not well integrated. This paper develops the need for an information architecture to integrate the processes and subsequent software used throughout the life of a building. It then defines a process model of the functions required to provide a facility to the end user, namely, managing, planning, designing, constructing, and operating the facility.
01 Jul 1989
TL;DR: An examination is presented of the performance of the Connection Machine model CM-1 system, a general-purpose computer capable of adapting to many sizes and types of data sets, and indicates howCM-1 performance is enhanced by the use of virtual processors and variable word size.
Abstract: An examination is presented of the performance of the Connection Machine model CM-1 system, a general-purpose computer capable of adapting to many sizes and types of data sets. An overview of the hardware and software systems is provided and a simple application is presented from which the raw performance of the machine is examined. This illustrates the power of data-level parallelism and indicates how CM-1 performance is enhanced by the use of virtual processors and variable word size. The CM-1 system consists of a 64000 processor array, from one to four front-end computers, and high-speed peripherals such as disks and image devices. >
TL;DR: The role of geometry in achieving automation of the overall finite element analysis process is discussed, and the geometry requirements for two of the key technologies within this process: fully automatic mesh generation and adaptive analysis are placed.
Abstract: This paper discusses the role of geometry in achieving automation of the overall finite element analysis process. Emphasis is placed on the geometry requirements for two of the key technologies within this process: fully automatic mesh generation and adaptive analysis. A geometric framework that permits the implementation of automated finite element procedures is presented. This includes high-level geometry-based problem specification and control, powerful data structures, and the geometric functionality that is necessary to support automation. An open architecture system, called TAGUS, which incorporates these notions and permits manipulation of geometry, topology, and attribute data from within an applications program, is also presented. In addition, the paper contrasts the geometry requirements of problems with static domains versus the special considerations that must be given for dynamically changing domains. Finally, a view of an integrated system architecture for analysis automation is presented.
01 Nov 1989
TL;DR: A systolic pipline architecture which can perform exponentiation function in a concurrent environment is presented and is amenable to easy implementation in VLSI.
Abstract: A systolic pipline architecture which can perform exponentiation function in a concurrent environment is presented. This function is computed in Galois fields. Under a steady-state condition the throughput of the architecture is shown to be the maximum, with the results appearing at every clock cycle. Being systolic in nature, the architecture is amenable to easy implementation in VLSI.
TL;DR: A VLSI system architecture for high-speed synthesis of 3D images composed of diffusely reflective surfaces using a multiprocessor Gauss-Seidel iterative system solver and a loosely coupled sub-system.
Abstract: In this paper we describe a VLSI system architecture for high-speed synthesis of 3D images composed of diffusely reflective surfaces. The system consists of two loosely coupled sub-systems. The first sub-system computes the form-factor matrixF. The form-factors are computed by an efficient ray-tracing algorithm. The second sub-system, a multiprocessor Gauss-Seidel iterative system solver, solves the sparse system of radiosity equations(I−ΛF)b=e.