Showing papers on "Systems architecture published in 1991"

Outline for a theory of intelligence

Abstract: Intelligence is defined as that which produces successful behavior. Intelligence is assumed to result from natural selection. A model is proposed that integrates knowledge from research in both natural and artificial systems. The model consists of a hierarchical system architecture wherein: (1) control bandwidth decreases about an order of magnitude at each higher level, (2) perceptual resolution of spatial and temporal patterns contracts about an order-of-magnitude at each higher level, (3) goals expand in scope and planning horizons expand in space and time about an order-of-magnitude at each higher level, and (4) models of the world and memories of events expand their range in space and time by about an order-of-magnitude at each higher level. At each level, functional modules perform behavior generation (task decomposition planning and execution), world modeling, sensory processing, and value judgment. Sensory feedback control loops are closed at every level. >

System architecture for a large scale video on demand service

Abstract: This short paper examines the technological feasibility of a “video on demand” service that is provided from a centralized location over a digital network. The proposed, hypothetical video on demand service is considered to be a service similar to the currently popular video-tape rental services. The problem addressed is divided into two parts: communications and database access. It is argued that the incremental communications cost is small, as long as one assumes that there is already a network with sufficient bandwidth to the customer. A solution to the database access problem is presented which could be implemented with technology available in no more than 10 years.

Sunshine: a high performance self-routing broadband packet switch architecture

Abstract: The authors present a high-performance self-routing packet switch architecture, called Sunshine, that can support a wide range of services having diverse performance objectives and traffic characteristics. Sunshine is based on Batcher-banyan networks and achieves high performance by utilizing both internal and output queuing techniques within a single architecture. This queuing strategy results in an extremely robust and efficient architecture suitable for a wide range of services. An enhanced architecture allowing the bandwidth from an arbitrary set of transmission links to be aggregated into trunk groups to create high bandwidth pipes is also presented. Trunk groups appear as a single logical port on the switch and can be used to increase the efficiency of the switch in an extremely bursty environment or to increase the access bandwidth for selected high-bandwidth terminations. Simulation results are presented. >

An overview of the Arjuna distributed programming system

Abstract: The use of the objects and actions computational model to develop Arjuna is discussed, and its system architecture is described. An overview of Arjuna's implementation is given. An example is provided to show how to construct Arjuna applications. >

Sketch of an IVHS systems architecture

Abstract: The development of a robust, unified systems architecture is an important problem in IVHS technology. This paper presents a sketch of a general architectural framework within which IVHS systems can carry out a wide range of management and control functions. The most important aspect of the work reported here is the definition of two parallel and compatible architectures suitable in the first case for ATMS and ATIS functions, where the driver controls the vehicle, and in the second case for AVCS functions, where the vehicle is under automatic control. The tasks that must be accomplished within either architecture are differentiated across four dimensions: • function - the functions range from stabilizing individual vehicles along nominal trajectories to adapting traffic flows to changing demands; • time scale - the frequency of decisions and responses varies from under 1 s for continuous control of vehicles to several hours for network flow optimization; • spatial scope - the impact of a control action can vary from a single vehicle to the traffic in the entire network; • information span -- satisfactory accomplishment of the task will require information ranging from that referring to a single vehicle to that which spans system-wide flows. The architecture that we outline incorporates a hierarchy of five layers. This hierarchy helps to formulate a structured, modular approach to the development of IVHS because: • The hierarchy satisfactorily resolves all four dimensions of difference in the tasks. • Each layer presents a standard reference model to the layer above it. This provides a, "clean" interface between layers, and the design of each layer can proceed independently using the reference model of the layer below. When standardized, the reference model serve as IVHS open systems architecture. • Communication takes place only between adjacent layers and between peer layers. This will help specify the communication capabilities needed to support the control system. For the ATMS and ATIS functions, in which the driver is in control of the vehicle the tasks are arranged in the following five layers: the physical, regulation, planning, link and network layers. For the most advanced AVCS functions, in which driving tasks are fully automated, the five layers are: physical, vehicle regulation, coordination, link and network. The corresponding layers in the two architectures are functionally similar, although the reference models are significantly different. The functions and the information requirements of the two architectures are sufficiently similar that we strongly urge that future work aimed at successive refinements of either architecture should insist on a graceful transition to the other architecture. In practice, this is most likely to mean that the ATMS and ATIS systems should be designed to accommodate the extensions to the additional features envisaged in a fully automated AVCS system. The modular, hierarchical nature of the architectural framework we have proposed makes it possible to do so from the start, before the AVCS details are fully worked out, and without significant additional cost. The basic motivation for this work is to invite discussion on IVHS architectures from relevant participants including transportation agencies, automobile manufacturers, control and communications equipment developers, and the research community. We have deliberately sketched an idealized portrait of the fully automated AVCS scenario and avoided the important concerns of system evolution in order to sharpen discussion.

Fault-Tolerant Membership Service in a Synchronous Distributed Real-Time System

Abstract: In many hard real-time applications, timely knowledge about the operational state of the nodes in a distributed computer system is of significant importance. This paper presents a fault-tolerant distributed membership protocol for the determination of the set of active nodes in a synchronous distributed real-time system. After a discussion of the system architecture and the fault hypothesis, which is supported by experimental data, the membership protocol is described in detail. In the final section the application of this protocol for the design of selfchecking nodes, for the solution of the atomic multicast problem and for the remote monitoring of nodes is discussed.

Hyperspeech: navigating in speech-only hypermedia

Abstract: Most hypermedia systems emphasize the integration of graphics, images, video, and audio into a traditional hypertext framework. The hyperspeech system described in this paper, a speech-only hypermedia application, explores issues of navigation and system architecture in an audio environment without a visual display. The system under development uses speech recognition to maneuver in a database of digitally recorded speech segments; synthetic speech is used for control information and user feedback. In this research prototype, recorded audio interviews were segmented by topic, and hypertext-style links were added to connect logically related comments and ideas. The software architecture is data driven, with all knowledge embedded in the links and nodes, allowing the software that traverses through the network to be straightforward and concise. Several user interfaces were prototype, emphasizing different styles of speech interaction and feedback between the user and machine. In addition to the issues of navigation in a speech-only database, areas of continuing research includtx dynamically extending the database, use of audio and voice cues to indicate landmarks, and the simultaneous presentation of multiple channels of speech information.

A novel architecture for queue management in the ATM network

Abstract: The author presents four architecture designs for queue management in asynchronous transfer mode (ATM) networks and compares their implementation feasibility and hardware complexity. The author introduces the concept of assigning a departure sequence number to every cell in the queue so that the effect of long-burst traffic on other cells is avoided. A novel architecture to implement the queue management is proposed. It applies the concepts of fully distributed and highly parallel processing to schedule the cells' sending or discarding sequence. To support the architecture, a VLSI chip (called Sequencer), which contains about 150 K CMOS transistors, has been designed in a regular structure such that the queue size and the number of priority levels can grow flexibly. >

A scalable ATM switching system architecture

Abstract: The architecture of an asynchronous transfer mode (ATM) switching system for prototype applications is presented. The general concept to upgrade the existing ISDN switch with an ATM module is introduced, and the building blocks of this ATM module are described in detail. Switching of ATM cells is performed in a single application-specific integrated circuit (ASIC). ASICs can be cascaded to form large switching modules. Peripheral modules interface the ATM switch to external transmission systems and perform all ATM-related functions, including means for redundancy of the switching network. The redundancy scheme tolerates single failures without affecting the user information. A switching network architecture is shown to be capable of fulfilling varying demands in terms of the number of ports for ATM switches and cross connects, concentrators, and multiplexers. >

Integrity S2: a fault-tolerant Unix platform

Abstract: A description is given of Integrity S2, a fault-tolerant, Unix-based computing system designed and implemented to provide a highly available, fault-tolerant computing platform for Unix-based applications. Unlike some other fault tolerant computing systems, no additional coding at the user-level is required to take advantage of the fault-tolerant capabilities inherent in the platform. The hardware is an RISC-based triple-modular-redundant processing core, with duplexed global memory and I/O subsystems. The goals for this machine, the system architecture, its implementation and resulting performance, and the hardware and software techniques incorporated to achieve fault tolerance are discussed. Fault tolerance has been accomplished without compromising the programmatic interface, operating system or system performance. >

Distributed desktop conferencing system with multiuser multimedia interface

Abstract: A distributed multiparty desktop conferencing system (MERMAID) and the architecture on which it is based are described. This architecture, called group collaboration support architecture, is a framework for assisting geographically separate group members to work together at the same time or at different times, efficiently and effectively, by means of computers and electronic communications equipment. The distributed desktop conferencing system provides distributed participants with an environment for holding conferences. This system is implemented by using ISDN (integrated services digital network), widely connected Ethernet, and UNIX-based engineering workstations with electronic writing pads, image scanners, video cameras, microphone-installed loudspeakers, etc. The system provides participants with a means of sharing information in such multimedia forms as video images, voice, text, graphics, still images, and hand-drawn figures. >

Distributed desktop conferencing system (MERMAID) based on group communication architecture

Abstract: A distributed multiparty desktop conferencing system called MERMAID is described. This system allows a group of users, seated at their desks, to conduct a meeting from their personal computers (PC). Participants can jointly view and process multimedia conference documents, including text, graphics, scanned images, and handwritten figures they are sharing, and they can simultaneously interchange voice and video images through ISDN (integrated services digital network) and high speed data network, etc. MERMAID is implemented using OS/2-based PCs with electronic writing pads, image scanners, microphone-installed loudspeakers, video cameras, etc. MERMAID is designed based on the group communication architecture, a framework for supporting group cooperative work in a distributed environment. It consists of two models: a function model, which defines hierarchically structured service functions, and a system model, which provides client-server model-based service interfaces and multimedia communication protocols. >

Datawave: a single-chip multiprocessor for video applications

Abstract: A fine-grained MIMD (multiple-instruction, multiple-data) array processor for video applications that combines submicron technology, parallel processing, and dataflow programming is presented. The Datawave processor is used as the building block of this cellular, data-driven system architecture. The processor executes statically scheduled dataflow programs, and self-timed hardware mechanisms handle the asynchronous dataflows automatically and transparently. The architecture is discussed first at the array level and then at the cell level. It is shown how Datawave implements a four-tap finite impulse response filer and a real-time image codec. Program development tools for Datawave are discussed, and the chip itself is briefly described. >

ESA/390 interpretive-execution architecture, foundation for VM/ESA

Abstract: The interpretive-execution facility of Enterprise Systems Architecture/390™ (ESA/390™) provides an instruction for the execution of virtual machines. This instruction, called START INTERPRETIVE EXECUTION (SIE), was initially created for virtualizing either System/370 or 370-XA architectures, and was used later for virtualizing ESA/370™ and ESA/390 architectures. SIE has evolved to provide capabilities for a number of specialized performance environments. Most recently it provides for the unique requirements of Enterprise Systems Architecture/Extended Configuration (ESA/XC) virtual-machine architecture. This comprehensive set of capabilities in the architecture serves as the platform for the ability of VM/ESA™ to provide functions in virtual machines for end users and system servers. This paper describes the evolution of SIE and outlines use of the various capabilities in VM/ESA.

An object-oriented environment for robot system architectures

Abstract: The object-oriented Robot Independent Programming Environment (RIPE), which is being used for the rapid design and implementation of a variety of applications, is described. A system architecture based on hierarchies of distributed multiprocessors provides the computing platform for a layered programming structure that models the application as a set of software objects. These objects are designed to support model-based automated planning and programming, real-time sensor-based activity, error handling, and robust communication. The object-oriented paradigm provides mechanisms such as inheritance and polymorphism which allow the implementation of the system to satisfy the goals of software reusability, extensibility, reliability, and portability. Designing a hierarchy of generic parent classes and device-specific subclasses which inherit the same interface allows a Robot Independent Programming Language (RIPL) to be realized. Workcell tasks demonstrating robot cask handling operations for nuclear waste facilities, which are successfully implemented using this object-oriented software environment, are discussed. >

The muse object architecture: a new operating system structuring concept

Abstract: A next generation operating system should accommodate an ultra large-scale, open, self-advancing, and distributed environment. This environment is dynamic and versatile in nature. In it, an unlimited number of objects, ranging from fine to coarse-grained, are emerging, vanishing, evolving, and being replaced; computers of various processing capacities are dynamically connected and disconnected to networks; systems can optimize object execution by automatically detecting the user's and/or programmer's requirements. In this paper, we investigate several structuring concepts in existing operating systems. These structuring concepts include layered structuring, hierarchical structuring, policy/mechanism separation, collective kernel structuring, object-based structuring, open operating system structuring, virtual machine structuring, and proxy structuring.We adjudge that these structuring concepts are not sufficient to support the environment described above because they lack the abilities to handle dynamic system behavior and transparency and to control dependency. Thus, we propose a new operating system structuring concept which we call the Muse object architecture. In this architecture, an object is a single abstraction of a computing resource in the system. Each object has a group of meta-objects which provide an execution environment. These meta-objects constitute a meta-space which is represented within the meta-hierarchy. An object is causally connected with its meta-objects: the internal structure of an object is represented by meta-objects; an object can make a request of meta-computing; a meta-object can reflect the results of meta-computing to its object. We discuss object/meta-object separation, the meta-hierarchy, and reflective computing of the architecture. We then compare the Muse object architecture with the existing structuring concepts.We also demonstrate that the Muse object architecture is suitable for structuring future operating systems by presenting several system services of the Muse operating system such as class systems, a real-time scheduler with hierarchical policies, and free-grained objects management. Class systems facilitate programming by several classes of programming languages. A real-time scheduler with hierarchical policies can meet various types of real-time constraints presented by applications. Free-grained objects management can suit the object granularity to the application, so that an object is efficiently managed according to its granularity. Finally, we present the implementation of the Muse operating system which is designed based on the Muse object architecture. Version 0.3 of the Muse kernel is running on the MC68030 based Sony NEWS workstations.

Architecture of fault-tolerant computers: an historical perspective

Abstract: The author surveys the approaches and techniques used to improve system reliability. Over the past 40 years computing systems have experienced over three orders of magnitude improvement in average time to failure and over six orders of magnitude improvement in work accomplished between outages. A three-dimensional design space for comparing fault-tolerant systems is proposed and populated by over two dozen actual systems. A detailed description is provided for a dozen systems evenly distributed throughout the design space. The author concludes by observing trends in the design space and projecting future developments. >

Optimum architecture for input queuing ATM switches

Abstract: An input queueing ATM switch architecture employing the contention resolution called ‘scheduling algorithm’ is described. A high efficiency of over 90% can be achieved without any considerable increase in the amount of hardware or contention control speed.

Smart enabling system for home automation

Abstract: The author describes an enabling system called SMART HOUSE that provides the common resources needed for home automation in a multiproduct, multivendor environment. The system includes the following: a system controller, housewide wiring network, communications protocols, standard interfaces (outlet designs) for connecting other products, and basic user controls such as programmable wall switches and DTMF telephone. Providing complete home automation functionality depends on the addition of other products such as more complex user controls, appliances that include consumer electronics, and application-specific controllers for energy management, security, climate control, etc. These compatible appliances and controllers are equipped with proprietary communications circuits that permit them to communicate with the system controller and with each other. The author provides a concise technical description of the system, concentrating upon the control communications aspects, including system architecture, protocols, messaging, and logic structure. >

Autonomous cross-country navigation: an integrated perception and planning system

Abstract: The development of a software system for obstacle avoidance that controls a vehicle smoothly, continuously, and safely across natural terrain en route to a goal is discussed. The work, carried out as part of the Strategic Computing Initiative of the US Defense Advanced Research Projects Agency (DARPA), was performed on the Autonomous Land Vehicle at Martin Marietta's Denver facilities. The planning software uses digital maps to plan a preferred route, and then, as the vehicle traverses that route, sensors are used to obtain scene descriptions. Techniques necessary to detect and avoid obstacles in cross-country terrain, with minimum delay between sensing and acting, are used. The system architecture, the cross-country perception system, the planning system for obstacle avoidance, the simulation environment, and the experiments are described. Work to develop a fine-grained control architecture, internalized plans, multisensor perception, and color image segmentation is discussed. >

A robotic haptic system architecture

Abstract: The question of what are the necessary elements to integrate a robotics system that would enable it to carry out a task, ie pick-up and transport objects in an unknown environment, is addressed One of the major concerns is to insure adequate data throughput and fast communication between modules within the system, so that haptic tasks can be adequately carried out The communication issues involved in the development of such a system are discussed >

Design and technology aspects of VLSIs for ATM switches

Abstract: A system concept based on a multipath self-routing switching principle and on an internal transfer mode using multislot cells is introduced. With the utilization of a shared buffer memory structure, this concept allows for a single-chip realization of the switching elements and fulfils important system requirements like fault tolerance, independence of the switch core from external data formats and traffic characteristics, and modular extendibility from small to very large systems. An example implementation of the concept with the resulting functional partitioning in boards and chips is given. Performance study results, as a basis for dimensioning, are also presented. The most important design aspects and a possible tool chain exploiting a hardware description language, logic simulator, and logic compiler are highlighted. >

OREGAMI: Tools for mapping parallel computations to parallel architectures

Abstract: The OREGAMI project involves the design, implementation, and testing of algorithms for mapping parallel computations to message-passing parallel architectures. OREGAMI addresses the mapping problem by exploiting regularity and by allowing the user to guide and evaluate mapping decisions made by OREGAMI's efficient combinatorial mapping algorithms. OREGAMI's approach to mapping is based on a new graph theoretic model of parallel computation called the Temporal Communication Graph. The OREGAMI software tools include three components: (1) LaRCS is a graph description language which allows the user to describe regularity in the communication topology as well as the temporal communication behavior (the pattern of message-passing over time). (2) MAPPER is our library of mapping algorithms which utilize information provided by LaRCS to perform contraction, embedding, and routing. (3) METRICS is an interactive graphics tool for display and analysis of mappings. This paper gives an overview of the OREGAMI project, the software tools, and OREGAMI's mapping algorithms.

The coming opportunities in microsensor systems

Abstract: Challenges and opportunities confronting the development of integrated sensing systems in the 1990s are discussed. Silicon microsensors can offer significant advantages over alternative technologies, employing features such as self-testing, autocalibration, digital compensation, and bus-compatibility to improve system reliability and performance while reducing cost. A system architecture which permits all of these features to be implemented is described. Each node in this distributed sensing system is composed of sensors, actuators, and a monolithic microprocessor-driven interface chip and is realized as a multichip module. A discrete prototype of this system achieves 12-b accuracy with the ability to read over 700 sensors per second. All data transfers include parity checking and polynomial-based sensor data compensation in the host computer. Over 300 Mbytes of data have been transferred error-free. Needs for further research in these areas are described, and the application of the prototype system to the measurement of pressure, flow, wafer temperature, and other variables in a reactive ion etching system is discussed. >

Prism-methodology and process-oriented environment

Abstract: The Prism model of engineering processes and an architecture which captures this model in its various components are described. The architecture has been designed to hold a product software process description the life-cycle of which is supported by an explicit representation of a higher-level (or meta) process description. The central part of this paper describes the nine-step Prism methodology for building and tailoring process models and gives several scenarios to support this description. In Prism, process models are built using a hybrid process modeling language that is based on a high-level Petri net formalism and rules. An important observation is that this environment should be seen as an infrastructure for carrying out the more difficult task of creating sound process models. >