Topic
Systems architecture
About: Systems architecture is a research topic. Over the lifetime, 17612 publications have been published within this topic receiving 283719 citations. The topic is also known as: system architecture.
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22 Oct 2006
TL;DR: A systematic analysis of exibility versus cost tradeoffs provided by these mechanisms permits the exibility of selecting the most appropriate level of reconfiguration in embedded sensor networks at multiple levels.
Abstract: In-situ reconfiguration of software is indispensable in embedded networked sensing systems. It is required for re-tasking a deployed network, fixing bugs, introducing new features and tuning the system parameters to the operating environment. We present a system that supports software recon-figuration in embedded sensor networks at multiple levels. The system architecture is based on an operating system consisting of a fixed tiny static kernel and binary modules that can be dynamically inserted, updated or removed. On top of the operating system is a command interpreter, implemented as a dynamically extensible virtual machine, that can execute high-level scripts written in portable byte code. Any binary module dynamically inserted into the operating systems can register custom extensions in the virtual machine interpreter, thus allowing the high-level scripts executed by the virtual machine to efficiently access services exported by a module, such as tuning module parameters. Together these system mechanisms permit the exibility of selecting the most appropriate level of reconfiguration. In addition to detailing the system architecture and the design choices, the paper presents a systematic analysis of exibility versus cost tradeoffs provided by these mechanisms.
86 citations
TL;DR: Results of simulations are given which show the stochastic architecture gives results similar to those found using standard analog neural networks or simulated annealing.
Abstract: A digital architecture which uses stochastic logic for simulating the behavior of Hopfield neural networks is described. This stochastic architecture provides massive parallelism (since stochastic logic is very space-efficient), reprogrammability (since synaptic weights are stored in digital shift registers), large dynamic range (by using either fixed- or floating-point weights), annealing (by coupling variable neuron gains with noise from stochastic arithmetic), high execution speed ( approximately=N*10/sup 8/ connections per second), expandability (by cascading of multiple chips to host large networks), and practicality (by building with very conservative MOS device technologies). Results of simulations are given which show the stochastic architecture gives results similar to those found using standard analog neural networks or simulated annealing. >
86 citations
13 Apr 2010
TL;DR: This paper presents an initial elastic computing framework that transparently optimizes application code onto diverse systems, achieving significant speedups ranging from 1.3x to 46x on a hyper-threaded Xeon system with an FPGA accelerator, a 16-CPU Opteron system, and a quad-core Xeon system.
Abstract: Over the past decade, system architectures have started on a clear trend towards increased parallelism and heterogeneity, often resulting in speedups of 10x to 100x. Despite numerous compiler and high-level synthesis studies, usage of such systems has largely been limited to device experts, due to significantly increased application design complexity. To reduce application design complexity, we introduce elastic computing - a framework that separates functionality from implementation details by enabling designers to use specialized functions, called elastic functions, which enable an optimization framework to explore thousands of possible implementations, even ones using different algorithms. Elastic functions allow designers to execute the same application code efficiently on potentially any architecture and for different runtime parameters such as input size, battery life, etc. In this paper, we present an initial elastic computing framework that transparently optimizes application code onto diverse systems, achieving significant speedups ranging from 1.3x to 46x on a hyper-threaded Xeon system with an FPGA accelerator, a 16-CPU Opteron system, and a quad-core Xeon system.
86 citations
Patent•
19 Aug 2003TL;DR: In this article, the authors present a web-based solution that facilitates online account reconciliation in a central and controlled method across many different divisions and business units, located within in the U.S. or around the world.
Abstract: An architecture and methodology provides a uniform approach for reconciling accounts in a manner that ensures proper controls, both legal and financial, are being met. In the described implementation, the architecture offers a web-based solution that facilitates online account reconciliation in a central and controlled method across many different divisions and business units, located within in the U.S. or around the world. The system architecture enables creation and maintenance of reconciliation profiles that define how different accounts are to be reconciled. The system architecture further supports creation of reconciliation documentations, based on the reconciliation profiles, which are used to reconcile individual accounts.
86 citations
TL;DR: How process automation system architectures have evolved and discusses future trends are reviewed, drawing an analogy between the synergistic new technologies being developed today and the technology landscape of the early 1970s that resulted in the first DCS systems.
86 citations