Topic
Systems architecture
About: Systems architecture is a research topic. Over the lifetime, 17612 publications have been published within this topic receiving 283719 citations. The topic is also known as: system architecture.
Papers published on a yearly basis
Papers
More filters
TL;DR: This paper presents the design of a novel, real-time, wireless, multisensory, smart surveillance system with 3D-HEVC features and measures of the proposed protocol have been shown to provide superior results compared to existing transport protocols.
Abstract: This paper presents the design of a novel, real-time, wireless, multisensory, smart surveillance system with 3D-HEVC features. The proposed high-level system architecture of the surveillance system is analyzed. The advantages of HEVC encoding are presented. Methods for synchronization between multiple streams are presented. Available wireless standards are presented and compared. A network-adaptive transmission protocol for a reliable, real-time, multisensory surveillance system is proposed. Adaptive packet frame grouping (APFG) and adaptive quantization are deployed to maximize the quality-of-experience (QoE). Measurements of the proposed protocol have been shown to provide superior results compared to existing transport protocols.
57 citations
TL;DR: The paper narrates how the lengthy and difficult conceptual work created a foundation of knowledge and experience which in turn produced an “explosion” of numerous prototypes, and tries to elaborate on the effort it takes to convert prototypes into marketable products.
57 citations
TL;DR: This paper describes a Japanese functional model that has been developed, and proposes a document-object-oriented architecture, which is-compared with other existing models.
56 citations
06 Nov 2008
TL;DR: This paper proposes a highly scalable parallelized L7-filter system architecture with affinity-based scheduling on a multi-core server and develops a model to explore the connection level parallelism in L8-filter and proposes an affinity- based scheduler to optimize system scalability.
Abstract: L7-filter is a significant component in Linux's QoS framework that classifies network traffic based on application layer data. It enables subsequent distribution of network resources in respect to the priority of applications. Considerable research has been reported to deploy multi-core architectures for computationally intensive applications. Unfortunately, the proliferation of multi-core architectures has not helped fast packet processing due to: 1) the lack of efficient parallelism in legacy network programs, and 2) the non-trivial configuration for scalable utilization on multi-core servers.In this paper, we propose a highly scalable parallelized L7-filter system architecture with affinity-based scheduling on a multi-core server. We start with an analytical study of the system architecture based on an offline design. Similar to Receive Side Scaling (RSS) in the NIC, we develop a model to explore the connection level parallelism in L7-filter and propose an affinity-based scheduler to optimize system scalability. Performance results show that our optimized L7-filter has superior scalability over the naive multithreaded version. It improves system performance by about 50% when all the cores are deployed.
56 citations
29 Sep 2013
TL;DR: This paper presents on overview of the LegUp design methodology and system architecture, and discusses ongoing work on profiling, hardware/software partitioning, hardware accelerator quality improvements, Pthreads/OpenMP support, visualization tools, and debugging support.
Abstract: Embedded system designers can achieve energy and performance benefits by using dedicated hardware accelerators. However, implementing custom hardware accelerators for an application can be difficult and time intensive. LegUp is an open-source high-level synthesis framework that simplifies the hardware accelerator design process [8]. With LegUp, a designer can start from an embedded application running on a processor and incrementally migrate portions of the program to hardware accelerators implemented on an FPGA. The final application then executes on an automatically-generated software/hardware coprocessor system. This paper presents on overview of the LegUp design methodology and system architecture, and discusses ongoing work on profiling, hardware/software partitioning, hardware accelerator quality improvements, Pthreads/OpenMP support, visualization tools, and debugging support.
56 citations