Topic
Systems architecture
About: Systems architecture is a research topic. Over the lifetime, 17612 publications have been published within this topic receiving 283719 citations. The topic is also known as: system architecture.
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TL;DR: The approach extensively prunes the potentially large configuration space by taking advantage of parameter dependencies and has successfully incorporated into the parameterized SOC tuning environment (Platune) and applied it to a number of applications.
Abstract: In this work, we provide a technique for efficiently exploring the power/performance design space of a parameterized system-on-chip (SOC) architecture to find all Pareto-optimal configurations. These Pareto-optimal configurations will represent the range of power and performance tradeoffs that are obtainable by adjusting parameter values for a fixed application that is mapped on the SOC architecture. Our approach extensively prunes the potentially large configuration space by taking advantage of parameter dependencies. We have successfully applied our technique to explore Pareto-optimal configurations of our SOC architecture for a number of applications.
144 citations
Patent•
HSBC1
TL;DR: In this article, the authors present a computer architecture and/or computer implemented methods for account opening, in which globally standardized, business configurable account opening processes are separate and decoupled from the user interface screens and are directly manageable by business functionality and personnel.
Abstract: The present invention provides, in alternative embodiments, a computer architecture and/or computer implemented methods for account opening. In some embodiments, the invention provides an integrated, component-based technology platform in which globally standardized, business configurable account opening processes are separate and decoupled from the user interface screens and are directly manageable by business functionality and/or personnel. In various embodiments, the invention provides pause and resume, save and retrieve, cross-channel, metrics, audit tracking, data logging, and/or straight-through processing capabilities for account opening.
144 citations
TL;DR: This paper shows how the seemingly intractable problem of visual perception can be converted into a much simpler problem by the application of several physical and biological constraints and argues strongly for the validity of the computational approach to modeling the human visual system.
Abstract: This paper demonstrates how serious consideration of the deep complexity issues inherent in the design of a visual system can constrain the development of a theory of vision. We first show how the seemingly intractable problem of visual perception can be converted into a much simpler problem by the application of several physical and biological constraints. For this transformation, two guiding principles are used that are claimed to be critical in the development of any theory of perception. The first is that analysis at the ‘complexity level’ is necessary to ensure that the basic space and performance constraints observed in human vision are satisfied by a proposed system architecture. Second, the ‘maximum power/minimum cost principle’ ranks the many architectures that satisfy the complexity level and allows the choice of the best one. The best architecture chosen using this principle is completely compatible with the known architecture of the human visual system, and in addition, leads to several predictions. The analysis provides an argument for the computational necessity of attentive visual processes by exposing the computational limits of bottom-up early vision schemes. Further, this argues strongly for the validity of the computational approach to modeling the human visual system. Finally, a new explanation for the pop-out phenomenon so readily observed in visual search experiments, is proposed.
143 citations
IBM1
TL;DR: An overview of the architecture and structure of SP2 is given, the rationale for the significant system design decisions that were made are discussed, the extent to which key objectives were met, and future system challenges and advanced technology development areas are identified.
Abstract: Scalable parallel systems are increasingly being used today to address existing and emerging application areas that require performance levels significantly beyond what symmetric multiprocessors are capable of providing. These areas include traditional technical computing applications, commercial computing applications such as decision support and transaction processing, and emerging areas such as “grand challenge” applications, digital libraries, and video production and distribution. The IBM SP2™ is a general-purpose scalable parallel system designed to address a wide range of these applications. This paper gives an overview of the architecture and structure of SP2, discusses the rationale for the significant system design decisions that were made, indicates the extent to which key objectives were met, and identifies future system challenges and advanced technology development areas.
143 citations
12 Nov 2000
TL;DR: This paper describes the architecture and implementation of the AlphaServer GS320, a cache-coherent non-uniform memory access multiprocessor developed at Compaq and incorporates a couple of innovative techniques that extend previous approaches for efficiently implementing memory consistency models.
Abstract: This paper describes the architecture and implementation of the AlphaServer GS320, a cache-coherent non-uniform memory access multiprocessor developed at Compaq. The AlphaServer GS320 architecture is specifically targeted at medium-scale multiprocessing with 32 to 64 processors. Each node in the design consists of four Alpha 21264 processors, up to 32GB of coherent memory, and an aggressive IO subsystem. The current implementation supports up to 8 such nodes for a total of 32 processors. While snoopy-based designs have been stretched to medium-scale multiprocessors by some vendors, providing sufficient snoop bandwidth remains a major challenge especially in systems with aggressive processors. At the same time, directory protocols targeted at larger scale designs lead to a number of inherent inefficiencies relative to snoopy designs. A key goal of the AlphaServer GS320 architecture has been to achieve the best-of-both-worlds, partly by exploiting the bounded scale of the target systems.This paper focuses on the unique design features used in the AlphaServer GS320 to efficiently implement coherence and consistency. The guiding principle for our directory-based protocol is to address correctness issues related to rare protocol races without burdening the common transaction flows. Our protocol exhibits lower occupancy and lower message counts compared to previous designs, and provides more efficient handling of 3-hop transactions. Furthermore, our design naturally lends itself to elegant solutions for deadlock, livelock, starvation, and fairness. The AlphaServer GS320 architecture also incorporates a couple of innovative techniques that extend previous approaches for efficiently implementing memory consistency models. These techniques allow us to generate commit events (which are used for ordering purposes) well in advance of formulating the reply to a transaction. Furthermore, the separation of the commit event allows time-critical replies to by-pass inbound requests without violating ordering properties. Even though our design specifically targets medium-scale servers, many of the same techniques can be applied to larger-scale directory-based and smaller-scale snoopy-based designs. Finally, we evaluate the performance impact of some of the above optimizations and present a few competitive benchmark results.
143 citations