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Showing papers on "Tantalum capacitor published in 2011"


Patent
27 Apr 2011
TL;DR: In this article, the authors proposed a method for predicting the life of a solid tantalum electrolytic capacitor, which comprises the following steps of: 1, collecting current degradation data; 2, determining a degradation track model and a degradation accelerating model; 3, extrapolating the degradation tracking model to obtain the pseudo-failure life of each sample; 4, performing hypothesis test of pseudo-life distribution and the estimation of unknown parameters; 5, determining the relation of population parameters of the pseudo life distribution and a stress level; 6 estimating the population parameters under the normal stress by extrap
Abstract: The invention relates to a method for predicting the life of a solid tantalum electrolytic capacitor, which comprises the following steps of: 1, collecting current degradation data; 2, determining a degradation track model and a degradation accelerating model; 3, extrapolating the degradation track model to obtain the pseudo-failure life of each sample; 4, performing hypothesis test of pseudo-life distribution and the estimation of unknown parameters; 5, determining the relation of population parameters of the pseudo-life distribution and a stress level; 6 estimating the population parameters of the life distribution of a tantalum capacitor under the normal stress by extrapolating; and 7, determining the average life and reliability curve of the tantalum capacitor. The method has novel concept and simple programs and does not need life tests, the test time can be shorted, the test cost can be saved, and the problem of disharmony between the prediction of the conventional life and engineering is solved, so the method has wide application prospect in the technical field of life prediction.

26 citations


Patent
16 Mar 2011
TL;DR: In this article, high electric energy density polymer film capacitors with high dielectric constant and low dissipation tangent, and low leakage current in a broad temperature range are presented.
Abstract: Examples of the present invention include high electric energy density polymer film capacitors with high dielectric constant, low dielectric dissipation tangent, and low leakage current in a broad temperature range. More particularly, examples include a polymer film capacitor in which the dielectric layer comprise a copolymer of a first monomer (such as tetrafluoroethylene) and a second polar monomer. The second monomer component may be selected from vinylidene fluoride, trifluoroethylene or their mixtures, and optionally other monomers may be included to adjust the mechanical performance. The capacitors can be made by winding metallized films, plain films with metal foils, or hybrid construction where the films comprise the new compositions. The capacitors can be used in DC bus capacitors and energy storage capacitors in pulsed power systems.

21 citations


Proceedings ArticleDOI
19 Jun 2011
TL;DR: In this paper, the authors proposed to increase the lifetime of capacitors by using self-healing capability of metallized film capacitors, which is the main reason for capacitance loss.
Abstract: High energy density capacitor is a key device in power supply source in Electromagnetic Gun (EMG) system. In order to increase the reliability of the power source equipment, the lifetime of capacitors must be lengthened. The increasing of the capacitor's lifetime is mainly beneficial from its self-healing capability. Nevertheless the self-healing is the main reason for the capacitance loss of metallized film capacitors, and it might finally lead to the failure of a capacitor.

20 citations


Patent
31 May 2011
TL;DR: In this paper, a method of fabricating a high-performance capacitor that may be incorporated into a standard CMOS fabrication process suitable for submicron devices is described, particularly for the definition and etch of the lower electrode layer.
Abstract: A method of fabricating a high-performance capacitor that may be incorporated into a standard CMOS fabrication process suitable for submicron devices is described. The parameters used in the standard CMOS process may be maintained, particularly for the definition and etch of the lower electrode layer. To reduce variation in critical dimension width, an Anti-Reflective Layer (ARL) is used, such as a Plasma Enhanced chemical vapor deposition Anti-Reflective Layer (PEARL) or other Anti-Reflective Coatings (ARCS), such as a conductive film like TiN. This ARL formation occurs after the capacitor specific process steps, but prior to the masking used for defining the lower electrodes. A Rapid Thermal Oxidation (RTO) is performed subsequent to removing the unwanted capacitor dielectric layer from the transistor poly outside of the capacitor regions, but prior to the PEARL deposition. Another embodiment instead eliminates the capacitor dielectric removal step, which is then replaced by a step to form an additional layer that is later etched away to leave spacers on the capacitor sides, thereby eliminating any undercutting of the dielectric.

18 citations


Patent
28 Jun 2011
TL;DR: In this article, an integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first andsecond capacitor electrodes, and an electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first, second and third capacitance layers.
Abstract: Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.

18 citations


Patent
01 Jun 2011
TL;DR: In this paper, a hybrid super capacitor using a composite electrode that may enhance equivalent series resistance (ESR) using a carbon nanotube chain is presented, where an anode 11 including an activated carbon layer applied 11 b on the anode oxide layer 11 a; and a cathode 21 being disposed to face the anodes 11.
Abstract: Provided is a hybrid super capacitor using a composite electrode that may enhance equivalent series resistance (ESR) using a carbon nanotube chain. The hybrid super capacitor includes: an anode 11 including an anode oxide layer 11 a and an activated carbon layer applied 11 b on the anode oxide layer 11 a; and a cathode 21 being disposed to face the anode 11. The cathode 21 may include a silicon oxide layer 21 a, a lithium titanium oxide layer 21 b disposed on the silicon oxide layer 21 a, and a carbon nanotube chain CT formed to pass through the silicon oxide layer 21 a and the lithium titanium oxide layer 21 b to thereby be electrically connected to each other, thereby enhancing ESR and expanding an output density and a lifespan of the hybrid super capacitor.

14 citations


Patent
28 Dec 2011
TL;DR: In this paper, a one-time programmable memory (OTP) cell with a gate, a gate dielectric layer, a source region, a drain region, and a capacitance layer and a conductive plug is provided.
Abstract: A one time programmable memory cell having a gate, a gate dielectric layer, a source region, a drain region, a capacitor dielectric layer and a conductive plug is provided herein. The gate dielectric layer is disposed on a substrate. The gate is disposed on the gate dielectric layer. The source region and the drain region are disposed in the substrate at the sides of the gate, respectively. The capacitor dielectric layer is disposed on the source region. The capacitor dielectric layer is a resistive protection oxide layer or a self-aligned silicide block layer. The conductive plug is disposed on the capacitor dielectric layer. The conductive plug is served as a first electrode of a capacitor and the source region is served as a second electrode of the capacitor. The one time programmable memory (OTP) cell is programmed by making the capacitor dielectric layer breakdown.

14 citations


Patent
18 Aug 2011
TL;DR: In this paper, an electrolytic solution for an electric double layer capacitor capable of providing stable quality, and a manufacturing method for the electric double-layer capacitor using the electrolytic solutions were provided.
Abstract: Provided are an electrolytic solution for an electric double layer capacitor capable of providing an electric double layer capacitor having stable quality, an electric double layer capacitor using the electrolytic solution, and a manufacturing method for the electric double layer capacitor. The electrolytic solution includes a supporting electrolyte, sulfolane, and a linear sulfone. It is preferred that the electrolytic solution further include an organic fluorine compound. Further, it is preferred that the supporting electrolyte contain 5-azoniaspiro[4.4]nonane tetrafluoroborate, and the content of 5-azoniaspiro[4.4]nonane tetrafluoroborate be 1.5 to 3.6 mol/dm 3 .

13 citations


Patent
26 May 2011
TL;DR: In this paper, a solid electrolytic capacitor with an anode and a dielectric on the anode is described, where a cathode is electrically connected to the conductive coating by an adhesive selected from the group consisting of a transient liquid phase sinterable material and polymer solder.
Abstract: A solid electrolytic capacitor with an anode and a dielectric on the anode. A cathode is on the dielectric and a conductive coating on said dielectric. A cathode lead is electrically connected to the conductive coating by an adhesive selected from the group consisting of a transient liquid phase sinterable material and polymer solder.

12 citations


Patent
Ueda Masahiro1, Ayao Moriyama1
25 Feb 2011
TL;DR: In this article, a solid electrolytic capacitor is defined as an element having an anode element having a dielectric film formed on a surface thereof and a conductive polymer layer formed on the anodes element, and the cation component contains a cation having two or more ether linkages.
Abstract: A solid electrolytic capacitor includes a solid electrolytic capacitor element having an anode element having a dielectric film formed on a surface thereof and a conductive polymer layer formed on the anode element, an ionic liquid composed of an anion component and a cation component is present in the conductive polymer layer, and the cation component contains a cation having two or more ether linkages.

12 citations


Patent
06 Oct 2011
TL;DR: In this article, a system-on-chip (SOC) device comprises a first capacitor in a first region, a second capacitor in a second region, and any additional number of capacitors in additional regions.
Abstract: A system-on-chip (SOC) device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or different thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, a radio frequency region, a dynamic random access memory region, and so forth.

Patent
Hiroki Hayashi1, Mutsumi Yano1, Yasumi Kobayashi1, Takatani Kazuhiro1, Kazuhito Kikuchi1 
22 Mar 2011
TL;DR: In this paper, the authors describe a method for forming a porous anode body using powder of valve metal or an alloy thereof, and then forming a dielectric layer on the surface of the anode.
Abstract: A method includes the following steps: forming a porous anode body using powder of valve metal or an alloy thereof; forming a dielectric layer on the surface of the anode body; soaking the anode body having the dielectric layer in a liquid containing a conductive-polymer monomer, thereby making the monomer adhere to the dielectric layer of the anode body; forming a first conductive polymer layer by soaking the anode body having the monomer adhered thereto in an oxidizing agent solution, thereby polymerizing the monomer by liquid-phase chemical polymerization; forming a second conductive polymer layer by bringing the conductive-polymer monomer into contact with the surface of the anode body having the first conductive polymer layer in a gas phase, thereby polymerizing the monomer by gas-phase chemical polymerization; and forming a third conductive polymer layer by soaking the anode body having the second conductive polymer layer in a liquid containing a monomer of a conductive polymer layer, thereby polymerizing the monomer by electrolytic polymerization.

Journal ArticleDOI
TL;DR: In this paper, the authors investigated the temperature dependence of leakage current for tantalum oxide metal-insulator-metal capacitors over the temperature range 20-160°C and found that leakage current shows an increase with temperature and the conduction mechanism at medium to high electric fields is in agreement with the modified Poole-Frenkel model.
Abstract: The temperature dependence of leakage current for tantalum oxide metal-insulator-metal capacitors has been investigated over the temperature range 20–160 °C The leakage current shows an increase with temperature and the conduction mechanism at medium to high electric fields is in agreement with the modified Poole–Frenkel model The activation energy of the dominant deep trapping center in the oxide is calculated using this model Constant voltage and constant current stress have been applied to the devices and the effect of stress conditions on leakage current, breakdown voltage, and high frequency capacitance-voltage have been investigated Early oxide breakdown or time-dependent dielectric breakdown was observed during constant voltage and constant current stress, in which the former is a function of stress time and applied voltage or current There is an increase in leakage current with time during the constant voltage stress, presumably due to generation of positive defect states This is also appare

Patent
Ian Pinwill1, David Masheder1, Silvie Vilcova1, Petr Stojan1, Jiri Hurt1, Ivan Horacek1 
31 May 2011
TL;DR: In this paper, a dispersant in the precursor solution is used to reduce the likelihood that the manganese oxide will form droplets upon contacting the surface of the dielectric.
Abstract: A solid electrolytic capacitor that contains an anode body formed from an electrically conductive powder and a dielectric coating located over and/or within the anode body is provided. The present inventors have discovered a technique that is believed to substantially improve the uniformity and consistency of the manganese oxide layer. This is accomplished, in part, through the use of a dispersant in the precursor solution that helps minimize the likelihood that the manganese oxide precursor will form droplets upon contacting the surface of the dielectric. Instead, the precursor solution can be better dispersed so that the resulting manganese oxide has a “film-like” configuration and coats at least a portion of the anode in a substantially uniform manner. This improves the quality of the resulting oxide as well as its surface coverage, and thereby enhances the electrical performance of the capacitor.

Journal ArticleDOI
TL;DR: This paper presents a very simple and cheap off-line technique that is able to evaluate the aluminum electrolytic capacitors condition through the identification of both capacitor internal resistance and capacitance.
Abstract: This paper presents a very simple and cheap off-line technique that is able to evaluate the aluminum electrolytic capacitors condition. Aluminum electrolytic capacitors equivalent circuit is composed by an internal resistance and a capacitance. The capacitors internal resistance increases with aging while the capacitance decreases. Manufacturers define the end of life limit of the capacitor when its internal resistance doubles its initial value or the capacitance changes more than 20% when it is compared with the initial one. The proposed technique evaluates the capacitor condition through the identification of both capacitor internal resistance and capacitance. To compute both capacitor internal resistance and capacitance a very simple, cheap, and practical experimental setup is proposed.

Patent
08 Jun 2011
TL;DR: In this paper, a gate dielectric is preprocessed with oxygen plasma and nitrogen-containing plasma to form a nitrogencontaining oxide layer thereon, and a high-k gate layer is grown on the oxide layer surface by a plasma-enhanced atomic layer deposition process, and then a metal electrode is formed on both an upper and a lower layer of the thus-formed semiconductor construction, so that a MIS capacitor is prepared.
Abstract: The present invention relates to a method of depositing a gate dielectric, a method of preparing a MIS capacitor and the MIS capacitor. In the method of depositing the gate dielectric, a semiconductor substrate surface is preprocessed with oxygen plasma and nitrogen-containing plasma to form a nitrogen-containing oxide layer thereon. Then, a high-k gate dielectric layer is grown on the nitrogen-containing oxide layer surface by a plasma-enhanced atomic layer deposition process, and the oxide layer converts during the gate dielectric layer growth process into a buffer layer of a dielectric constant higher than SiO2. Then, a metal electrode is formed on both an upper layer and a lower layer of the thus-formed semiconductor construction, so that a MIS capacitor is prepared. According to the present invention, the formation of the buffer layer enables the interface characteristics between semiconductor materials and high-k gate dielectric layers to be improved effectively, equivalent oxide thickness (EOT) to be reduced and electrical properties to be enhanced.

Patent
Yousuke Abe1, Atsushi Furuzawa1
10 Nov 2011
TL;DR: In this paper, a solid electrolytic capacitor with an anode element, a dielectric film covering a surface of the anode elements, a conductive polymer layer provided on the dielectrics film, and a water-repellent portion not in contact with the conductive polymers and containing silicone oil is provided.
Abstract: A solid electrolytic capacitor having an anode element, a dielectric film covering a surface of the anode element, a conductive polymer layer provided on the dielectric film, and a water-repellent portion provided on the dielectric film not in contact with the conductive polymer layer and containing silicone oil is provided.

28 Mar 2011
TL;DR: In this paper, a surge step stress test (SSST) was applied to identify the critical stress level of a capacitor batch to give some predictability to the power-on failure mechanism.
Abstract: Power-on failure has been the prevalent failure mechanism for solid tantalum capacitors in decoupling applications. A surge step stress test (SSST) has been previously applied to identify the critical stress level of a capacitor batch to give some predictability to the power-on failure mechanism [1]. But SSST can also be viewed as an electrically destructive test under a time-varying stress (voltage). It consists of rapidly charging the capacitor with incremental voltage increases, through a low resistance in series, until the capacitor under test is electrically shorted. When the reliability of capacitors is evaluated, a highly accelerated life test (HALT) is usually adopted since it is a time-efficient method of determining the failure mechanism; however, a destructive test under a time-varying stress such as SSST is even more time efficient. It usually takes days or weeks to complete a HALT test, but it only takes minutes for a time-varying stress test to produce failures. The advantage of incorporating a specific time-varying stress profile into a statistical model is significant in providing an alternative life test method for quickly revealing the failure mechanism in capacitors. In this paper, a time-varying stress that mimics a typical SSST has been incorporated into the Weibull model to characterize the failure mechanism in different types of capacitors. The SSST circuit and transient conditions for correctly surge testing capacitors are discussed. Finally, the SSST was applied for testing Ta capacitors, polymer aluminum capacitors (PA capacitors), and multi-layer ceramic (MLC) capacitors with both precious metal electrodes (PME) and base metal electrodes (BME). The test results are found to be directly associated with the dielectric layer breakdown in Ta and PA capacitors and are independent of the capacitor values, the way the capacitors were built, and the capacitors manufacturers. The test results also show that MLC capacitors exhibit surge breakdown voltages much higher than the rated voltage and that the breakdown field is inversely proportional to the dielectric layer thickness. The SSST data can also be used to comparatively evaluate the voltage robustness of capacitors for decoupling applications.

Patent
23 Feb 2011
TL;DR: A multi-layer capacitor includes a first capacitor layer and a second capacitor layer adjacent and substantially parallel to the first layer as discussed by the authors, and the second layer has a surface area that is less than the surface area of the first capacitance layer.
Abstract: A multi-layer capacitor includes a first capacitor layer and a second capacitor layer adjacent and substantially parallel to the first capacitor layer The second capacitor layer has a surface area that is less than the surface area of the first capacitor layer

Proceedings ArticleDOI
01 Aug 2011
TL;DR: In this article, the first proof-of-concept demonstration of a novel silicon-compatible high-density capacitor technology was reported, where the key novelty stems from the tremendous enhancement in surface area from porous copper nanoelectrodes and conformal alumina dielectric.
Abstract: Achieving high capacitance densities with capacitors integrated in thin film form has been a major challenge for the past few decades. Nanocapacitors utilizing nanostructured electrodes and conformal nanodielectrics provide unique opportunities to enhance capacitance volumetric efficiency by 5–10X compared to the state-of-the-art tantalum capacitors. This paper reports the first proof-of-concept demonstration of a novel silicon-compatible high-density capacitor technology. The key novelty stems from the tremendous enhancement in surface area from porous copper nanoelectrodes and conformal alumina dielectric on such nanoelectrodes. Alternative organic package compatible high-density capacitors using etched foils is also presented. Both approaches show substantial improvements in capacitance densities compared to traditional integrated thin film or trench capacitors.

Patent
Masahiro Ueda1
25 Feb 2011
TL;DR: In this article, a method of manufacturing a solid electrolytic capacitor includes the steps of forming a dielectric film on a surface of an anode element, forming a first conductive polymer layer on the dielectrics film, impregnating the anodes element having the first conductives polymer layer formed with an ion liquid, and forming a second conductives polymers on the first polymers after impregnation with the ion liquid.
Abstract: A method of manufacturing a solid electrolytic capacitor includes the steps of forming a dielectric film on a surface of an anode element, forming a first conductive polymer layer on the dielectric film, impregnating the anode element having the first conductive polymer layer formed with an ion liquid, and forming a second conductive polymer layer on the first conductive polymer layer after impregnation with the ion liquid.

Patent
07 Feb 2011
TL;DR: In this paper, a polymer of a polymerized monomer, including a thiophene derivative represented by an ethylene dioxythiophene derivatives having an alkyl substituent group and an alkoxy group is formed on a valve action metal having a dielectric oxide film as a solid-state electrolytic layer.
Abstract: PROBLEM TO BE SOLVED: To provide a superior solid-state electrolytic capacitor which is superior in an electric characteristic of capacity, an equivalent series resistance, and the like, and has small leakage current and high withstand voltage; and a manufacturing method of the capacitor.SOLUTION: In the solid-state electrolytic capacitor, a polymer of a polymerized monomer including a thiophene derivative represented by an ethylene dioxythiophene derivative having an alkyl substituent group and a thiophene derivative whose third and fourth orders are substituted by an alkoxy group is formed on a valve action metal having a dielectric oxide film as a solid-state electrolytic layer. It is desirable to form the polymerized monomer by chemical oxidative polymerization in the manufacturing method of the solid-state electrolytic capacitor.

Patent
01 Nov 2011
TL;DR: In this paper, a gate dielectric overlying an N-doped silicon substrate and a sub-monolayer of tantalum oxide is deposited overlying the gate by a process of atomic layer deposition.
Abstract: Methods are provided for fabricating integrated circuits having controlled threshold voltages. In accordance with one embodiment a method includes forming a gate dielectric overlying an N-doped silicon substrate and depositing a layer of titanium nitride and a layer of tantalum nitride overlying the gate dielectric. A sub-monolayer of tantalum oxide is deposited overlying the layer of tantalum nitride by a process of atomic layer deposition, and oxygen is diffused from the tantalum oxide through the tantalum nitride and titanium nitride.

Patent
15 Jun 2011
TL;DR: In this article, the authors provided a silver paste for gluing a tantalum capacitor, which consisted of the following components according to weight percentage: 60-80 percent of silver powder; 5-18 percent of epoxy resin; 4-15 percent of solidifying agent; 0.1-2 percent of accelerant;0.5-3 percent of anti-settling agent; and 2-10 percent of solvent.
Abstract: The invention provides a silver paste for gluing a tantalum capacitor, which comprises the following components according to weight percentage: 60-80 percent of silver powder; 5-18 percent of epoxy resin; 4-15 percent of solidifying agent; 0.1-2 percent of accelerant; 0.5-3 percent of anti-settling agent; and 2-10 percent of solvent. The invention also provides a preparation method of the tantalumcapacitor as follows: 1) the epoxy resin, the solidifying agent, the accelerant, the anti-settling agent, the dissolvent and the silver powder are mixed according to proportion; and 2) the evenly mixed silver paste is rolled. The gluing silver paste provided by the invention has good dispersiveness and anti-settling performance as well as good electric conductivity and high gluing strength. Testresults show that the silver paste provided by the invention has the gluing strength of more than or equal to 3MP and good overall performance, and can meet the current requirements for highly automatic production of the tantalum capacitor.

Patent
05 Jan 2011
TL;DR: In this article, a rotatable hanging electrode is used as an anode to reduce the amount of the cathode material, thus being capable of reducing volume of the capacitor, improving volume energy density and facilitating the miniaturization of a high energy capacitor to be possible.
Abstract: The invention provides a method for preparing RuO2 film in internal wall of tantalum shell applied to a tantalum capacitor, comprising the following steps: 1) tantalum shell preprocessing: grinding, polishing and cleaning the tantalum shell for standby; 2) preparation of a rotatable hanging electrode: using a hollow graphite electrode as the anode, arranging a plurality of through holes on the wall of the hollow graphite electrode; 3) electrodeposit technique: taking the acid aqueous solution of colloid ruthenium chloride as electrodeposit liquid, taking the hollow graphite electrode and tantalum shell as anode and the cathode respectively and putting both into the electrodeposit liquid and depositing RuO2 film in the tantalum shell; 4) heat treatment of the film. The RuO2 film prepared bythe method of the invention can be used as the cathode material of the capacitor to reduce the amount of the cathode material, thus being capable of reducing volume of the capacitor, improving volumeenergy density of the capacitor and facilitating the miniaturization of a high-energy capacitor to be possible.

Patent
05 May 2011
TL;DR: In this article, a solid electrolytic capacitor with high capacitance and low ESR has been described, and a method for producing the same has been presented, where the molecule described in [1] is formed on a valve-action metal on which a dielectric oxide film has been formed.
Abstract: Disclosed is a solid electrolytic capacitor having heat-resistance and electrical properties that are more excellent and that has a high capacitance and a low ESR. Further disclosed is a method for producing same. [1] The solid electrolytic capacitor is a thiophene derivative having a heteroatom-containing cyclic substituent group and is characterized by containing as a solid electrolyte the molecule obtained by polymerizing a compound having an alkyl substituent group on the heteroatom-containing cyclic substituent group. [2] The method for producing the solid electrolytic capacitor has a step wherein the molecule described in [1] mentioned above is formed on a valve-action metal on which a dielectric oxide film has been formed.

Patent
24 Mar 2011
TL;DR: In this article, a technology for recovering high-content tantalum from tantalum-containing waste with reducing various impurities such as antimony (Sb) and phosphorus (P) which hinder reuse of the tantalum in tantalum capacitors is presented.
Abstract: The present invention provides a technology for recovering high-content tantalum from tantalum-containing waste with reducing various impurities such as antimony (Sb) and phosphorus (P) which hinder reuse of the tantalum in tantalum capacitors. The method for recovering tantalum from tantalum-containing waste according to the present invention is characterized in that tantalum-containing waste is subjected to an acid treatment and then to an alkali treatment, thereby recovering tantalum. The acid treatment is preferably performed with use of an acid containing hydrochloric acid and the alkali treatment is preferably performed with use of sodium hydroxide or potassium hydroxide. The tantalum-containing waste in the present invention is preferably a tantalum sintered compact collected from a tantalum capacitor.

Journal ArticleDOI
TL;DR: In this article, the authors modify two standard accelerated tests, the steadystate temperature humidity bias life test (the 85/85 test) and the temperature cycling test, for use in testing tantalum capacitors more efficiently.
Abstract: Purpose – Accelerated tests are commonly used to evaluate the reliability of electronic components and to detect failures caused by environmental conditions in field use. Many standard accelerated tests are available for evaluating the reliability in a commonly approved way. These tests form a good basis for reliability testing. However, sometimes standard accelerated tests may not be directly used to test the reliability of a certain component. Rather, such tests should be modified for each component, based on the component's structure and field use. The purpose of this paper was to modify two Joint Electron Device Engineering Council (JEDEC) standard accelerated tests: the steady‐state temperature humidity‐bias life test (the 85/85 test) and the temperature cycling test, for use in testing tantalum capacitors more efficiently.Design/methodology/approach – The 85/85 test was first modified by adding a ripple voltage and then by adding a voltage off‐period. The temperature cycling test was modified by usi...

Journal ArticleDOI
TL;DR: In this paper, the effects of seacoast atmosphere on tantalum capacitors were tested using salt spray, temperature cycling, and a 100% RH humidity test, and the results showed that combination of high humidity and high temperature did not possess significant risk for these capacitors during their normal use.
Abstract: The goal of this research was to test the effects of seacoast atmosphere on tantalum capacitors. Four tests were chosen for this purpose: the 85/85 test was chosen for testing the effects of the combination of high humidity and high temperature, salt spray testing was done for examining the effects of high humidity and salt, temperature cycling test was applied for testing the effects of temperature changes, and a 100% RH humidity test was developed for examining the effects of very high humidity. The results show that combination of high humidity and high temperature did not possess a significant risk for these capacitors during their normal use. Very high humidity and radical temperature changes both affected the breakdown voltages of tantalum capacitors. Salt fog caused corrosion of these components and had a small effect on breakdown voltage but did not have an effect on capacitance or ESR.

Patent
20 Apr 2011
TL;DR: In this article, a non-polarity chip tantalum capacitor and a preparation method are presented, where the capacitor comprises two tantalum structures which are arranged in an encapsulation shell, each tantalum structure is provided with an anode and a cathode.
Abstract: The invention discloses a non-polarity chip tantalum capacitor and a preparation method thereof, wherein, the capacitor comprises two tantalum capacitor structures which are arranged in an encapsulation shell; each tantalum capacitor structure is provided with an anode and a cathode; the cathodes of the two tantalum capacitors are electrically connected and two anodes thereof are encapsulated as the tantalum capacitor and lead out two non-polarity electrodes; the tantalum capacitor forms the chip tantalum capacitor without polarity as all cathodes of two tantalum capacitor structures are electrically connected; the tantalum capacitor has simple structure and convenient manufacture process, and can sufficiently utilize most of the existing preparation processes; the prepared non-polarity tantalum capacitor can meet the requirement of various circuits, thus greatly extending the application of the tantalum capacitor.