Tantalum capacitor

About: Tantalum capacitor is a research topic. Over the lifetime, 2432 publications have been published within this topic receiving 26709 citations.

Process for manufacturing a solid state electrolytic capacitor

Abstract: A process for manufacturing a solid state electrolytic capacitor having on an anode (1) a dielectric coating layer (3) and a solid state electrolytic layer (4), comprises the steps of forming a conductive polymer compound layer (4) as the solid state electrolytic layer, and subsequently forming the dielectric coating layer (3) by anodizing.

Metallized Paper for Capacitors

Abstract: Metallized capacitor paper is attracting widespread interest as a way of reducing capacitor size. In metallized paper capacitors, the usual metal foil is replaced by a thin layer of metal evaporated onto the surface of the paper. Lacquering the paper prior to metallizing increases the dielectric strength and insulation resistance, reduces atmospheric corrosion of the metal, and diminishes the rate of loss of electrode metal by electrolysis. Owing to the extreme thinness of the metal layer, metallized paper capacitors are subject to a type of failure not ordinarily found in conventional capacitors. This type of failure consists of the loss of electrode by electrolysis and occurs under dc potential when the ionic conductivity is high, as results, for example, from the presence of moisture. For this reason, it is recommended that special precautions be taken to keep the ionic conductivity low, in particular with respect to thorough and effective drying and sealing of the capacitor units.

High voltage, high temperature capacitor and interconnection structures

Abstract: Capacitors and interconnection structures for silicon carbide are provided having an oxide layer, a layer of dielectric material and a second oxide layer on the layer of dielectric material. The thickness of the oxide layers may be from about 0.5 to about 33 percent of the thickness of the oxide layers and the layer of dielectric material. Capacitors and interconnection structures for silicon carbide having silicon oxynitride layer as a dielectric structure are also provided. Such a dielectric structure may be between metal layers to provide a metal-insulator-metal capacitor or may be used as a inter-metal dielectric of an interconnect structure so as to provide devices and structures having improved mean time to failure. Methods of fabricating such capacitors and structures are also provided.

Solid electrolytic capacitor and method for producing same

Abstract: A solid electrolytic capacitor that is able to maintain a high capacitance and low ESR, and also exhibits a high degree of heat resistance. The solid electrolytic capacitor 10 is produced by winding a porous anode foil 11 having a dielectric layer formed thereon, and a cathode foil 13 b, with a separator having a solid electrolyte 13 a supported thereon disposed therebetween, wherein the solid electrolyte 13 a comprises at least a conductive complex having a cationized conductive polymer and a polymer anion, and not more than 7% by mass of water.

Capacitor and Method for Making Same

Abstract: A system-on-chip (SOC) device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or different thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, a radio frequency region, a dynamic random access memory region, and so forth.