Tantalum capacitor

About: Tantalum capacitor is a research topic. Over the lifetime, 2432 publications have been published within this topic receiving 26709 citations.

Production method of solid electrolytic capacitor

Abstract: The present invention relates to a method for producing a niobium-oxide solid electrolytic capacitor having an anode being at least one member selected from niobium monoxide, niobium and an alloy mainly comprising niobium, or a mixture of niobium monoxide with niobium or an alloy mainly comprising niobium, which capacitor formed by the electrolytic oxidation (electrochemical formation) of the anode; and the method including sequentially repeating twice or more a step of exposing a dielectric layer to a temperature to 1,000° C. before formation of a cathode and a step of re-electrochemically forming the dielectric layer. The niobium solid electrolytic capacitor obtained by the present invention improved in the leakage current value after mounting and excellent in reliability.

Capacitor element and carbon paste

Abstract: The present invention provides a capacitor wherein increase in the ESR value after a high temperature loading test is mitigated. A capacitor element, comprising an electric conductor having formed on the surface thereof a dielectric layer as one electrode, and a semiconductor layer, carbon layer and electrode layer formed sequentially on the dielectric layer, which capacitor element is characterized in that the carbon layer contains a dopant; a carbon paste as a material of the capacitor element; a capacitor using the capacitor element; and an electronic circuit and an electronic device using the capacitor.

Dielectric ceramics, multilayer ceramic capacitor and method for manufacturing the same

Abstract: Crystal grains mainly composed of barium titanate have a mean grain size of not more than 0.2 μm. The volume per unit cell V that is represented by a product of lattice constant (a, b, c) figured out from the X-ray diffraction pattern of the crystal grains is not more than 0.0643 nm 3 . Thereby, a dielectric ceramics having high relative dielectric constant can be obtained. A multilayer ceramic capacitor comprises a capacitor body and an external electrode that is formed at both ends of the capacitor body. The capacitor body comprises dielectric layers composed of the dielectric ceramics, and internal electrode layers. The dielectric layers and the internal electrode layers are alternately laminated.

Monolithic, buried-substrate, ceramic multiple capacitors isolated, one to the next, by dual-dielectric-constant, three-layer-laminate isolation layers

Abstract: A monolithic, buried-substrate, ceramic multiple capacitor is laid up as multiple capacitors that are isolated, one to the next, by a dual-dielectric-constant, three-layer-laminate, isolation layer. Each isolation layer has and presents (i) an innermost layer of a low dielectric constant (low K) material, located between (ii) outer laminate layers of a high dielectric constant (high K) material. By such construction negative effects of the physio-chemical reaction (i) occurring at the boundary between the high-K and low-K layers, (ii) contaminating the high-K dielectric and lowering its K, and (iii) undesirably serving both to lower the capacitance of any (buried substrate) capacitor that makes use of the ("contaminated") high-K dielectric while increasing capacitor leakage current, are mitigated or avoided. This occurs because the physio-chemical reaction zone, or band, located between the high-K dielectric layers (from which each buried-substrate capacitor is formed) and the low-K dielectric isolation layer (between successive capacitors) is moved slightly away from the region of the capacitor itself. Moreover, the ceramic multiple capacitor is strongly and stably fused together in its several layers, which different layers of different dielectric constant have different thermal coefficients of expansion, because the outer (high-K) laminate layers of the isolation layer are preferably of intermediary thickness between the innermost (low-K) layer and the (high-K) dielectric layers of the bordering buried-substrate capacitors.

High linearity variable capacitor array

Abstract: A highly linear, variable capacitor array (400) constructed from multiple cells (100-0, 100_ 1,... 100_ N). Each cell includes a pair of passive, two-terminal capacitor components connected in antiparallel. The capacitor components may be Metal Oxide Semicondutor, MOS, capacitors. A control circuit (410) applies bias voltages (411_0, 411 1,... 411_ N) to bias voltage terminals associated with each capacitor component, to thereby control the overall capacitance of the array. The two capacitors in each cell are connected in anti-parallel to reduce the cell's and the array's voltage coefficient of capacitance. MOS capacitors are preferably operated in inversion or accumulation mode.