Showing papers on "Task (computing) published in 1978"

Rule-Directed Interactive Transaction Agents: An Approach to Knowledge Acquisition.

Abstract: : A description of computer programs, called user agents, that can perform various tasks for the user. Interacting with users, these agents can learn facts and store them in a data base or learn data-manipulation procedures and represent them as programs. The agents are written in RITA, the Rule- directed Interactive Transaction Agent system, and are organized as sets of IF- THEN rules. Four types of RITA agents are described: (1) an exemplary programming agent that 'watches' a user perform a task, then writes a program to perform the same task; (2) a self-modifying agent that performs file transfer tasks, modifying itself to perform them with less help each time; (3) a tutoring agent that watches demonstrations of interactive computer languages or local operating systems, then creates teaching agents for assisting new users; (4) a reactive-message creating agent that elicits text to create a reactive message, which is then sent to a recipient who interacts with it, automatically returning a response to the sender.

The LASS hardware processor

Abstract: The problems of data analysis with hardware processors are reviewed and a description is given for a programmable processor. This processor, the 168/E, has been designed for use in the LASS multi-processor system; it has an execution speed comparable to that of the IBM 370/168 and uses the subset of IBM 370 instructions appropriate to the LASS analysis task.

Time-Sharing Ability in Complex Performance. An Expanded Replication,

Abstract: Factor analyses were performed on data from 51 subjects tested on the CAMI Multiple Task Performance Battery (MTPB). Five different complex performance task combinations were used as well as the six individual MTPB tasks performed by themselves. The primary treatment of the data involved factor analyses of the tasks of the five different complex tasks along with appropriate measures of the tasks performed singly. The results were interpreted to support the hypothesized existence of a time-sharing ability. Orthogonal factors were found on which the monitoring tasks, in general, loaded during simple performance; the monitoring tasks loaded on separate orthogonal factors when they were performed as a part of a complex task. Potential relevance of these findings to aviation selection and performance research programs is noted. (Author)

A Scheduler for Real-Time Task Control in Microcomputers

Abstract: A special-purpose task scheduler is described which is suitable for many dedicated, real-time minicomputer and microcomputer applications. The scheduling algorithm is presented in detail. A brief discussion of a basic interrupt-driven real-time executive (RTE) is also included. Its memory size is estimated at about 1 kbyte, using the Intel 8080 instruction set.

Multiple computer system

Abstract: PURPOSE: To obtain a multiple computer system which is eaily made into modules, by eliminating the relation of subordination among computers and also discontinuance of the system due to the breakdown of a certain computer, by providing a processing routine with a fixed function CONSTITUTION: Computers COMP 1 , COMP 2 COMP n consists of arithmetic controllers CPU 1 , CPU 2 CPU n and main memory units MEM 1 , MEM 2 MEM n bus- connected to them, and those are enabled to transmit and receive signals to and from auxiliary memory unit AUXMEM and common memory unit MEMC This AUXMEM is stored with all user's tasks to be executed by this multiple computer, and MEMC with the queue of a part of user's tasks that the system executes and uer's task registration talbes corresponding to CPU 1 , CPU 2 CPU n In the multiple computer system like this, the operation systems of respective computers are made identical and equipped with a processing routine where the signal of a computer breaking down is detected COPYRIGHT: (C)1980,JPO&Japio

Reconfiguration stategies for the SIFT fault-tolerant computer

Abstract: We describe methods for achieving an acceptable level of fault-tolerance in a multiprocessor designed for the execution of critical flight tasks on commercial aircraft. The SIFT (Software Implemented Fault-tolerant) system differs from other reliable computer architectures in the manner of utilization of redundant resources. The SIFT system is designed to cope with hardware faults by detecting discrepancies in the results computed by separately executed versions of critical programs. When such a discrepancy occurs we identify the processor/memory unit, bus unit, or processor/bus interface that has failed. A reconfiguration of task execution among the available resources is carried out to avoid the use of hardware units that have been identified as faulty or unreliable. We explain how the identification of faulty units can be effected, how the system may be reconfigured to avoid use of faulty units, and show that these reconfiguration policies are "safe" with respect to faults that do not occur in separated units during the short interval required to carry out the reconfiguration of tasks.

LASS hardware processor

Abstract: The problems of data analysis with hardware processors are reviewed, and a description is given for a programmable processor. This processor, the 168/E, was designed for use in the LASS multi-processor system; it has an execution speed comparable to that of the IBM 370/168 and uses the subset of IBM 370 instructions appropriate to the LASS analysis task. 2 figures, 2 tables.