Showing papers on "Task (computing) published in 1983"

MASSIVELY PARALLEL ARCHITECTURES FOR Al: METL, THISTLE, AND BOLTZMANN MACHINES

Abstract: It is becoming increasingly apparent that some aspects of intelligent behavior rcquirc enormous computational power and that some sort of massively parallel computing architecture is the most plausible way to deliver such power. Parallelism, rather than raw speed of the computing elements. seems to be the way that the brain gets such jobs done. But even if the need for massive parallelism is admitted, there is still the question of what kind of parallel architecture best fits the needs of various AI tasks. In this paper we will attempt to isolate a number of basic computational tasks that an intelligent system must perform. We will describe several families of massively parallel computing architectures, and we will see which of these computational tasks can be handled by each of these families. In particular, we will describe a new architecture, which we call the Boltzmann machine, whose abilities appear to include a number of tasks that are inefficient or impossible on the other architectures. FAMILIES OF PARALLEL ARCHITECTURES By “massively parallel” architectures, we mean machines with a very large number of processing elements (perhaps very simple ones) working on a single task. A massively parallel system may be complete and self-contained or it may be a special-purpose device, performing some particular task as part of a larger system that contains other modules of a different character. In this paper we will focus on the computation performed by a single parallel module, ignoring the issue of how to integrate a collection of modules into a complete system. * Scott Fahlman i* 3 supported by the Defense Advanced Research Projects Agency, Department of Defense, ARPA Order 3597, monitored by the Air Force Avionics Laboratory under contract F3361581-K-1539. The other two authors are supported by grants from the System Development Foundation. The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressed or implied, of the Defense Advanced Research Projects Agency or the U.S. Government. One useful way of classifying these massively parallel architectures is by the type of signal that is passed among the clcmcnts. Fahlman (1982) proposes a division of thcsc systems into three classes: markerpassing, valuc-passing, and message-passing systems. Message-passing systems are the most powerful family, and by far the most complex. They pass around mcssagcs of arbitrary complexity, and perform complex operations on these messages. Such generality has its price: the individual computing clcmcnts are complex, the communication costs are high, and there may be severe contention and traffic congestion problems in the network. Message passing dots not seem plausible as a detailed model of processing in the brain. Such models are being actively studied elsewhere (Hillis, 1981; Hewitt, 1980) and we have nothing more to say about them here. Marker-passing systems, of which NETL (Fahlman, 1979) is an example, arc the simplest family and the most limited. In such systems, the communication among processing elements is in the form of single-bit markers. Each “node” element has the capacity to store a few distinct marker bits (typically 16) and to perform simple Boolean operations on the stored bits and on marker bits arriving from other elements. These nodes are connected by hardware “links” that pass markers from node to node, under orders from an external control computer. The links arc, in effect, dedicated private lines, so a lot of marker traffic can proceed in parallel. A node may be connected to any number of links, and it is the pattern of node-link connections that forms the system’s long-term memory. In NETL, the elements are wired up to form the nodes and links of a semantic network that represents some body of knowledge. Certain common but computation-intensive searches and deductions arc accomplished by passing markers from node to node through the links of this network. A key point about marker-passing systems is that there is never any contention due to message traffic. If many copies of the same marker arrive at a node at once, they are simply OR’ed together. Value-passing systems pass around continuous quantities or numbers and perform simple arithmetic operations on these values. From: AAAI-83 Proceedings. Copyright ©1983, AAAI (www.aaai.org). All rights reserved.

Multiple task oriented processor

Abstract: The computer system for missile guidance comprises five parallel processors interconnected by a global bus; with each processor having its own CPU, program memory, temporary memory, and two critical variable memories, interconnected by a local bus. The program memory and critical variable memory are hard MNOS to survive nuclear radiation. Each processor has its own cycle time, synchronized by a master clock. In each processor, the cycle has three phases for intercommunication, task processing, and critical variable storage. Thus the critical variables are stored only after task processing is completed.

Self-configuring computerized robot control system

Abstract: Apparatus constructed such that it may control various other equipment for the performance of various work tasks, even other equipment yet to be designed for work tasks yet to be designed. The apparatus comprises a central computer control means comprising (1) a dictionary storage means for tagging and storing command-specific parameters for a specific work tasks and that specific robot module to which each of the parameters belongs and (2) sequencing means to schedule said work-tasks for a plurality of said modules. The module also can be activated for the task without use of the sequencing means, e.g. by having the module request one of its own dictionary entries.

Computer hardware executive

Abstract: The computer hardware executive is a special purpose associative processorhich interfaces to the memory bus of a digital computer to provide high-speed execution of executive functions. These functions include task registration, task synchronization, normal, time-dependent and time-critical event registration and triggering, hierarchical event-to-semaphore translation, and buffer allocation. The programmer invokes an executive function by accessing the address in the hose computer address space dedicated to that function. The data written to or read from that address is the function operated or result, respectively. The hardware executive maintains task and event tables internally within its associative memory. The memory is organized such that the same field bit position of all table entries is accessed in parallel within a microinstruction cycle. Searches are performed by sequencing through the bit positions of interest. The computer hardware executive also contains an internal clock for comparison against time-dependent and time-critical event registrations. The executive function algorithms are executed by an internal microprogram.

Method and apparatus for preventing overloading of the central controller of a telecommunication system

Abstract: In telecommunication systems in which tasks are performed collectively and centralized by the processor of the central controller, the problem is encountered that this central control may be overloaded. The method in accordance with the invention has for its object to prevent this by rapidly detecting an imminent overload. The number of tasks (for example calls) being processed and the number of idle jobs which were performed are taken as a measure of the load. On the basis of the continuously actualized value of the maximum number of tasks which can be handled it is determined at each new task (for example a call from a subscriber) whether the maximum calls in the process of being set-up determined for that period is not exceeded.

Threads of Identity in Maxine Hong Kingston's Woman Warrior

Abstract: As an autobiographer, Kingston has an even more difficult task than the knot-maker: before tying the string into a button, this book of her self, she must untangle the threads of her identity; there is no Gordian short-cut. It is a perilous and difficult process. She must first defy the authority of the emperor, here exercised humanely, to pursue what seems an arbitrary artistic task. She may lose her sight in sorting out the mass of threads of a self created "in an interface between two cul tures."2 How does a Chinese-American woman "separate what is pecu liar to childhood, to poverty, insanities, one family, your mother who marked your growing with stories, from what is Chinese?" (page 6). Her task is harder than the knot-maker's in another sense as well. Al though the pattern of the cruel knot was given "long ago in China," Kingston, as a Chinese-American, must move beyond that pattern to make one of her own, incorporating new threads and creating even more complex interweavings. As a female, too, she must find a new de

A Simulation Study of Multimicrocomputer Networks.

Abstract: Recent developments in integrated circuit technology have suggested a new building block for parallel processing system::;: the single chip computer. This building block makes iL economically feaSible to interconnect large numbers of computers to ferm a muttiImcrocomputer network. Becat:.se the nodes of .men a network do not share any memory, it is Cl'llclUl that a inlerr,unneclion network capable of efficiently supporting message passing be found. We prp.sent a model of Lime varying computation based on task precedence graphs that corresponds closely to the beilav1rIl' of fork/join algorithms such as divide ~nd conquer. Using thIS mond, we investigate the behavior f)f t:!ve interconncctiol~ ndwod~s under varying "Workloads with distributed scheduling.

A contribution to the investigation of time-sharing ability*

Abstract: The aim was to investigate whether a distinct time-sharing factor is involved in performance of complex tasks. Three complex tasks were used, each of which consisted of two simple component tasks. On each of five consecutive days 51 subjects performed all these tasks, both complex and simple, twice: once singly and once concurrently with an additional loading task. The performances of the nine tasks (i.e. three complex and six simple) recorded under both conditions were intercorrelated and factor analysed. Four factors emerged, among which one was interpreted as a time-sharing factor.

Factors Affecting Line Tracing in Tactile Graphs

Abstract: Twenty-four braille readers in grades 4 to 12 performed a line-tracking task on tactile line graphs which differed in the type of raised line used to represent the data curve (continuous-interrupted, narrow-wide) and the nature of the display background (grid, no grid). A grid was found to impair the trackability of every line tested, despite high levels of discriminability between the test lines and the grid line. Line type and grade level had only marginal effects on tracking proficiency. Implications for the design of tactile line graphs for the blind are discussed.

Interactive work station with auxiliary microprocessor for storage protection

Abstract: An interactive work station in which a main microprocessor (1) controls various input/output devices (4) using a read/write memory (6) containing data and/or control code. An auxiliary microprocessor (8) is arranged to monitor access of the memory (6) by the main microprocessor (1) whilst the latter is executing STORE instructions. The main microprocessor (1) maintains a storage allocation table (11) in the memory. The auxiliary microprocessor (8) queues task identification information and STORE target addresses received from the main microprocessor (1) in a stack. By comparing the active task identification with the task identification stored in the storage allocation table (11) for each STORE target address, the auxiliary microprocessor (8) provides a storage protection mechanism for the main microprocessor (1) with substantially no performance degradation of the latter. The task giving rise to the error is interrupted although other independent tasks may be allowed to proceed.

Interface system for inter-program input/output buffer

Abstract: PURPOSE:To easily decide the influence and suitability when changing a design of a program, by fetching and processing a data from an exclusive buffer by a receiving instruction, and sending out a result data to a buffer of other program by a transmitting instruction. CONSTITUTION:Each task 2a-2c inputs an input data from task exclusive input/output buffers 122-12c, respectively, by a receiving instruction 8 from a data delivery control routine 11, and sends out an output data to the buffers 12a-12c by a transmitting instruction 9. These instructions 8, 9 transfer only the name of a task to each task, and an address of input/output data is decided in accordance with an inter-task interface related diagram in which the control routine 11 is designed in advance. The control routine 11 decides the address, and after that, stores the input/output data in the address area of a buffer 12 corresponding to a designated task. In this way, the input and output of these buffers 12 is executed by the data control routine.

A Computer Aided Workstation Assessor for Crew Operations - Wostas:

Abstract: WOSTAS is the first module in a Multi-Man-Machine Work Area Design and Evaluation System - MAWADES. WOSTAS is an interactive program aimed at grouping and/or subdividing crew activities in such a way that all job stations have a fairly equal amount of work in terms of the time to perform the tasks. Being a network based model, WOSTAS accepts mission oriented task requirements, and generates suggested total number of workstations and the tasks to be carried out at each station.

Degenerating method for computer

Abstract: PURPOSE:To eliminate a heavy fault of a system, by giving an execution priority level to tasks preliminarily on a basis of their classifications and inhibiting the execution of a task having the lowest exeuction priority level when the load of the computer attains high abnormally CONSTITUTION:One unit of the work to be executed in a computer is defined as a task; and each time the execution request of a task is generated, an execution request generation order and an execution priority level predetermined for this task are given, and the task is registered in a task queue 1 The queue is inspected by a task response scheduler 2, and a task having the first execution request generation order out of tasks stored in the queue is executed by a task execution scheduler 3 The task for which execution is terminated is erased from the queue 1 If the total number of tasks registered in the queue 1 attains a prescribed value, the response scheduler 2 erases a task, which has the lowest execution priority level and the last execution request generation order, out of tasks registered in the queue 1

Parallel problem solving on ZMOB

Abstract: A parallel problem solving system, PRISM (parallel inference system) is described. It is implemented on ZMOB, a highly parallel machine. PRISM provides facilities to trace execution steps, provides statistics concerning the execution of the problem, and can determine a minimum configuration of processors in ZMOB needed to execute a specific task. Programs and data stored on a host are automatically transferred to processors within ZMOB. The parallel problem solver, solves a problem (which may consist of a conjunction of subproblems) by taking advantage of and/or parallelism in a program, either automatically or suggested by the user. The underlying philosophy is that microprocessor technology can be exploited for high performance, low cost parallel computation. 18 references.

Method of preventing overloading of the central controller of a telecommunication system and arrangement for performing the method

Abstract: In telecommunication systems in which tasks are performed collectively and centralized by the processor of the central controler, the problem is encountered that this central control may be overloaded. The method in accordance with the invention has for its object to prevent this by rapidly detecting an imminent overload. The number of tasks (for example calls) being processed and the number of idle jobs which were performed are taken as a measure of the load. On the basis of the continuously actualized value of the maximum number of tasks which can be handled it is determined at each new task (for example a call from a subscriber) whether the maximum calls in the process of being set-up determined for that period is not exceeded.

Fault tolerant distributed systems using Ada

Abstract: This paper discusses the use of Ada on distributed systems in which failure of processors has to be tolerated. It is assumed that communication between tasks on separate processors will take place using the facilities of the Ada language, primarily the rendezvous. It is shown that there are numerous aspects of the language which make its use on a distributed system very difficult. The issues are raised from the desire to be able to recover, reconfigure, and provide continued service in the presence of hardware failure. For example, if a rendezvous takes place between two tasks on different processors, failure of the processor executing the serving task will cause the calling task to be permanently suspended because the rendezvous will never end. Extensive modifications to the execution support required for Ada are proposed which provide all the necessary facilities for programs written in Ada to withstand arbitrary processor failure. Mechanisms are suggested to allow processor failure to be detected and for tasks which would be permanently suspended to be released. Provided the required program structures are used, continued processing can be provided.

Display device for response time of multicomputer system

Abstract: PURPOSE:To reduce the load individual computers and guide the operator in respect to the transition of the response time of each computer, by providing one monitoring computer, which measures the response time of each computer, in the multicomputer system. CONSTITUTION:A clock 17 supplies the time signal to CPUs 14 in parallel, and the signal output time point and the signal input time point in a CPU 18 are matched to each other. When the execution request of a task is generated, each CPU 14 sets the signal of logical ''1'' to this task 15 during the time from the start indication to the execution indication and transmits this signal to the CPU 18 through a process input/output device 16. Tasks 15 are divided to about 16 levels in the whole of the multicomputer system and are transmitted to the CPU 18 in time division. Sixteen kinds of level signal are transmitted from respective tasks 15, which are divided to 16 levels, repeatedly in every time frame. If the task is not within a response time, the signal is set to logical ''0''. Response times for respective levels are measured and stored and are displayed 19 on a display and are printed 20 on a printer 20 in time series, thus reporting them to the operator.

Executing system of os

Abstract: PURPOSE:To attain a parallel operation, by cutting off a part that is capable of a parallel operation as an independent program in an operating system and then allotting a working processor to every program. CONSTITUTION:An operating system OS is roughly provided with an SVC process routine group 420, an interruption process routine group 410, an OS process dispatcher 431, a task dispatcher 441, an idle routine 450 and an OS process group 436. The group 420 serves as an OS service counter to a task group 442. The group 410 processes an interruption.

Fault diagnosing system of arithmetic processor

Abstract: PURPOSE:To increase the range of diagnosis and to improve the reliability for the titled diagnosing system, by checking the executing address, executing order and executing time of a program and enabling the diagnosis of the execution estimated address, the execution estimated time and the executing time respectively with every task unit. CONSTITUTION:The plural tasks, the task-based execution diagnosing time and the task-based execution estimated address group which are changed into a unit for each series of process program are stored in a memory 11 connected to an arithmetic processing part (CPU)10. Then the execution estimated address is stored in an diagnostic cue 14 based on the order of register request of the CPU10 and via a diagnostic cue register circuit 13. The address stored at the head of the cue 14 is compared with the executing address of a memory 11 through an address comparator 16. When a coincidence is obtained from this comparison, the executing address of the cue 14 is drawn out to a diagnostic cue drawing-out circuit 17. At the same time, the reset signal is delivered to a time circuit 12. Then the signal alarming the occurrence of a fualt is delivered from the circuit 12 in case the reset signal is supplied by the CPU10 before the execution doagnosis time for each task. Thus the range of diagnosis is increased.

Multitasking OS manages a team of processors

Abstract: MTOS-68k is a real-time multitasking operating system designed for the popular MC68000 microprocessors. It aproaches task coordination and synchronization in a fashion that matches uniquely the structural simplicity and regularity of the 68000 instruction set. Since in many 68000 applications the speed and power of one CPU are not enough, MTOS-68k has been designed to support multiple processors, as well as multiple tasks. Typically, the devices are tightly coupled single-board computers, that is they share a backplane and parts of global memory.

Task control system of multiprocessor system

Abstract: PURPOSE:To allow synchronism collation even when two microprocessors differ in processing time greatly to cause deviation in timing, by synchronizing both microprocessors with each other on the basis of the judgement of a main system once data from an external device is concatenated to a task. CONSTITUTION:A main microprocessor 11 and a conventional microprocessor 12 are connected to the external device 8, and synchronous data transmitter and receivers 13 and 14 are coupled with those microprocessors 11 and 12 and coupled mutually through a synchronism data transfer line 15 to constitute a synchronous port. Input data from the external device 8 is fetched in the microprocessors 11 and 12 at the same time and stored in input buffers. Once the task requests the input data, synchronism data is generated and the received data of both systems are collated with each other and then used for the task.

Suspension locking in a multilevel multiprocessor

Abstract: For multilevel processors in which independent processing of tasks is possible at a plurality of processing levels, current processing taking place at the most significant level at which a priority task exists, a processor in which a potential owner is suspended becomes, in general, free to continue processing at some other level.

Scheduling system of os

Abstract: PURPOSE:To perform high-speed operating system (OS) processing through an OS with less capacity than when a task waiting for resources is left, by selecting either of an OS process and a task waiting for resources are selected and performing an OS process in OS mode when it is selected CONSTITUTION:When a resource queue 312 is generated during the routine execution 311 of an OS, this process is interrupted and an OS process as a resource waiting program is registered Then, either of a resource waiting task and the OS program is selected in OS mode at a part 331 and when the selected one is the OS process, the program execution state of a computer is set for the OS, thereby restarting the interrupted process When the resource waiting task and OS process are both present, the OS process is selected and executed with priority to the task on resource release detection 313

Dynamic Parameter Array System (DPA)

Abstract: This paper describes software which provides a means of sharing data among tasks and of accessing and altering dynamically the values of parameters in an executing task. The parameters reside in an RSX-l1M memory management region or a VMS global section. The data may be accessed and altered by any task attaching the region. An interactive task is described which allows the user read/write access to the parameters from the keyboard. Keyboard commands can be used to make a disk file copy of values in the region, to initialize the values from a disk file, to examine and modify values, and to define synonyms for parameters. User-callable subroutines which create, attach, and map the region are also described.

Program managing method of remote monitor controller

Abstract: PURPOSE:To process plural tasks easily with good accuracy, by providing a timer controlling a processing time of a central operation processor processing plural tasks cyclicly. CONSTITUTION:When the number of tasks to be processed is three, the processing time of each task by a CPU3 is T1-T3, an output time of a control signal from a timer 9 is taken as T and programmed in advance. When a control signal of high level is outputted from the timer 9, it is discriminated at the CPU3 and the processing of each task is done sequentially. A control signal of low level is outputted after the time T, the processing of one period of the CPU3 is finished and the processing for the 1st task only is done. The cycles above are repeated and the 1st - the 3rd tasks are processed cyclicly. Plural tasks are processed easily with good accuracy with a simple program like this.