Showing papers on "Task (computing) published in 1985"

Reconfigurable dual processor system

Abstract: A is a duel processor system (100) with duplicated memory (114,124) has two modes (10,11) of operation: a converged mode (10) in which one of the two processors (101,102) is active and executing all system tasks while the other processor is inactive; and a diverged mode (11) in which both processors are active and independently executing different tasks. The system automatically changes modes in response to requests such as manual and program control and certain system fault conditions. In diverged mode, the system may be in either of two states of operation (1 and 2). In one state (1) one processor (101) is designated a primary processor, and in the other state (2) the other processor (102) is designated the primary processor. In the converged mode the system may be in either of four states of operaton (3-6). In two of these states (3,4) one processor is active while the other processor is standing by ready to take up execution of tasks from the point where the one processor stoped execution. In the other two of these states (5,6) one processor is active while the other processor is out of service and cannot take up task execution without being initialized. The system 100 makes transitions between the various states in response to requests. Except for transitions of an active processor to an out-of-service condition, the state transitions are transparent to tasks other than fault recovery programs and, upon a fault condition, the faulted program.

On the Expected Relative Performance of List Scheduling

Abstract: Let XI„ = X1, ', Xn denote an ordered list of service times required by n tasks. The service will be performed by m ≥ 2 processors working in parallel. Each processor serves one task at a time and, having once started a task, finishes it before starting another. A schedule determines how the tasks are to be served. A list schedule keeps the tasks not yet serviced listed in the order prescribed by XI„. Whenever a processor completes a service, it then takes its next task from the head of the list. The makespan of a schedule is the time required for all service to be completed. The makespan LXI„ of a list schedule is usually longer than necessary. Reordering the tasks in an optimal way can reduce the makespan to OPTXI„, the smallest possible makespan, but requires knowing the Xi in advance and solving an NP-complete problem. The ratio RXI„ = LXI„/OPTXI„ measures the penalty paid for serving the tasks in a predetermined order. Here, the service times Xi are treated as independent identically distributed random variables. Two distributions for Xi, uniform and exponential, are considered. Bounds on the mean ERXI„ and on the distribution function P[RXI„ >x] are obtained.

Self-configuring computerized robot control system with call-back feature

Abstract: Apparatus constructed such that it may control various other equipment for the performance of various work tasks, even other equipment yet to be designed for work tasks yet to be designed. The improvement in the apparatus feature a call-back control procedure which is activatable from device intelligence to ensure that a specific robotic device can be "called-back", i.e. reactivated, to perform some specific action without the necessity of there being a code entry in the sequence intelligence of the central computer system enabling the specific action. The apparatus comprises a central computer control means comprising (1) a dictionary storage means for tagging and storing command-specific parameters for a specific work tasks and that specific robot module to which each of the parameters belongs and (2) sequencing means to schedule said work-tasks for a plurality of said modules. The module also can be activated for the task without use of the sequencing means, e.g. by having the module request one of its own dictionary entries.

Method and apparatus for incremental load simulation

Abstract: An adjustable incremental load simulator 200 acts upon a telephone control processor 300 to drive the processor toward and into an overload state. This is accomplished by reducing the number of processing cycles available for system task execution by execution control 360. The simulator 200 pulses an interrupt circuit 350, thereby halting the execution of system tasks for a fixed number of processing cycles. The adjustable incremental load simulator has an adjustment which controls the rate of generation of interrupt signals and thereby controls the rate at which system task execution cycles are made unavailable to the execution control. The performance of the system is monitored via a display 150; thus, the simulated incremental load can be adjusted while system performance is monitored.

Touch as a communicative sense: introduction.

Abstract: A brief survey is made of some of the threads of research and theory that have converged upon the problems of application of the touch sense to the task of substituting for the hearing process.

Efficient initialisation routines for multiprocessor systems programmed in Ada

Abstract: As an Ada task cannot be initialised at the time of creation a rendezvous must be used to pass identification data to those tasks that require it. With multiprocessor systems this initialisation phase can be a source of inefficiency as it is, essentially, a sequencial activity. Algorithms, and code, are presented that remove this potential bottleneck by involving all tasks in the initialisation process. Two approaches are discussed; the first delays each active task by a minimum amount (the time it takes to perform two rendezvous), the second method delays all active tasks but initialises the maximum number in any time period. For example 1023 tasks can be initialised in the time taken to perform 10 rendezvous.

A Fine-Motion Planning Algorithm

Abstract: Assembly tasks typically involve tight fits and precise positioning beyond the capability of position-controlled robots. The motions required for such tasks, called fine-motions, may be performed by means other than pure position control. Fine-motions must overcome the inherent uncertainty in the robot's position relative to its environment. This uncertainty results from errors in sensing, modeling, and control. If bounds on these errors are known or can be estimated accurately, motions may be planned that will perform fine-motion tasks despite the uncertainty. Automatic planning of robot motions to perform these tasks prevents the tedious, error-prone process of constructing a plan for each task by hand. This paper presents an approach to fine-motion planning and an implementation of the algorithms in a planning system. A simple method is explored to plan and perform assembly tasks in the presence of uncertainty using a geometric model of the task, error bounds, and a model of compliant behavior. The principal ingredients of the method are algorithms that manipulate graph representations of the task to find, and choose from, a small number of alternative plans. The approach is implemented in a system that generates plans from task descriptions of two degree-of-freedom operations.

On the applicability of using multiprogramming level distributions

Abstract: A computer system's workload is represented by its multiprogramming level, which is defined as the number of tasks (jobs, customers) which actively compete for resources within the system. In a product-form queuing network model of the system, the workload is modeled by assuming that the multiprogramming level is either fixed (i.e., closed model) or that the multiprogramming level depends upon an outside arrival process (i.e., open model). However, in many actual systems, closed and open models are both inappropriate since the multiprogramming level is neither fixed nor governed by an outside arrival process.In an actual system., the multiprogramming level varies due to features such as task spawning, killing, blocking, parallel processing, and/or simultaneous resource possession. The multiprogramming level is a random variable with an associated distribution. This paper demonstrates that improved models can result from using this multiprogramming level distribution information. Several examples relative to open versus closed models, subsystem models, actual system models, and blocking models are given which demonstrate the applicability of using multiprogramming level distributions. This applicability, shown via the examples, is the main contribution of the paper. The examples also motivate interesting theoretical results relating to open models, closed models, and subsystem models.

Distributed Computing for Vision: Architecture and a Benchmark Test

Abstract: Computer vision algorithms are notorious for their computational expense. Distributed vision, the use of more than one processor, can decrease computation costs and speed up algorithms. There are various ways to do this, ranging from parallelism at the sensor level to true multiprocessor systems. This correspondence first describes a system of the latter type: a system of microprocessors on a high-speed bus. A canonical vision task, locating a number of objects and measuring certain two-dimensional features of those objects, serves as a benchmark test for the system. An algorithm for this task is presented. Performance measures are compared from implementations on the distributed system, a Vax 11/750, and a Vax 11/780. Results indicate that three microprocessors outperform a Vax 11/780 at this task. Finally, other more interesting distributed algorithms are briefly discussed.

The Interfering Effects of Processing Code on Visual Memory

Abstract: The possibility of reducing task interference in complex aviation environments by taking advantage of the verbal-spatial short term memory dichotomy is explored in a dual-task paradigm. Eighteen subjects performed verbal and spatial retention memory tasks concurrently with intervening verbal and spatial cognitive tasks. Both number and processing code of the intervening tasks were manipulated. Support was found for code-specific interference such that concurrently performed tasks of the same code disrupted performance more than concurrent tasks of different codes. In addition spatial memory was found to be more fragile than verbal memory. Implications of the findings to mental workload reduction include task scheduling, presentation format, and assignment.

Controlling method of multitask

Abstract: PURPOSE:To enable all CPUs to be applied to a microcomputer multitask control system by controlling the execution of a task in accordance with a command generated from a unit other than the CPU. CONSTITUTION:A multitask support proccessor (MTSP) element 1 is connected to the system through a master CPU2 and an internal bus 3 similarly to the other peripheral input element 4. A program memory 5 programs an initializing program of the MTSP element 1 and plural tasks independently and is constituted by connecting a memory 6 as a data memory to be used by respective tasks. The MTSP element 1 is provided with a task scheduling function for attaining the multitask system, synchronizing and communicating functions of tasks, a memory controlling function, a clock function, etc. An access from the CPU2 to the MTSP element 1 is executed by a command and an access from the MTSP element 1 to the CPU2 is executed by interruption.

Fallback operation system of application program

Abstract: PURPOSE:To execute an another task in an application program by forming a temporary data set when the application program fails the allocation processing of a certain data set or its open processing. CONSTITUTION:Prior to the execution of tasks 8-A, 8-B, 8-C, a task 8-D requests the opening of resources A, B, C to a resource open processing mechanism 2. If the opening of the resource C is failed, the application program 1 is abnormally ended. In order to operate the fallback of the application program, a temporary resource X is formed in stead of the resource C in question at first. To form the temporary resource X, an operator inputs the variable resister serial number of the variable resister 7-X for forming the temporary source X, the name of a skimmer 9 defining the the resouce C in question and SWITCH(DS) command designating the name of the resouce C in question from a console 5. After the preparation and registration processing of the resource X is carried, the operator executes the application program 1 again.

A comparison of operator performance in manual and automated versions of a dynamic decision-making task

Abstract: The study of operator performance in manual and automated versions of dynamic decision tasks is proposed. The two microcomputer paradigms of simple and complex, dynamic scheduling tasks are described. Error detection accuracy and latency of assignment, and fault detection and correction for the two tasks are to be analyzed.

Reconfigurable dual processor system and method for operating it

Abstract: A dual processor system (100) with duplicated memory (114, 124) that has two modes (10, 11) of operation: a converged mode (10) in which one of the two processors (101, 102) is active and executing all tasks of the system while the other processor is inactive; and a diverged mode (11) in which both processors are active and executing substantially independently of each other different tasks of the system. The system automatically changes its modes of operation in response to requests such as manual and program control and certain system fault conditions. In the diverged mode, the system may be in either of two states of operation (1 and 2). In one state (1) one of the processors (101) is designated a primary processor, and in the other state (2) the other processor (102) is designated the primary processor. In the converged mode the system may be in either of four states of operation (3-6). In two of these states (3, 4) one of the processors is active while the other processor is standing by ready to take up execution of tasks from the point where the one processor stopped execution. In the other two of these states (5, 6) one of the processors is active while the other processor is out of service and cannot take up task execution without being initialized. The system (100) makes transitions between the various states in response to requests. Except for transitions of an active processor to an out-of-service condition, the state transitions are transparent to tasks other than fault recovery programs and, upon a fault condition, the faulted program.

Measurement of the Criticality of Combat Tasks

Abstract: : This report describes the development of a method for selecting combat tasks for training based on their criticality in determining the successful accomplishment of the unit mission in which they are performed. Comparisons are made between this method for assessing task criticality and the approach recommended in the Instructional Systems Development (ISD) model. One of the major problems experienced by training developers is the lack of sufficient time and resources to train all of the tasks that are performed by soldiers in a particular duty position. Currently the Army trains only those tasks that can be handled within the available time and resource constraints, but to include those tasks that are most critical to mission success. Although this approach would prevent soldiers from learning all of the tasks performed in an MOS, careful selection of tasks could keep the impact on unit performance to a minimum. Ideally, tasks that are not learned during institutional training could be learned later during unit training or learned informally while on the job.

Control system of call processing task

Abstract: PURPOSE:To execute easily addition and deletion and modification of priority order of exchange service by making optionally registration of plural services with respect to one event a possible and activating sequentially the service having higher registered priority. CONSTITUTION:A state memory part for storing the call state, an input event kind memory part for storing the kind of input events and a task deciding table for retrieving in such a way that the registered priority of service and contents are sequentially incremented are provided in main memory device 2-2 of a high performance terminal 2. Desired tasks are sequentially executed in accordance with the information sequentially read out from the task deciding table based on the call state read out from the state memory part and the priority information of the event and tasks read out from the input event kind memory part.

Task scheduling system of data processor

Abstract: PURPOSE:To improve the using efficiency of a data processor by using a hardware circuit to search repetitively for task waiting for execution of the highest priority which requires the longest execution time among scheduler actions. CONSTITUTION:Hardware flags 21 equivalent to the number of priorities of a task are provided to a control circuit 20 for priority, and the presence or absence is displayed for a task waiting for execution. The relative addresses for the read/write mode of the flag 21 are produced by a controller 22. A counter circuit 24 gives the address information of ''0''-''255'' to the controller 22 when it detects an on-flag of the highest priority. An interface circuit 26 is connected to a central processor and controls the interpretation and execution of an instruction fed from a scheduler.

Exclusive control system for inter-task shared data

Abstract: PURPOSE:To attain an exclusive control system of shared data for extraction of the parallel property by distributing ticket numbers for control of the sequential property of each process to these processes in a process production mode. CONSTITUTION:A request interpretation unit 1 judges the read or write of an input request and selects a substitute part deciding unit 6 through a request scheduler 2. The unit 6 performs the processing in response to the type of the request when signals 13-15 are all available and delivers the control to an instruction execution unit 4. The unit 4 gives +1 to the value of the signal 15 and the ticket number (n) received with the signal 16 and writes them to a register 5 with a write request. Then a request end output 21 is sent to a gate 7. The gate 7 waits for an output 17 to be supplied from another substitute part deciding unit which has a ticket number (n+1). Then the gate 7 outputs a release request signal 23 to the scheduler 2 when the signal 21 is available.

Control system for substitute of overlay

Abstract: PURPOSE: To enable an execution request task to carry out programs with no consciousness of the program on a main memory, by having residence of a substitute part on the main memory to perform the overlay procedure against the program stored in an external storage and to be overlayed. CONSTITUTION: A substitute part 13 is resident on a main memory 1 to perform the overlay procedure against programs A, BW21 stored in an external storage 2 and to be overlayed. Thus an execution request task C12 on the memory 1 issues an execution request EXEC macroinstruction after regarding as if the programs A, BW21 were set on the memory 1. As a result, the part 13 overlays the program A21, for example, on the memory 1 from the storage 2. Then the task C12 can produce a command to be executed by the program A14 with no consciousness of the overlay control at all. COPYRIGHT: (C)1987,JPO&Japio

The robot sequencing problem: polynomial algorithm and complexity

Abstract: An industrial robot is to perform n tasks, Each task will be executed by exactly one of robot's m grabs. Precedence relations are given by a finite directed acyclic-graph such that some tasks can be performed only after other tasks have been completed. The problem is to find a sequence of tasks which fits the precedence relations and minimizes the number of grab's changes, The problem is shown to be NP-hard and a polynomial algorithm for a special case including the two-grab-problem is presented.

Theoretical Results on Distributed Processing with Limited Computing Resources

Abstract: : A task is a set of related operations which can be performed on some input data. An algorithm is a collection of tasks with an underlying structure defined in terms of precedence relationships among the tasks. Two models of processing systems are considered. A distributed processing system consists of separate processors, each one dedicated to perform a single task, and permits pipelined processing of consecutive requests, as well as concurrent processing of tasks for a given request. A centralized processing system consists of a single processor which performs all the tasks for a given request sequentially, and services the requests sequentially without pipelining. The performance of these two systems is compared in terms of average execution times, under the constraint that the capacity of the processor in the centralized system is equal to the sum of the capacities of individual processors in the distribution system.

Interpreting parallel processor performance measurements

Abstract: This paper discusses execution time versus number of simultaneous operations in parallel computing systems The main focus is on shared memory multiprocessors A model for execution time as a function of the number of processes used in a computation is developed The model addresses the effect of sequential code, code which can be executed by only a limited number of processes, hardware limits to speedup, critical section synchronization overhead and the influence of task granularity The model is shown to correspond very closely to experimental measurements of execution time on the HEP pipelined, shared memory multiprocessor Use of the model as an analysis tool in complex parallel programs is indicated

Multiprocessor application in flight management systems

Abstract: The Flight Management Computer System (FMCS) for the 737-300 has a three-processor architecture with fixed task allocations divided F'imarily into the navigation, performance, and inputloutput functions. The computer architecture uses controlled communication protocol through a global memory accessible to all processors. of this architecture are in functional separation for testing and validation, and in increased throughput by parallel processing of several system functions. The disadvantage is in the inefficiency of fixed task allocation when a high demand for several tasks allocated to the same processor occur simultaneously, thus limiting the system response time to a single prOCeSSOr'S throughput. An alternate multiprocessor architecture for future systems may consider variable task allocation to the processing elements, depending on the availability and capability of each element. system controller is required to assign tasks as a function of the response priority. In this way, a higher effective throughput is achieved since each processing element is more fully utilized. Issues such as internal bus control, memory access, and priority assignment methods are explored for this type of architecture. Advantages

Time division multiplex memory bank control system

Abstract: PURPOSE:To attain efficient system processing by recognizing the exclusive state of a memory bus, switching selectively a memory bank during the task processing to a specific memory bank, and allowing the switched memory bank to access other task processing. CONSTITUTION:A memory bank selector 14 is selected depending on the content of output signals 2 -2 of a decoder circuit 13. The low-order 4-bit and CH of data bus information are stored in a storage circuit C of an I/O port comprising ports 10-12 at the print data transfer task. The CH is stored in a storage circuit B at the data reception task from the high-order machine. Moreover, the CH is stored in a storage circuit A at the task processing not requiring the DMA processing. A DMA control section discriminates the DMA request of each task with priority, makes a DACk signal 5 response to the circuit B and selects the circuits A-C and feeds the result to a selector 14. Thus, the RAM of the required memory bank is accessed to improve the processing efficiency at each task.

Response controlling system of circuit

Abstract: PURPOSE:To compensate a response even in case when a task which is being processed does not abandon a right of execution for many hours, by executing a control so that a response is returned to a control station from an interruption processing part of a circuit control part with respect to a call signal from the control station. CONSTITUTION:An interrupting signal is sent to an interruption processing part 11-1 of a work terminal WS21 from a control part 1 and the processing is ended, thereafter, a call signal PS returns a response A within a prescribed time. Therefore, the control station 1 can know an interruption processing state in the work terminal WS21. After this response A has been returned, the right of execution is shifted to a task A again, and the processing is continued from (e).

Response control system of line

Abstract: PURPOSE:To decrease the processing time by resetting a reception section until a processing at a line level of a data is finished to suppress the response to a call signal from a control station thereby reducing the correspondence of excess call and response. CONSTITUTION:The reception section 12 is inhibited in case of the processing of either or an interruption processing section 11-1 and a task processing section 11-2 of a line control program processing section 11 of a job terminal equipment 2 in response from interruption data from a control station. In case of the task processing, data from a buffer 14 is read, transferred to a main storage device 20 or posted to a high-order task execution section 16. When the post (1) to the high-order task execution section is finished, the inhibition of reception of the reception section 12 is released (2) from a monitor 15 and a call signal is transmitted to a vector table 13. The reception data posted in the task execution section 16 is stored in the main storage device 20.

Automatic tuning of multi-task programs for real-time embedded systems

Abstract: This paper describes a programming tool for real-time embedded systems. Real-time embedded systems are usually implemented by multiple tasks. It is important to allocate tasks to the system appropriately. Our tool, called TRUE, performs the allocation of tasks by transformation of the program the user has written. TRUE reads the program and the requirements about its response time. TRUE transforms the program applying rules based on the requirements. Then the program is translated into a code for operating system I-TRON. I-TRON is our original real-time operating system for 32-bit microprocessors. This paper also describes the implementation of TRUE and an example of its use.

Guard processing method of important signal

Abstract: PURPOSE:To prevent an important signal from malfunction even if softwave runs away by executing respective program tasks independently and sending output information in accordance with respective program tasks. CONSTITUTION:A task schedular 7 makes the program tasks 5, 6 execute alternately at 100ms period by a time interrupting method or the like. If an output signal 3 is set up to ''1'' and sent in error when a processor 1 executes malfunction due to noise or the like, a program runs away, the program task 5 executes a step for setting up the outut signal 3 to ''1'', and an input signal 2 is ''0'', the execution of the program is returned to the task schedular 7, so that the program task 6 is executed from its head and an output signal 4 is not turned to ''1''. Thus both the output signals 3, 4 are scarecely set up to ''1'' simultaneously.