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Task (computing)

About: Task (computing) is a research topic. Over the lifetime, 9718 publications have been published within this topic receiving 129364 citations.


Papers
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DOI
01 Jan 2008
TL;DR: A method to analyze the duration and the cost of sequences of integration and test-diagnose-fix tasks and indicates that choosing a di??erent test sequence can reduce the test duration by 30% to 70%.
Abstract: Complex manufacturing machines, like ASML wafer scanners, consist of thousands of components like electronic boards, software, mechanical parts and optics. These components of multiple disciplines are assembled or integrated into modules. The modules are integrated into sub-systems forming the system, according to an integration plan. Components as well as modules, sub-systems, and systems, can be tested, diagnosed and ??xed, according to a test-diagnose- fix plan. An increase in the number of components results in an increase of the number of tasks in these plans. Moreover, the effort required to obtain a sequence that describes in which order the tasks should be executed also increases. The duration and the cost of a sequence depends on the quality of the system. In this project we introduce a method to analyze the duration and the cost of sequences of integration and test-diagnose-fix tasks. The method uses test-diagnose-fixed models to analyze the performance of sequences. The basic elements in such a model are: a) test, diagnose and fix tasks with their costs and durations, b) fault states, c) the coverage of test tasks on fault states, d) failure probabilities of fault states. These elements can be obtained for components, modules or sub-systems of multiple disciplines. Three case studies have been performed using this method. The outcome of the analysis indicates that choosing a di??erent test sequence can reduce the test duration by 30% to 70%. In addition, three techniques have been developed to improve integration and test-diagnose-fix sequences: ? To reduce the execution time of test-diagnose-fix sequences an algorithm has been developed to determine a new test task with an optimal coverage w.r.t. the fault states. The algorithm selects the new test task based on the maximum information gain. A test sequence, including the new test case, improves the test duration of the test-diagnose-fix task, because faults can be detected earlier. ? To reduce the execution time of test-diagnose-fix sequences an adapted hypergraph partitioning algorithm has been developed. The algorithm partitions a test-diagnose-??x task into smaller tasks which can be executed in parallel. The result of a case study is a reduction of the test duration by 30% with a concomitant increase of 30% in the test cost. ? The impact of the choice of the system architecture on the execution time and planning effort of integration and test-diagnose-fix sequences is investigated

90 citations

Patent
18 Sep 2001
TL;DR: In this paper, the authors present dialog boxes (400, 500, 600, 700, 800, 900) for pilot commands so that task parameters may be input or modified, such as "direct-to", "hold", "procedure turn", "cross with flyover", "show info", "orbit", "radial", and the like.
Abstract: Various embodiments of the invention suitably provide dialog boxes (400, 500, 600, 700, 800, 900) in response to pilot commands so that task parameters may be input or modified. Pilot tasks include 'direct-to', 'hold', 'procedure turn', 'cross with flyover', 'show info', 'orbit', 'radial', and the like. According to various embodiments, certain dialog boxes include graphical functionality (502) and incorporate 'human factors' enhancements such that information is efficiently presented in a manner that corresponds to air traffic control instructions.

90 citations

Proceedings ArticleDOI
01 Oct 2009
TL;DR: The obtained results suggest that the wall-following task, formulated as a pattern classification problem, is nonlinearly separable, a result that favors the MLP network if no memory of input patters are taken into account.
Abstract: This paper reports results of an investigation on the degree of influence of short-term memory mechanisms on the performance of neural classifiers when applied to robot navigation tasks. In particular, we deal with the well-known strategy of navigating by “wall-following”. For this purpose, four standard neural architectures (Logistic Perceptron, Multilayer Percep-tron, Mixture of Experts and Elman network) are used to associate different spatiotemporal sensory input patterns with four predetermined action categories. All stages of the experiments — data acquisition, selection and training of the architectures in a simulator and their execution on a real mobile robot — are described. The obtained results suggest that the wall-following task, formulated as a pattern classification problem, is nonlinearly separable, a result that favors the MLP network if no memory of input patters are taken into account. If short-term memory mechanisms are used, then even a linear network is able to perform the same task successfully.

90 citations

Journal ArticleDOI
TL;DR: If all the software bottlenecks can be removed, the performance limit will be due to a conventional hardware bottleneck, and the method for estimating the performance benefit to be obtained is given.
Abstract: Software bottlenecks are performance constraints caused by slow execution of a software task, in typical client-server systems a client task must wait in a blocked state for the server task to respond to its requests, so a saturated server will slow down all its clients. A rendezvous network generalizes this relationship to multiple layers of servers with send-and-wait interactions (rendezvous), a two-phase model of task behavior, and to a unified model for hardware and software contention. Software bottlenecks have different symptoms, different behavior when the system is altered, and a different cure from the conventional bottlenecks seen in queueing network models of computer systems, caused by hardware limits. The differences are due to the "push-back" effect of the rendezvous, which spreads the saturation of a server to its clients. The paper describes software bottlenecks by examples, gives a definition, shows how they can be located and alleviated, and gives a method for estimating the performance benefit to be obtained. Ultimately, if all the software bottlenecks can be removed, the performance limit will be due to a conventional hardware bottleneck. >

90 citations

Patent
24 Sep 1998
TL;DR: In this paper, a graphical undo/redo manager provides a graphical indication of multiple tasks that were recently performed, allowing a user to undo multiple tasks in one step by selecting a task the user wishes to revert to, and undo all the commands that were done subsequent to the selected task, taking the computer program to a desired state in only one user operation.
Abstract: A graphical undo/redo manager provides a graphical indication of multiple tasks that were recently performed. A user may undo multiple tasks in one step by selecting a task the user wishes to revert to, and the graphical undo/redo manager then undoes all the commands that were done subsequent to the selected task, taking the computer program to a desired state in only one user operation. In similar fashion, a user may redo multiple tasks in one step by clicking on a selected subsequent task (that was previously undone) that the user wishes to go forward to, and the graphical undo/redo manager then redoes all the commands between the last undo and the selected task, including the selected task. In addition, the graphical undo/redo manager provides for collapsing multiple tasks into a marker, either automatically when certain commands are executed in the computer program or upon command by a user for future reference.

90 citations


Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202210
2021695
2020712
2019784
2018721
2017565