Task (computing)

About: Task (computing) is a research topic. Over the lifetime, 9718 publications have been published within this topic receiving 129364 citations.

Set-based Tasks within the Singularity-robust Multiple Task-priority Inverse Kinematics Framework: General Formulation, Stability Analysis and Experimental Results

Abstract: Inverse kinematics algorithms are commonly used in robotic systems to transform tasks to joint references, and several methods exist to ensure the achievement of several tasks simultaneously. The multiple task-priority inverse kinematics framework allows tasks to be considered in a prioritized order by projecting task velocities through the nullspaces of higher priority tasks. This paper extends this framework to handle setbased tasks, i.e. tasks with a range of valid values, in addition to equality tasks, which have a specific desired value. Examples of set-based tasks are joint limit and obstacle avoidance. The proposed method is proven to ensure asymptotic convergence of the equality task errors and the satisfaction of all high-priority set-based tasks. The practical implementation of the proposed algorithm is discussed, and experimental results are presented where a number of both set-based and equality tasks have been implemented on a 6 degree of freedom UR5 which is an industrial robotic arm from Universal Robots. The experiments validate the theoretical results and confirm the effectiveness of the proposed approach.

Simulation and expected performance analysis of multiple processor Z-buffer systems

Abstract: The results of expected performance analysis and simulation of three multiple processor Z-buffer architectures are presented. These architectures have been proposed as approaches to applying many processors, working in parallel, to the task of rapidly creating shaded raster images. These architectures are attractive since they offer potentially high performance, in terms of image update rate, at modest cost. All three approaches make use of multiple instances of identical processor modules.The analyses and simulations indicate that substantial gain is possible by applying multiple processors to the task. But, as more and more processors are added, additional gains in performance become smaller and smaller. This result suggests optimal system sizes. The performance of these architectures depends on the processors used, the number of processors, and certain characteristics of the image environments. Each architecture has its own performance characteristics and limitations.

Compressing SQL workloads

Abstract: Recently several important relational database tasks such as index selection, histogram tuning, approximate query processing, and statistics selection have recognized the importance of leveraging workloads. Often these tasks are presented with large workloads, i.e., a set of SQL DML statements, as input. A key factor affecting the scalability of such tasks is the size of the workload. In this paper, we present the novel problem of workload compression which helps improve the scalability of such tasks. We present a principled solution to this challenging problem. Our solution is broadly applicable to a variety of workload-driven tasks, while allowing for incorporation of task specific knowledge. We have implemented this solution and our experiments illustrate its effectiveness in the context of two workload-driven tasks: index selection and approximate query processing.

Multiprocessor computer apparatus employing distributed communications paths and a passive task register

Abstract: Computer apparatus which employs a plurality of processing units, a memory unit, and a communication unit, each of the units including a data transfer bus. A bus coupler is provided between each pair of units of differing type to form a distributed data communications network. An addressable, passive task register is associated with one of the units for communication through the couplers and is adapted to register a task priority value associated with a task request, the register being readable by any one of the processor units to obtain the highest priority value registry.