Technology CAD

About: Technology CAD is a research topic. Over the lifetime, 781 publications have been published within this topic receiving 5343 citations. The topic is also known as: Technology Computer Aided Design & TCAD.

Physical Mechanisms behind the Field-Cycling Behavior of HfO2-Based Ferroelectric Capacitors

Abstract: Novel hafnium oxide (HfO2)-based ferroelectrics reveal full scalability and complementary metal oxide semiconductor integratability compared to perovskite-based ferroelectrics that are currently used in nonvolatile ferroelectric random access memories (FeRAMs). Within the lifetime of the device, two main regimes of wake-up and fatigue can be identified. Up to now, the mechanisms behind these two device stages have not been revealed. Thus, the main scope of this study is an identification of the root cause for the increase of the remnant polarization during the wake-up phase and subsequent polarization degradation with further cycling. Combining the comprehensive ferroelectric switching current experiments, Preisach density analysis, and transmission electron microscopy (TEM) study with compact and Technology Computer Aided Design (TCAD) modeling, it has been found out that during the wake-up of the device no new defects are generated but the existing defects redistribute within the device. Furthermore, vacancy diffusion has been identified as the main cause for the phase transformation and consequent increase of the remnant polarization. Utilizing trap density spectroscopy for examining defect evolution with cycling of the device together with modeling of the degradation results in an understanding of the main mechanisms behind the evolution of the ferroelectric response.

TCAD-based statistical analysis and modeling of gate line-edge roughness effect on nanoscale MOS transistor performance and scaling

Abstract: The effects of line edge roughness (LER) of nanometer scale gate pattern on the MOS transistor parameter fluctuations and their technology scaling are investigated using the simplified modeling and statistical analysis based on two-dimensional technology CAD (TCAD) tools. From the simple statistical analysis, it is shown that the gate patterns without appropriate LER may cause severe device parameter and performance fluctuations in highly scaled nanometer technologies, resulting in a negative average threshold voltages shift, a subthreshold slope degradation, an unrealistic effective channel length extraction and an exponential increase in off-state leakage current due to LER-induced inhomogeneous channel potential. The characteristics of the average off-state leakage current and the threshold voltage uncertainty as a function of technology scaling provide a useful guideline for advanced gate patterning process and demand much tighter control of LER less than 3-5 nm for a successful CMOS scaling into deep nanometer scale physical gate length regime below 50 nm.

Impact of LER and Random Dopant Fluctuations on FinFET Matching Performance

Abstract: Parameter variations pose an increasingly challenging threat to the CMOS technology scaling. Among the sources of variability, line-edge-roughness (LER) and random dopant (RD) fluctuations are significant in current technology nodes. In this paper, the impact of the LER and RD on the matching performance of FinFETs is investigated for the LSTP-32 nm node, where these devices represent an attractive alternative to the planar CMOS transistors. Line-edge-roughness contributions from the fin, top-, and side wall-gates of n- and p-channel FinFETs are compared by means of 2-D and 3-D technology computer-aided design (TCAD) simulations, performed with a quantum-corrected hydrodynamic model on large statistical ensembles. Correlations between geometrical roughness and resulting electrical parameters are analyzed to provide further insight into the impact of the LER. A noise analysis approach is adopted to evaluate the impact of RD fluctuations throughout the impurity concentration ranges of interest, providing a direct comparison with the line-edge-roughness contributions. The impact of the extension doping profile specifications on the LER- and RD-induced mismatch is investigated, highlighting the potential drawbacks of junction engineering.

Nanoscale MOSFETS: Physics, Simulation and Design

Abstract: This thesis discusses device physics, modeling and design issues of nanoscale transistors at the quantum level. The principle topics addressed in this report are 1) an implementation of appropriate physics and methodology in device modeling, 2) development of a new TCAD (technology computer aided design) tool for quantum level device simulation, 3) examination and assessment of new features of carrier transport in nano-scale transistors, and 4) exploration of device design issues near the ultimate scaling limit with the help of the developed tools. We concentrate on the technical issues by investigating a double-gate structure, which has been widely accepted as the ideal device structure for ultimate CMOS scaling. We focus on quantum effects and non-equilibrium, near-ballistic transport in extremely scaled transistors (in contrast to quasi-equilibrium, scattering-dominant transport in long channel devices), where a non-equilibrium Green’s function formalism (NEGF) has been used to deal with the quantum transport problem.