Showing papers on "Thin-film transistor published in 1975"

A hydrogen−sensitive MOS field−effect transistor

Abstract: An MOS transistor in silicon with 10−nm silicon dioxide as gate insulator and 10−nm palladium as gate electrode was fabricated. The threshold voltage of this transistor was found to be a function of the partial pressure of hydrogen in the ambient atmosphere. At a device temperature of 150 °C it was possible to detect 40 ppm hydrogen gas in air with response times less than 2 min.

Potassium ion-sensitive field effect transistor

Abstract: The construction and theory of operation of a potassiumsensitive field effect transistor Is described, and Its performance is characterized both as a solid-state field-effect device and as an electrochemical sensor. The performance of this device is comparable with the correspondlng PVC-type ion selective electrodes. The transistor operates satisfactorliy in the presence of proteins and it has been used for determination of potassium ion concentration in blood serum. A new type of electrochemical sensor, an ion-sensitive field-effect transistor (ISFET), was introduced when Bergveld removed the metal gate from a metal oxide semiconductor field-effect transistor (MOSFET) and exposed the silicon oxide gate insulator to a measured solution (I). A similar approach was followed later by Matsuo and Wise (Z), and this new subject area has been recently reviewed by Zemel (3). In the broader sense of chemically sensitive field-effect transistors, one sensitive to molecular hydrogen has also been reported (4). The ISFET is a result of the integration of two technologies: ion-selective electrodes and solid state microelectronics. This development opens several new possibilities, such as miniaturization, development of multiprobes, all solidstate design and in situ signal processing. Because of its small size, it presents a difficult encapsulation and packaging problem which is, however, amply offset by the elimination of electrical pick-up noise by in situ impedance conversion and on site signal amplification. Bergveld did not modify the ion-sensitive layer in any way although he considered introducing impurities in order to render the device ion selective. In this paper, we introduce a class of devices having a chemically-sensitive layer placed over the gate region, and we report our results with valinomycin/plasticizer/poly(vinylchloride) membrane

Process for fabricating non-volatile field effect semiconductor memory structure utilizing implanted ions to induce trapping states

Abstract: Disclosed is a non-volatile field effect information storage device which can be electrically written and erased. It consists of an insulated gate field effect transistor having a single gate dielectric material formed in two stages. The gate dielectric is made up of two adjacent layers of silicon dioxide, one of which is relatively thin and adjacent to the semiconductor substrate, while the other is relatively thick and implanted with ions at controlled depths and dosages near the interface with the first silicon dioxide layer. With the application of an appropriate control voltage on the gate structure, charges from the adjacent transistor channel region tunnel through the relatively thin layer of silicon dioxide and become stored in the trapping sites introduced by the implanted ions located in the second layer of silicon dioxide and very near the interface between the two silicon dioxide layers. While there, the charges control the conductivity of the channel, and thus the logic state of the transistor.

Silicon on sapphire MOS transistor

Abstract: An MOS transistor constructed using silicon on sapphire technology in which the channel region can be electrically connected either to the source or drain terminal is disclosed. The transistor is advantageous in that the shift of the threshold voltage of the transistor in the presence of radiation is substantially decreased. Connecting the channel region of the transistor to the source terminal also substantially reduces what is normally referred to as the "kink" effect in MOS transistors utilizing floating substrate channel regions. Reducing the sensitivity to radiation and the kink effect results in a transistor having improved electrical characteristics.

Flat panel display device with integral thin film transistor control system

Abstract: A large area integrated solid-state flat panel display is detailed in which thin film transistor addressing and drive circuitry is provided at each individual picture point with a display medium. The preferred display medium is an electroluminescent phosphor layer. An insulating layer of laminated photoresist is disposed over all electrical circuit elements except the electroluminescent drive electrodes.

Use of trapped hydrogen for annealing metal-oxide-semiconductor devices

Abstract: In a metal-oxide-semiconductor field effect transistor (MOSFET) device, in which the surface of the silicon semiconductor substrate suffers damage during such steps as a sputtering type deposition of a metallic electrode layer, and in which the silicon dioxide layer of the MOSFET device is sealed by the combination of metallic electrodes and insulator layers which are impervious to hydrogen, gaseous hydrogen in introduced into the oxide layer prior to the deposition of the metallic layer, thereby trapping hydrogen in the oxide. The damage in the silicon is thereafter annealed by heating at an annealing temperature subsequent to the deposition of the metallic layer, whereby the trapped hydrogen migrates from the oxide to the silicon surface and repairs to the damage.

N-channel MOS transistor

Abstract: An N-channel MOS transistor wherein two layers of different dielectric materials (e.g., silicon dioxide and silicon nitride) are used in conjunction with a P-doped silicon gate to permit the use of a higher resistivity P-type substrate. This enables a higher junction breakdown voltage and a higher threshold voltage without a reverse bias on the substrate due to an increase in the work function difference between the gate and substrate. Because of the lower concentration (i.e., higher resistivity) of the substrate, high frequency response is increased due to lower drain-source capacitance.

Field effect transistor structure and method of making same

Abstract: An improved field effect transistor structure which reduces a leakage phenomenon, termed the "sidewalk" effect, between the semiconductor substrate and a conductive silicon dioxide layer disposed over the substrate. The improvement comprises forming a layer of highly resistive silicon dioxide or silicon oxynitride, which is between the conductive oxide and the silicon nitride layer which forms a portion of the gate insulator for the field effect transistor.

Schottky gate field effect transistor

Abstract: A Schottky gate field effect transistor of the type comprising a silicon body of one conductivity type on an insulator substrate, and source, drain and gate electrodes is provided with a pn-junction located parallel to the surface of the substrate which produces a space charge zone occupying the zones of the silicon body close to the substrate surface, and a relatively thin active layer is located between the space charge zone and the gate electrode, the active layer having the same type conductivity as the silicon body.

Theoretical influence of surface states and bulk traps on thin film transistor characteristics

Abstract: It is shown that the theoretical derivation of drain current versus drain voltage characteristics of thin film transistors (TFT) is obtained, in the gradual channel approximation, by integration of the conduction electron charge versus gate voltage curve. The influence of bulk traps and surface states on these curves is evaluated quantitatively by using specific models. It is shown that at high donor concentrations, bulk traps have much more influence on TFT characteristics and even make it difficult to obtain good characteristics. At low donor concentrations, surface states have more influence but still allow good characteristics except at unusually high concentrations. Finally, the importance is shown of measurements of the channel conductance at low drain voltage as a function of the gate voltage for gaining insight in the physical parameters that determine TFT behavior.

Method of electrically isolating individual semiconductor circuits in a wafer

Abstract: A monolithic integrated circuit includes a vertical transistor having a low collector resistance with high current handling ability. The integrated circuit comprises a P type epitaxial layer grown on an N type substrate with both deep and shallow N type diffusions made into the P type layer. In the high current vertical transistor region with the deep N type diffusion, the deep diffusion penetrates the P layer to the N type substrate, whereas in the other transistor the shallow diffusion does not penetrate to the substrate. An N epitaxial layer is grown on the P type layer and thereafter normal processing techniques are used to form the base and emitter regions for the devices including the high current transistor which has its collector electrically coupled to the substrate.

Thin-film-transistor switching matrix for flat-panel displays

Abstract: A thin-film-transistor (TFT) switching array suitable as a module for matrix addressing of a wide variety of display media in flat-panel form has been designed and fabricated. The switching matrix and the display medium are on separate substrates. Solder bumps or other suitable contacts are used to connect each switch to the corresponding resolution element of the display. The matrix is a 20-line-per-inch 32 × 32-element array on a 1.6-in-square active area. A 5 × 7-dot character matrix is employed, and a single module will produce four lines of five characters each. The application of this array to an electroluminescent (EL) film display is described.

Slow states in InSb/SiOx thin film transistors

Abstract: An investigation of the slow decay in conductivity modulation observed in InSb/SiO x thin film field effect transistors has been carried out. The decay is ascribed to “slow” trapping states, with a characteristic trapping time of > 1 msec. These are postulated to be due to tunnelling of electrons from the semiconductor into traps in the insulator and this theoretical model is used to analyse the experimental results and to obtain a density, N t , of traps in the insulator. N t was found to be ∼ 10 20 cm −3 and the capture cross-section referred to the semiconductor/insulator interface was ∼ 10 −20 cm 2 . The traps were found to be filled to a depth of ∼ 20 A into the insulator.

Experimental realization of floating-gate-memory thin-film transistor

Abstract: CdSe thin-film nonvolatile memory transistors have been made using the concept of a double-insulator structure with a thin floating gate inserted at the interface of the two insulators. The thin floating gate enhanced the charging and charge-retention behaviors of the memory transistors. On/off conductance ratio of greater than 1000 has been achieved. Writing speed on the order of microseconds is possible.

Method of obtaining high temperature resistant assemblies comprising isolated silicon islands bonded to a substrate

Abstract: A method is described for obtaining high temperature resistant assemblies comprising isolated silicon islands bonded to a substrate in view of the manufacture of bipolar or MOS circuit element built-in devices. The flat surface of an initial wafer comprising a silicon layer wherein unisolated silicon islands are nested within a silicon oxide layer otherwise having a planar interface with the silicon layer is totally oxidized and coated with a thicker insulating layer at least part of which is comprised of silicon oxide up to an exposed surface, and a second substrate at least the surface of which is comprised of silicon oxide is bonded to the said exposed oxide surface by fusion of an intermediate phosphosilicate glass layer between said two oxide surfaces. Thereafter, the silicon material of the initial wafer is removed up to the said interface.

Complementary transistor structure having two epitaxial layers and method of manufacturing same

Abstract: A monolithic semiconductor device comprising at least two complementary transistors, in which the base zone of a first transistor and the collector zone of a second transistor are provided in a first epitaxial layer, while the emitter zone of the second transistor, the emitter zone of the first transistor and the base zone of the second transistor are provided in a second epitaxial layer. A separation groove is provided between the transistors in the second epitaxial layer.

High frequency, field-effect transistor

Abstract: A high frequency, Schottky barrier gate, field-effect transistor is provided with a substantially constant impedance over a broadband of frequencies. The transistor is comprised of a thin dielectric layer providing an effective dielectric constant at gate and drain contacts greater than √2. The dielectric layer is supported on the major surface of a conductor substrate, and is preferably 5 microns in thickness and has a dielectric constant greater than about 5. The transistor is also comprised of a thin semiconductor layer of less than about 2 microns in thickness at least at gate portions with an N-type concentration of between about 5 × 10 14 and 5 × 10 17 carriers/cm 3 . The gate contact of the transistor is an elongated Schottky barrier contact adjoining the semiconductor layer spaced between elongated source and drain contacts which make ohmic contact with the semiconductor layer. Means are also provided to maintain the source contact at substantially the same RF potential as the conductor substrate.

Manufacturing method for self-aligned mos transistor

Abstract: The method of manufacturing a self-aligned, metal gate n-channel MOS transistor includes the steps of depositing a layer of silicon dioxide on a p-type silicon surface, diffusing phosphorus into the silicon dioxide to a depth of about 1,000 A from the silicon surface in a region coextensive with source, drain and gate regions of the transistor, removing the phosphorus doped portion of the silicon dioxide from a region coextensive with the gate region, diffusing phosphorus contained in the remaining phosphorus doped region of silicon dioxide through the rest of the silicon dioxide layer to form n-type source and drain regions in the silicon surface and metalizing the transistor. The phosphorus is diffused to an easily controlled depth in the layer of silicon dioxide, and because the phosphorus converts the silicon dioxide to a phosphosilicate glass having a faster etch rate than silicon dioxide, it is easy to etch away the glass opposite the gate region without etching appreciably into the 1,000 A of silicon dioxide. The simultaneous definition of adjacent drain, gate and source boundary regions results in a self-aligned metal gate transistor.

Fabrication of a ferroelectric gate memory transistor

Abstract: Transistors were fabricated using a sputtered barium titanate dielectric for the gate insulator. The insulator shows two polarization states. It is possible to have normal field effect transistor characteristics in one state and the transistor turned off in the other state. These transistors may be useful in memory applications.

Bipolar HF transistor with mesa configuration - has two semiconductor regions of conductivity opposite to that of substrate

Abstract: The HF transistor has a substrate with a mesa portion of the same conductivity with adjacent surfaces. The substrate surface carries a passivating film, through extend base and emitter terminals. Inside the substrate is arranged a semiconductor region of opposite conductivity, surrounding the mesa part and forming with the substrate a pn-junction. This region has a given conductivity level and serves as a base contact region for the transistor. A second semiconductor region of opposite conductivity is provided in the mesa part in connection with the first semiconductor region, forming the transistor operating region. The second semiconductor region has a lower conductivity level and surrounds a region of first conductivity forming the transistor emitter.

Thin-film-transistor stability investigation

Abstract: : This program was undertaken to identify the key parameters required for stable operation of thin-film transistors (TFTs), to define the range of stable operation, and to assess TFT-device reliability and yield. Lead sulfide (PbS) and lead selenide semiconductors were found to produce stable TFFs (i.e., free from ionic-drift and carrier-trapping effects) in combination with aluminum oxide (Al2O3) as the gate dielectric, but lead telluride devices exhibited carrier trapping. Stable TFT operation was obtained with chromium, molybdenum, or tungsten source/drain electrodes, while aluminum, titanium, lead, and gold electrodes were not as satisfactory. Unsatisfactory devices were obtained with silicon dioxide as the gate insulator. Stable PbS TFT operation was demonstrated over the range from -196 to +125C.