Showing papers on "Thin-film transistor published in 1977"

Method of making a V-MOS field effect transistor for a dynamic memory cell having improved capacitance

Abstract: This disclosure relates to a method of making a V-MOS field effect transistor which does not require the extra steps of epitaxial growth in order to form the source area of the transistor. The formation of the source area is achieved by masking the silicon substrate, opening an aperture in the mask and then etching the silicon substrate in such a manner as to undercut the mask so that the mask provides a shield to subsequent ion implanting of the source area. Both P and N type dopants can be separately implanted with different energy levels so as to form an enhanced PN junction capacitance for the device. Such a field effect transistor can be achieved without the formation of a graded dopant concentration in the channel between the source and drain areas of the transistor and is provided with enhanced source capacitance.

Liquid crystal display unit of matrix type

Abstract: PURPOSE: To increase the characteristics and to simplify the manufacturing process, by using Te for the semiconductor layer of a thin film transistor, in a display unit sealing liquid crystal between the entirely transparent conductor and the substrate on which thin film transistor array is formed at each cross point of a plural number of gate wires and source wires orthogonal to the gate wires. COPYRIGHT: (C)1979,JPO&Japio

Method for making a bipolar transistor structure utilizing self-passivating diffusion sources

Abstract: A semiconductor structure, formed within a recessed oxide isolation region, includes a semiconductor substrate of a first conductivity type within which a collector of opposite conductivity type is formed below the surface of the substrate and extending in part to the surface of the substrate for ease of contact. A first layer of doped polycrystalline silicon or polysilicon is formed on a first portion of the surface of the substrate and in electrical contact with the substrate which acts as the base of a transistor. The first polysilicon layer is oxidized to form an outer insulating layer thereover. A second doped polysilicon layer is disposed over the outer insulating layer onto a second portion of the surface of the substrate so as to be spaced from the first portion by only the thickness of the outer insulating layer on the first polysilicon layer. The dopant in the second polysilicon layer is driven into the surface of the semiconductor substrate to form an emitter therein. Means, which may include a portion of the second polysilicon layer, are provided for electrically contacting the collector to thus form a completed compact bipolar transistor which has very high performance.

High display viewability provided by thin-film EL, black layer, and TFT drive

Abstract: This laboratory has recently developed low-voltage thin-film electroluminescent (EL) emitters combining the brightness maintenance characteristics first reported by the Sharp Corporation in 1974 [1] with a new light-absorbing black layer, reminiscent of those introduced by Sigmatron [2],[3]. This combination, together with a new thin-film-EL active-matrix TFT switch configuration, has resulted in highly efficient high-ambient viewability. In addition, brief mention is made of a new approach to display addressing utilizing our newly developed thin-film bucket-brigade device [4].

Method for adjusting the leakage current of silicon-on-sapphire insulated gate field effect transistors

Abstract: A method for adjusting the leakage current of insulated gate field effect transistors comprised of silicon mesas epitaxially formed on a sapphire substrate, wherein the leakage current of a P channel transistor is increased by preoxidizing the silicon prior to standard processing and/or wherein the leakage current is decreased by annealing the silicon in a reducing atmosphere in addition to standard processing steps. The leakage current of an N channel transistor is reduced by preoxidizing the silicon of the transistor prior to forming the transistor and/or is increased by annealing in a reducing atmosphere in addition to the steps necessary for forming the transistor.

Complementary MOSFET device

Abstract: A CMOS FET device having a P well layer diffused in an N type semiconductor substrate, a P channel MOS transistor formed on the N type semiconductor substrate, and an N channel MOS transistor provided in the P well layer, wherein the source of the P channel MOS transistor is made to have the same potential as the N type semiconductor substrate and for the source of the N channel MOS transistor is made to have the same potential as the P well layer, thereby suppressing the operation of a parasitic bipolar transistor whose base is constituted by the N type semiconductor substrate and/or a parasitic bipolar transistor whose base is formed of the P well layer.

Method of manufacturing Si gate MOS integrated circuit

Abstract: An IC manufacturing method that eliminates the need for separate pad area and allows polysilicon MOS transistor gates to be contacted directly. Present silicon gate process techniques are utilized up to and including the formation of the gate oxide layer, with areas etched through to the substrate. Then polysilicon and silicon nitride are deposited preferably in the same deposition equipment. The polysilicon interconnect and gate pattern is selectively etched for both silicon nitride and polysilicon. Next, the gate oxide exposed by the previous step is removed and phosphorous is diffused into the exposed silicon substrate surfaces. The initial nitride thickness is chosen such that after phosphorous predeposition and subsequent removal of phosphorous glass, a thin layer of silicon nitride is left. A silicon oxide protective layer is then grown over the exposed silicon substrate surfaces. The remaining silicon nitride is removed and a phosphosilicate glass is deposited over the entire surface. Contact cuts are made through the phosphosilicate glass through which metal contacts are established.

Metal base transistor with thin film amorphous semiconductors

Abstract: A transistor having a continuously variable modulation characteristic is provided by a structure of two semiconductive films with at least one of them composed of amorphous material sandwiching a thin metallic film base. The transfer characteristics of the device are continuous rather than bistable. When both semiconductive films are amorphous, the transistor can be deposited upon inexpensive crystalline or noncrystalline substrates.

Single transistor memory cell employing an amorphous semiconductor threshold device

Abstract: A single transistor memory cell wherein the memory cell is provided by the base collector capacitance of the transistor in the integrated circuit chip. Mounted on top the chip in electrical contact with the base of the transistor is an amorphous semiconductor threshold device employing a tellurium based chalcogenide such that when a charge is applied to the terminal of the device opposite the transistor base, the device will be switched to a high conducting state until such time as the base collector capacitance has been charged and then the threshold device will be switched to a low-conducting state. Specifically, the amorphous threshold device employs Ge 15 Te 81 Sb 2 S 2 .

Monolithic combination of two complementary bipolar transistors

Abstract: In the production of integrated I 2 L-circuits, a lateral transistor and a vertical transistor are generated next to one another on the surface of a monocrystalline semiconductor body. Thereby, it is seen to that the base zone of the vertical transistor coincides with the collector zone of the lateral transistor and the base zone of the lateral transistor coincides with the emitter zone of the vertical transistor. Further, it is known to provide at least one collector zone of monocrystalline semiconductor material belonging to the vertical transistor and marked off from the base zone of this transistor by a pn-junction and to provide a Schottky contact as collector electrode. The invention makes provisions for applying a polycrystalline layer of the same semiconductor material and the doping of the collector zone on the surface of the monocrystalline collector zone and then making this the carrier of the collector electrode or collector electrodes, respectively. In addition to reducing the effort otherwise required, an increase of the component density as well as a series of structural improvements can be attained.

CCD output circuit using thin film transistor

Abstract: Compact, low-capacitance output circuit for charge coupled device (CCD). The circuit includes a semiconductor electrode which is doped at opposite edges thereof to form the source and drain regions, respectively, of a thin film transistor. The conduction channel of the transistor is the region of the semiconductor electrode between the source and drain regions. The gate electrode of the transistor is the region of the substrate adjacent to the conduction channel and the input signals comprise the packets of charge shifted to this substrate region by the multiple phase voltages which operate the CCD.

MNOS Memory transistor

Abstract: A memory transistor includes a body of semiconductor material having therein a channel region of one conductivity type and source and drain regions of the opposite conductivity type. A channel insulation is on the surface of the semiconductor body and extends over the channel region. The channel insulation includes a first layer of silicon dioxide directly on the surface of the semiconductor body and a layer of silicon nitride on the silicon dioxide layer. A gate of conductive polycrystalline silicon is preferable provided on the channel insulation. The channel of the transistor is sufficiently narrow so that electrons can be avalanched into the interface between the silicon nitride layer and the silicon dioxide layer completely across the full width of the channel where the electrons can be stored.

Schottky-transistor-logic

Abstract: A Schottky-transistor-logic arrangement is disclosed which comprises a highly doped semiconductor substrate of one conductivity type. An epitaxial layer of the same conductivity type is formed on the substrate. A deep-implanted doped zone of the other conductivity type is located in the epitaxial layer in a plane spaced below the outer surface of said epitaxial layer and lying substantially parallel thereto. A load transistor and an output transistor are formed by constructing the arrangement so that the buried layer provides the base of the load transistor and the emitter of the output transistor. The emitter of the load transistor is provided by a portion of the epitaxial layer which lies below the deep-implanted doped zone. The collector of the load transistor and the base of the output transistor are provided by the portion of the epitaxial layer which lies above the deep-implanted zone. A Schottky electrode on the outer surface of the epitaxial layer provides the collector of the output transistor. A plurality of Schottky diodes are also formed in a portion of the epitaxial layer which possess a lower Schottky barrier than the Schottky electrode of the output transistor.

Radiation hardened drain-source protected mnos transistor

Abstract: A radiation hardened drain-source protected MNOS transistor is disclosed. A layer of silicon oxide overlies the channel and the junctions formed by the intersections of the drain and source regions with the channel. Drain and source protection is provided by relatively thick portions of the silicon oxide layer which overlie the junctions formed by the drain and source regions and the channel. The portion of the silicon oxide layer overlying the central section of the channel is thinner than the remainder of this layer. A silicon nitride layer and an electrically conductive layer forming the gate electrode overlie the thinner portion of the silicon oxide layer to complete the MNOS transistor. The conductive layer forming gate electrode of the transistor is in electrical contact with both the silicon nitride and the silicon oxide layers. This provides a convenient method for electrons generated at the interface of the silicon and the silicon-oxide layer during irradiation to be transported to the gate, thereby preventing charge build-up in the silicon oxide which causes shifts in the characteristics of the transistor.

MIS-type field effect transistor and method of producing the same

Abstract: An MIS-type field effect transistor, comprising a semiconductor substrate having a projection, source and drain regions formed in the substrate with the projection intervening therebetween, and a gate structure formed on the surface of the projection. The transistor is advantageous for enhancing the integration degree of an integrated circuit.

Large Area Masking Techniques For Thin Film Transistor Arrays

Abstract: Thin Film Transistor technology permits the generation. af extremely large area active networks, which currently find their principal application in the Large Scale Integration of solid state, flat panel displays. This paper reviews some of the problems encountered in carrying a design for a large area active matrix through the stages of layout, pattern-generation and stencil mask preparation, the latter being used in the final fabrication of the thin film circuits. An alternative approach, used in thl laboratory, which has great versatility, and which has yielded the largest circuits so far generated (36 in), will also be touched upon.

Thin Film Transistor Addressed Display Device.

Abstract: : This is the final report on Contract DAAB07-72-C-0061; the objective of which was an examination of the feasibility of fabricating a multielement dot-matrix display using electroluminescent output and an integrated thin film transistor addressing array. The concepts have been validated, good quality functional displays were made and delivered to the US Army. Three formats were examined: 6 in. x 6 in., 20 lpi (12,000 elements), 6 in. x 6 in., 30 lpi (25,000 elements) and 6 in. x 3 in. approximately 30 lpi (17,000 elements); the latter display was designed to be integrated into a US Army field system, the TACFIRE forward observer terminal, and the Digital Message Device. Specimen displays are now being fitted into that device for field trials. The TFT arrays met all the expectations of this program. Devices in the array could switch 300 Vpp power, they demonstrated excellent uniformities which allowed the presentation of good grey scale imagery as well as alphanumerics. Devices with extremely low leakage currents ( 1 nA) were achieved. Active matrix arrays containing 90,000 devices (60,000 TFTs and 30,000 capacitors) were made containing only a small number of imperfections, which did not interfere with the operation of the panel. The resulting displays clearly demonstrated the point that the use of the TFT addressing array allows the selection of an optimal display media.

A simple boundary condition at semiconductor-insulating substrate interface of a TFT☆

Abstract: Using the Wexler, Green and Miles (WGM) procedure, a criterion is given for neglecting the electric field in insulating substrate of a Thin Film Transistor in presence of surface states. It is shown that this is fulfilled for a real TFT.

Mos type field effect transistor

Abstract: A MOS type field effect transistor has an electrode, which is in the neighborhood of, but not in contact with, the drain diffusion region and is electrically connected with the surface portion of the semiconductor substrate in which the MOS type field effect transistor is formed, and whose potential is held at the rear surface potential of the semiconductor substrate, i. e., the substrate bias potential.