Showing papers on "Thin-film transistor published in 1978"

Cadmium selenide thin‐film transistors

Abstract: Vacuum‐deposited CdSe thin‐film transistors (TFT’s) with reproducible good stability, performance, uniformity, and yield were made using sputtered SiO2 gate insulator, Cr source–drain (s–d) electrodes, and postdeposition annealing in N2. These materials and procedures permit the use of multiple pumpdown fabrication methods with no loss in ac characteristics and little sacrifice in dc stability. Promising results were obtained using photolithography (PL) to delineate s–d electrodes, further simplifying fabrication. The dc instability is electron‐trapping type and the drain current decay exhibits a logarithmic time dependence. The slope of this decay curve is used as a parameter to describe device stability and its dependence on the fabrication methods studied: M=0.03–0.06 for one‐pumpdown devices, 0.05–0.08 for multiple pumpdown TFT’s, and 0.1–0.2 for TFT’s with PL‐delineated s–d electrodes. Preliminary reliability studies show that suitably encapsulated TFT’s have long time stability comparable to the good short time stability observed for fresh devices, indicating the absence of built‐in failure mechanisms and the capability for a satisfactory operating life.

Method for forming oxide isolated integrated injection logic semiconductor structures having minimal encroachment utilizing special masking techniques

Abstract: A process for fabricating integrated injection logic structures including both vertical and lateral bipolar transistors in oxide isolated pockets of silicon includes the steps of forming a patterned composite silicon nitride-silicon dioxide layer to serve as a transistor emitter and self-aligned base mask, and introducing desired impurities to form the lateral transistor emitter and collector. The mask is partially removed and additional impurities introduced to form the vertical transistor base and vertical transistor collector. The process does not require the use of vapor deposited silicon dioxide to pattern the wafer surface, and therefore reduces pinhole defects and the encroachment of the field oxidation on the epitaxial silicon pocket in which devices are formed. The process also results in a flatter topography to allow more uniform and reliable metal interconnections.

Method for forming semiconductor structure with improved isolation between two layers of polycrystalline silicon

Abstract: In a field effect device such as a charge coupled device or field effect transistor in which at least two levels of polycrystalline silicon conductors are used; these two levels of polycrystalline silicon are isolated from one another with a dielectric layer. Disclosed is a composite dielectric layer formed either by in situ oxidation of the first polycrystalline silicon layer plus chemical vapor deposited silicon dioxide or, in the alternative, the composite dielectric layer is formed by a phosphosilicate glass layer with thermal reoxidation of the first polycrystalline silicon layer.

I2 L Integrated circuit and process of fabrication

Abstract: In a complementary pair of bipolar transistors, one vertical and one lateral, the vertical transistor includes a heavily doped buried emitter, lightly doped buried graded base and a heavily doped surface collector and the lateral transistor includes a lightly doped substrate base and heavily doped emitter and collector. The lateral transistor's collector isolates the lateral transistor's base from the vertical transistor's collector. This integrated circuit approach includes the I 2 L structure of the present invention and T 2 L devices. The I 2 L transistors are in dielectrically isolated regions with the vertical transistors emitter being connected to the polycrystalline support through a vertical opening in the dielectric isolation. The process of fabrication includes forming the vertical transistor's base by diffusion into a first surface of a substrate of opposite conductivity type, forming the vertical transistor's emitter epitaxially on the first surface and forming the vertical transistor's collector and the lateral transistor's emitter and collector by diffusion into the opposite surface of the substrate. The lateral transistor's collector diffusion is from the opposite surface down to the vertical transistor's base and separates the vertical transistor 's collector from the portion of the substrate which is the lateral transistor's base. For integrated circuits, the process includes dividing the substrate into a plurality of dielectrically insulated regions after forming the epitaxial emitter and depositing a polycrystalline support.

Semiconductor device having complementary transistor structures and method of manufacturing same

Abstract: A semiconductor device includes a body comprising two planar complementary transistor structures preferably but not exclusively with dielectric insulation. Both complementary transistor structures comprise parts of two epitaxial layers of opposite conductivity types present one on top of the other, the first layer forming the base zone of the first transistor and the second layer forming the collector zone of the second transistor, the emitter zone of the first transistor and the base zone of the second transistor being formed by parts of the second layer.

Method of producing a metal-semiconductor field-effect transistor

Abstract: A metal-semiconductor field-effect transistor is formed by providing a blanket layer of the same conductivity type as the semiconductor body, with field oxide subsequently being grown, and with a region of opposite conductivity type being formed to extend partially under the field oxide, the initial blanket layer acting as the field implant region of the field-effect transistor.

CMOS FET device with abnormal current flow prevention

Abstract: A CMOS FET device which comprises an N type semiconductor substrate; a P type well layer formed in the N type semiconductor substrate; a p-channel type MOS transistor provided in the N type semiconductor substrate; an n-channel type MOS transistor formed in the P type well layer; and a noise-absorbing capacitor provided at the input or output terminal of the MOS transistor or at a power supply section.

Matrix-type liquid crystal display unit

Abstract: PURPOSE: To prevent the deterioration of TFT caused by the liquid crystal by providing the insulator film on the surface of TFT. CONSTITUTION: Substrate 1 contains plural units of the gate wire and the source wire along with the thin-film transistor (TFT) array using Te for the semiconductor layer formed at each intersection. And opposite substrate 11 is provided at the position opposing to substrate 1 with transparent conducting film 10 formed. Then liquid crystal component 12 is put between the both substrate, and TFT is protected by insulator film 13. COPYRIGHT: (C)1979,JPO&Japio

A channel conductance measuring technique for determining the interface properties of a SiOInSb thin film transistor

Abstract: A small-signal method to determine the interface properties of a thin film transistor is described for the frequency range of 10 Hz to 100 KHz. By measuring the in-phase and out-of-phase change of the channel conductance due to a small ac gate voltage, one can identify the possible nature of the surface states and their time constants. This method has been applied to a SiO-InSb thin film transistor and the results obtained indicates that the interface states are, most likely, located in the SiO, and that these states can follow an ac signal of 7.6 KHz.

Semiconductor gas sensor

Abstract: A metal-oxide-semiconductor transistor gas sensor including a gate oxide film of a dielectric material having a permittivity of more than about ten between a substrate and a gate is provided. The existence of a particular gas is detected by the change in threshold voltage of the transistor.

Thin-Film Field-Effect Transistor

Abstract: Coplanar electrode thin-film transistor, fabricated by vacuum evaporation of aluminium and cadmium selenide is described. The drain characteristics of one of the fabricated samples are presented. The transconductance and gain-bandwidth product of the device are approximately 27 micromhos and 3 kHz respectively. The drain characteristics are observed to be sensitive to the incident light. The hysteresis loops observed in the characteristics can be due to positive alkali-ion drifts and traps in the insulator and insulator-semiconductor interface.