Showing papers on "Thin-film transistor published in 1982"

Conductivity behavior in polycrystalline semiconductor thin film transistors

Abstract: CdSe thin film transistor (TFT) structures which have been ion implanted with 50 keV 52Cr, 50 keV 27Al, or 15 keV 11B have a very steeply rising conductivity above some threshold dose and exhibit modulated transistor characteristics over certain ranges of implant dose, even though there is no thermal annealing during or after ion implantation. These results are interpreted using a model based on grain boundary trapping theory. The dependence of leakage current on implant dose, and of drain current (at a fixed dose) on gate voltage are described very well by this model, when the drain voltage is very small. Using this simple model, the important parameters of the polycrystalline CdSe film, namely the trap density per unit area in the grain boundary, the donor density, grain size, and electron mobility can be deduced. The effect of thermal annealing on implanted and unimplanted CdSe TFT’s has also been studied and the model appears to give a general description of the conductivity behavior in polycrystallin...

Manufacture of thin-film transistor

Abstract: PURPOSE:To improve the characteristics of a transistor to a large extent, by depositing a silicon dioxide film on a silicon thin film from the outside, thereafter performing thermal oxidation, thereby making the thickness of the silicon thin film further thin. CONSTITUTION:A silicon thin film 302 is deposited on an n insulating substrate 301. The film thickness is made to be, e.g. t0=500Angstrom . Then, a silicon dioxide film 303 is deposited on the entire surface. The film thickness is made to be, e.g. toxo=1,300Angstrom . In this case, the silicon dioxide film can be formed by any method if the film is not formed by oxidizing the silicon thin film but is directly depsited from the outside. Thermal oxidation treatment is performed, and a film thickness 304 of the silicon dioxide film on the silicon thin fil is grown. The final film thickness of the silicon thin film becomes t1=400Angstrom by the thermal oxidation. After a gate electrode 305 has been formed, impurities are introduced into the silicon thin film, and a source region 306 and a drain region 307 are formed. Then, an interlayer insulating film 308 is deposited, contact holes are provided, and a source electrode 309 and a drain electrode 310 are formed.

Dual-gate a—Si:H thin film transistors

Abstract: Dual-gate accumulation mode thin film transistors have been fabricated for the first time in a-Si:H on bulk glass substrates. The devices display exceptionally high performance, as compared to previously reported single-gate a-Si:H transistors. For a channel length of 10 µm and width of 168 µm, drain currents in the range of 5-10 µA were obtained for gate biases of 15 V in both of the two conducting channels induced in the a-Si:H layer. The drain current of the TFT operating in the dual-gate mode was found to be larger than the arithmetic sum of the drain currents through the two individual channels obtained from single-mode operation. A significant difference in dc stability between the two channels was observed. The use of the dual-gate TFT as a diagnostic structure for studying interface properties and contact effects has been demonstrated.

Thin film transistors

Abstract: A thin film transistor has a semiconductor layer, an insulating layer and source, drain and gate electrodes. The improvement comprises creating an enhanced conductivity layer in the semiconductor by ion implantation or diffusion on phased deposition. The benefits of the enhanced conductivity layer are that transistor action is obtained without the conventional annealing step and D.C. stability is much improved.

Manufacture of thin film field effect transistor

Abstract: PURPOSE:To improve the operating speed of a TFT circuit and to enable to microminiaturize and integrate an element by self-aligning a gate electrode with source and drain electrodes. CONSTITUTION:A gate electrode 12 is formed by sputtering and patterning of Al on a transparent glass substrate 11, and an oxidized silicon film 13 is then formed by sputtering as a transparent gate insulating film, an indium or tin oxidized film 14a is further accumulated. Subsequently, an amorphous silicon film 14b added with P (phosphorus) is accumulated by the glow discharge decomposition of SiH4 and PH3. Then, an negative type resist 15 is coated, ultraviolet ray is exposed with the electrode 12 as a mask from the back surface of the substrate 11, a development is performed, and the resist is patterned. Then, an amorphous silicon film added with P and indium, tin oxidized film are etched to form source 141 and drain 142 electrodes which are self-aligned with the gate electrode. An amorphous silicon film 16 is then accumulated by the flow discharge decomposition of the SiH2, formed in the prescribed pattern by PEP technique. Wirings out of the source and drain regions of an element are eventually formed in the desired pattern, thereby completing a TFT.

Thin-film transistors on a-Si:H

Abstract: A comparison has been made of the characteristics of nitride and oxide MOSFET's fabricated with thin films of amorphous silicon. Published data indicate that Si 3 N 4 -Si:H thin film devices are superior to the oxide devices. Accumulation-mode MOSFET's were fabricated in which the drain current arises from electric-field induced accumulation of electrons (majority carriers) at the a-Si:H-insulator interface. Hydrogenated amorphous silicon layers were deposited at 230°C by glow-discharge plasma decomposition in silane. The deposition conditions were found to be critical, and in the present study the films were grown on an electrically grounded substrate with RF power of 1 W applied to the counter electrode. The a-Si:H was deposited onto silicon nitride and silicon dioxide layers of 100-500-nm thickness, and thin-film transistors were fabricated with the inverted MOS configuration. Devices were tested with on/off drain current ratios greater than 104for a gate voltage swing of 0 to 12 V and drain-current saturation for source-drain voltages of less than 12 V. The properties of MOSFET's on a-Si:H are discussed with a comparison of the silicon-nitride-a-Si: H and silicon-dioxide-a-Si:H interfaces and an evaluation of doped active layers. The transistors on silicon dioxide are as good as any reported to date on silicon nitride.

Darlington transistor circuit

Abstract: A three-stage Darlington transistor circuit having a power transistor (T 3 ), a driver transistor (T 2 ) and an initial transistor (T 1 ) is provided The collectors of these three transistors are connected with one another, while the emitter of the driver transistor (T 2 ) is connected to the base of the power transistor (T 3 ), and the emitter of the initial transistor (T 1 ) is connected to the base of the driver transistor (T 2 ) Connected to the base of the driver transistor (T 2 ) is a series circuit comprising a first resistor (R 1 ), which is connected directly to this base, and a Zener diode (ZD), the anode of the Zener diode being connected with the resistor (R 1 ); and a second resistor (R 2 ); the second resistor (R 2 ) is connected in parallel to the emitter-base path of the driver transistor (T 2 ) Upon the attainment of a predetermined voltage at the cathode of the Zener diode (ZD), the driver transistor (T 2 ) and the power transistor (T 3 ) are switched ON The temperature dependency of this switch-on voltage can be adjusted by varying the resistance ratio of these two resistors (R 1 , R 2 )

A self-alignment process for amorphous silicon thin film transistors

Abstract: A new method of fabricating amorphous Si thin film transistors (a-Si TFT's) has been developed. This method uses the self-alignment process, which also includes the successive deposition of gate insulator and active amorphous Si layers in one-pumpdown time in an RF glow discharge apparatus. This method greatly simplifies the fabrication process and results in stable device performance. The practicability of this method was confirmed by experimentally fabricated devices.

Stacked MOS transistor

Abstract: In a stacked metal-oxide-semiconductor (SMOS) transistor, the transistor source, drain and channel each have a lower part (18, 20, 22) formed in a silicon substrate (12) and an upper part (30, 32, 26) composed of recrystallized polysilicon. The device gate (24) is located between the upper and lower channel parts. By vertically integrating a MOS transistor, performance limitations imposed by the direct scaling approach to device miniaturization are avoided.

Method for making thin-film transistors

Abstract: A method for making a thin-film transistor wherein a gate insulating layer is formed by anodizing two oxide layers on the substrate and then etching the assembly to completely remove the uppermost one of these layers to leave the lowermost layer so as to serve as the gate insulating layer.

Single-crystal silicon transistors in laser-crystallized thin films on bulk glass

Abstract: High-performance thin-film transistors (TFT) have been fabricated in single-crystal silicon thin films on bulk fused silica. Deposited films of polycrystalline silicon were patterned to control nucleation and growth of single-crystal material in pre-selected areas and encapsulated with a dielectric layer (e.g., SiO 2 ) in preparation for laser crystallization. Patterning also minimized microcracking during crystallization. The patterned silicon layer was crystallized with a scanning CO 2 laser, which produced islands with preferred crystal orientation. The single crystallinity of the islands was established with transmission electron microscopy after transistor evaluation. The silicon islands were processed with conventional microelectronic techniques to form metal-oxide-semiconductor-field-effect transistors operating in the n-channel enhancement mode. The devices display exceptional electrical characteristics with "low-field" channel mobilities > 1000 cm2/V sec and leakage currents 2 - laser processing of silicon films a viable and versatile basis for a silicon-on-insulator technology.

High-voltage silicon thin film transistor on quartz

Abstract: A high voltage enhancement-type thin film transistor (TFT) has been fabricated on quartz in layers of laser-recrystallized polysilicon. The fabrication details and TFT characteristics are described.

Active matrix substrate

Abstract: PURPOSE:To obtain an inexpensive active matrix substrate which uses thin film transistors having sufficiently large ON current, a sufficiently small OFF current and excellent reproducibility and reliability by employing a true polycrystalline silicon thin film on a channel region and a true polycrystalline silicon thermally oxidized film on a gate insulated film. CONSTITUTION:After a true polycrystalline silicon 9 is accumulated on an insulating substrate 8, a thermal oxidation is performed, thereby forming a gate insulated film 12. Then, a gate electrode 13 and a common electrode 17 of a condenser are formed. These two electrodes may be formed of the same conductive material simultaneously. Subsequently, after an impurity is doped to form source and drain regions 10, 11, an interlayer insulated film 14 is accumulated, and a contacting hole is opened. The doping of the impurity to the source and drain regions is performed by thermal diffusion or ion implantation. Subsequently, a gate line 15 is formed, and a drive electrode 16 is then formed to complete it. In this manner, the true polycrystalline silicon thin film is used to increase the ON current in the channel region, and the OFF current is reduced. Further, the impurity is not doped in a true shape, thereby minimizing the OFF current.

Planar-type field-effect transistor having metallized-well electrodes and a method of fabrication of said transistor

Abstract: A field-effect transistor having a gate consisting of a metallic plane projecting metallized wells of less than one micron in diameter through the channel layer downwards to the semiconductor substrate. They are formed by ion-beam etching. Metallization is performed by cathodic sputtering of a substance which forms a Schottky contact with the semiconductor. The wells are spaced at intervals of less than one micron so as to form a row and are joined together by means of a gate electrode.

Amorphous-silicon TFT array for LCD addressing

Abstract: A 64×64 element matrix array of amorphous-silicon thin-film transistors has been fabricated on a glass substrate. Using a drive scheme to simulate a 500-line display, an output voltage of 8.5 V RMS is obtained. This large output voltage is sufficient for an alphanumeric liquid-crystal display using the dyed cholesteric-nematic phase-change effect. The driving voltages for the array are compatible with LOCMOS (18 V) peripheral circuitry.

Manufacture of thin film transistor

Abstract: PURPOSE:To accelerate the operating speed of a transistor by coating a negative type resistor film and forming source and drain regions at gate electrodes by the exposure from the surface of a substrate, thereby micromiaturizing an element CONSTITUTION:After an opaque metal gate electrode 42 is formed on a transparent insulating substrate 41, a gate insulating film 43 and a P type thin semiconductor film 44 are sequentially accumulated on the overall surface Thereafter, an insulating film 45 is accumulated, a negative type resist film 46 is coated on the film, the entire surface is exposed by a visible light 47 from the back surface of a substrate 41, patterned, the film 45 is etched, a resist pattern self-aligned with the electrode 42 is formed, an ions 48 are implanted to form an n type source region 49 and drain region 50 Then, the films 46, 45 are removed, an insulating film 51 is formed on the overall surface, contacting holes are opened at the film, source and drain electrodes 52, 53 are arranged, thereby completing an n-channel thin film transistor

Self-aligned metal field effect transistor integrated circuit

Abstract: A self-aligned metal field effect transistor is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistor integrated circuits. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar.

Manufacture of self-alignment thin film transistor

Abstract: PURPOSE:To improve high frequency characteristics of a transistor by forming by self-aligning method source and drain electrodes, treating and cleaning by hydrogen plasma the all boundary in which the source and drain electrodes are contacted with amorphous silicon. CONSTITUTION:After a gate electrode 16 is formed on a glass substrate 15, a gate insulating film 17 of SiO2 is formed by a plasma CVD method in a thin film forming apparatus, and an amorphous silicon film 18 is continuously formed in Si4 gas atmosphere without breaking vacuum state. A positive resist 19 is then coated on the film 18, with the electrode 16 as a mask it is exposed from the substrate side to develop it, thereby allowing only the resist 19 to remain on the gate electrode. Then, it is treated with hydrogen plasma at 23, thereby cleaning the surface of the film 18. After aluminum is deposited, a source electrode 20 and a drain electrode 21 are formed by lifting-off. The source and drain electrodes 20, 21 and the chanel region of the film 18 are cleaned, and an amorphous silicon film 22 is formed.

Direct observation of grain boundary effects in polycrystalline silicon thin‐film transistors

Abstract: We have applied charge collection scanning electron microscopy to the gate capacitor of n‐channel thin‐film transistors that were fabricated in laser recrystallized polycrystalline silicon. The action of grain boundaries as impediments to channel current flow and as fast diffusion paths for source and drain dopants is directly observed.

Amorphous-silicon silicon-nitride field-effect transistors

Abstract: n-channel and p-channel amorphous-silicon field-effect transistors have been fabricated on a glassy substrate using undoped and impurity-doped a-Si films as the semiconductor and silicon nitride deposited from an SiH4-N2 mixture as the gate insulator A change in the source-drain conductance of greater than four orders of magnitude is realised by changing the gate potential from 0 to 5 V

Thin-film transistor

Abstract: PURPOSE: To obtain an excellent TFT by a film having superior mass productivity and high quality by bringing a gas material containing deposit-film constituent atoms and a gassy halogen group oxidizer into contact, forming a plurality of precursors under the state of excitation and shaping the film, using the precursors as supply sources CONSTITUTION: One kind of Si n H 2n+2 (n=1∼8), SiH 3 , SiH(SiH 3 ), Ge m H 2m+2 (m =1∼5), etc or a mixture is used as a material, halogen gas such as F 2 and the oxidizer of F, etc under a nascent state are introduced into a reaction space at a desired flow rate and supply pressure together with a material gas and a plural kind of precursors under the state of excitation are shaped, an energy level is transferred to a low energy level, accompanied by light emission, and a semiconductor film 233 having uniform excellent physical properties is deposited equally on a conductive substrate 234 The flow ratio of the mate rial and the oxidizer is brought to 1/5∼50/1 and film-formation space pressure to 005∼10Torr, and a substrate temperature is selected properly, thus acquiring an amorphous film and a polycrystalline film According to the film formation method, layers, such as amorphous Si 233, an amorphous P high-concentration addition layer 232, an SiO 2 layer 231 are shaped, thus forming a TFT COPYRIGHT: (C)1987,JPO&Japio

Method of forming thin film transistors

Abstract: In the formation of a thin film transistor, integrity of the semiconductor-insulator and semiconductor-conductor interfaces is preserved by depositing layers of insulator (13, 33), semiconductor (15, 35), and conductor (17, 37) in successive sequence under continuous vacuum. The method minimizes contamination exposure of the critical interfaces between semiconductor and gate insulator and semiconductor and source-drain contacts of a thin film transistor.

Two stage etching process for through the substrate contacts

Abstract: Electrical interconnection paths or vias are provided through relatively thick type III/V semiconductive substrates, such as gallium arsenide, to permit through the substrate electrical interconnection of planar transistor devices. The vias are etched in a two-step process which ensures that the via lateral dimensions are less than the transistor contacts with which they are aligned. The first step comprises selectively thinning the thick substrate from the back surface over an area which encompasses the transistor array formed in the front surface of the substrate. The second step is to etch the individual vias through this prior thinned substrate at areas aligned with the transistor contacts.

Thin-film transistor

Abstract: PURPOSE:To decrease the variation of the characteristics of the thin-film FET even at the time of optical irradiation by conducting treatment, which increases the center of recombination of optical carriers and the density of a trap, to sections except an active layer of a Si thin-film. CONSTITUTION:When the poly Si thin-film 2 is formed onto a substrate 1, and irradiated by a N2 laser 22, intensity is properly controlled and pulsed light is given, the several hundred Angstrom thickness of the surface at the substrate 1 side of the thin-film 2 is melted, and recrystallized. Cooling is fast because pulse width is within 100n sec., crystals recrystallized have small grain size and many defects, and the centers of recombination of the optical carriers and conditions forming the traps are shaped to the surface layer in large numbers. A source 9 and a drain 10 are formed onto the Si layer 2 sufficiently shallowly according to a predeterimined method, and the FET is completed. According to this constitution, since the centers of recombination of the carriers and the traps are partially distributed to the surface layer at the substrate side in the FET, the life of the optical carriers generated through optical irradiation from the substrate side decreases remarkably, and the variation of the characteristics of the FET is largely inhibited.

Process for producing thin-film transistors on an insulating substrate

Abstract: Process for the production of thin-film transistors on an insulating substrate, wherein it comprises the following stages: 1. deposition on an insulating substrate of a coating of a metal able to form a silicide in contact with a silicon, 2. photoengraving of the first metal coating to define the sources, drains and channels for the future transistors and various connections between the transistors, 3. deposition of a silicon coating by reactive gaseous phase plasma, which leads to the appearance of a silicide coating in contact with the metal of the photoengraved coating, 4. deposition of a silica coating by reactive gaseous phase plasma, 5. deposition of a conductive coating by reactive gaseous phase plasma, 6. photoengraving of the conductive coating-silica coating-silicon coating system, without etching the silicide covering the photoengraved metal coating. Application to the production of large-area electronic components used e.g. in the production of flat display screens and the like.

Thin-film transistor and method of manufacture therefor

Abstract: A method for manufacturing thin-film transistor (74) comprises steps of sequentially forming in laminar state a gate film (42), an insulating film (44) and a conductive film having a transparent electrode film (60) and an amorphous silicon film (62) added with an impurity thereto on the top surface of glass substrate or layer (40); irradiating ultraviolet ray (50) from the bottom surface side of the substrate (40) to expose negative photoresist film (64) on said conductive film (60, 62) and to etch the same; and forming an amorphous semiconductive film (72) on the structure. In this manner, source and drain electrodes (68, 70) are respectively self-aligned with the gate electrode (42) and contacted therewith through a semiconductive film (72) and a low resistive and semiconductive film (62a).

Method of making integrated circuits comprising dielectric isolation regions

Abstract: A method of reducing lateral field oxidation in the vicinity of the active regions of a silicon substrate in which integrated circuit elements are to be formed is described. The method utilizes a first thin layer of silicon dioxide in contact with the active region of the substrate and a second thick layer of silicon nitride overlying the thin layer of silicon dioxide. The thin layer of silicon dioxide is provided with peripheral portions constituted of a silicon oxynitride.

Thin film transistor for transmission type display panel and manufacture thereof

Abstract: PURPOSE:To facilitate the formation of an FET having good characteristics and good reliability by laminating a transparent electrode and a metal on a transparent insulating substrate and forming the two-layer electrode at the connecting part of source and drain electrodes to a semiconductor layer CONSTITUTION:An oxidized In layer 21 and a Cr layer 22 are, for example, laminated on the overall surface of a glass substrate 1, and with a resist 23 as a mask the layers 22, 23 are sequentially selectively etched with exclusively used etchants Subsequently, a semiconductor layer 3 of CdSe or the like and a gate insulating film 4 are laminated, a gate film 4 is patterned as a mask, and the layer 3 of the prescribed configuration is retained only in the FET Then, an aluminum layer 24 is covered on the overall surface, a resist mask 25 is formed to etch the aluminum, and a gate electrode 5 is formed With the film 4 as a mask the exposed film 22 is then etched, and a Cr electrode 11 is retained at the part which is contacted with the layer 3 Since the metallic electrode functions as the source and drain electrodes of the FET, the characteristics of the FET can be improved Further, the step of manufacturing the FET can be facilitated

Manufacture of thin film transistor

Abstract: PURPOSE:To improve characteristics of an amorphous silicon thin film transistor for a liquid crystal display element and a throughput by a high speed formed film of amorphous silicon by forming the amorphous silicon film of a boundary to a gate insulating film under conditions of obtaining a film having excellent characteristics at a low speed, and forming the other part at a high speed. CONSTITUTION:The method for manufacturing a thin film transistor comprises the steps of placing glass board 6 on which a source electrode, a drain electrode and wirings are formed on a board holder 9, heating the board 6 to 230 deg.C by a heater, and forming an amorphous silicon film on a surface of the board. The method further comprises the steps of introducing monosilane gas as reaction gas into a film forming reaction chamber 3 via a supply tube 10, and exhausting it via a turbo molecular pump 13. The method further comprises the steps of generating a plasma by applying microwaves, and forming an amorphous silicon film having a thickness of 200nm. The method further comprises the steps of then forming a silicon nitride film of about 200nm thick as a gate insulating film by a microwave plasma CVD method, vapor-depositing aluminum as an upper electrode, and then forming it into a gate electrode pattern, thereby obtaining the transistor.

A metal insulator semiconductor transistor

Abstract: An MIS transistor, which is built on an insulating layer (11) has the insulating layer (11) arranged with a thin portion (12) under the channel region (16) of the MIS transistor and a thick portion (13) under the remainder of the device, and has a conducting layer (19) formed beneath the insulating layer (11). Typically the device is a short channel MIS transistor having a channel length of 2.0 µm or less. Such a transistor has the advantage that equipotential lines run generally parallel to the gate electrode (17) and have a reduced drain voltage feedback and an increased trans-conductance and punch-through voltage.