Showing papers on "Thin-film transistor published in 1983"

Charge trapping instabilities in amorphous silicon‐silicon nitride thin‐film transistors

Abstract: The most important instability mechanism in amorphous silicon‐silicon nitride thin‐film transistors is charge trapping in the silicon nitride layer, which leads to a threshold voltage shift (ΔVT). We have measured the time, temperature, and gate voltage dependence of ΔVT and conclude that the rate limiting process, in the charge transfer from semiconductor to insulator, is the conduction in the nitride by variable‐range hopping. The threshold shift (under positive bias) is temperature dependent with an activation energy of 0.3 eV. This activation energy is identified with the mean hop energy required to inject charge deep into the silicon nitride at the low applied fields appropriate to transistor operation.

Method of making low resistance polysilicon gate transistors and low resistance interconnections therefor via gas deposited in-situ doped amorphous layer and heat-treatment

Abstract: In the disclosed method, a transistor is fabricated by depositing an unpatterned layer of silicon on an insulating layer over a surface of a semiconductor substrate, with the silicon layer being deposited in an amorphous state to improve its uniformity in thickness and smoothness. Subsequently, while the silicon layer is still in the amorphous state, it is patterned by removing selected portions to form a gate. This patterning in the amorphous state improves the gates edge definition. Thereafter, the patterned amorphous silicon layer is heated to change it to polycrystalline silicon, thereby increasing its stability and conductivity.

Thin film device applications

Abstract: 1 Thin Film Technology An Introduction- 11 Why Thin Films?- 12 Thin Film Growth Process- 121 Structural Consequences of the Growth Process- 122 Solubility Relaxation- 13 Vapor Deposition Techniques- 131 Physical Vapor Deposition (PVD)- 132 Chemical Vapor Deposition (CVD)- 14 Solution Deposition Techniques- 141 Chemical Solution Deposition (CSD)- 142 Electrochemical Deposition (ECD)- 15 Thick Film Deposition Techniques- 151 Liquid-Phase Epitaxy (LPE)- 152 Screen Printing- 153 Melt Spinning- 154 Dip Coating, Spinning, and Solution Casting- 16 Monitoring and Analytical Techniques- 161 General Remarks- 162 Deposition Rate and Thickness Measurement- 163 Structural Analysis- 164 Composition Analysis- 17 Microfabrication Techniques- 2 Thin Films In Optics- 21 Optics of Thin Films- 22 Antireflection Coatings (AR Coatings)- 221 Single-Layer AR Coatings- 222 Double-Layer AR Coatings- 223 Multilayer and Inhomogeneous AR Coatings- 23 Reflection Coatings- 231 Metal Reflectors- 232 All-Dielectric Reflectors- 24 Interference Filters- 241 Edge Filters- 242 Band-Pass Filters- 25 Thin Film Polarizers- 26 Beam Splitters- 261 Polarizing Beam Splitter- 262 Dichroic Beam Splitter- 27 Integrated Optics- 271 Waveguides- 272 Thin Film Optical Components- 273 Passive Devices: Couplers- 274 Active Devices- 3 Optoelectronic Applications- 31 Introduction- 32 Photon Detectors- 321 Photoconductive Detectors- 322 Photoemissive Detectors- 33 Photovoltaic Devices- 331 Solar Cells: General Analysis- 332 Thin Film Solar Cells- 34 Applications in Imaging- 35 Electrophotography (Xerography and Electrofax)- 36 Thin Film Displays- 361 Electroluminescent (EL) Displays- 362 Electrochromic Displays- 37 Information Storage Devices- 371 Introduction- 372 Optical Hole Memories- 373 Holographic Memories- 38 Amorphous Silicon-Based Devices- 4 Microelectronic Applications- 41 Introduction- 42 Thin Film Passive Components- 421 Electrical Behavior of Metal Films- 422 Dielectric Behavior of Insulator Films- 423 Resistors- 424 Capacitors- 425 Inductors- 426 Conductors (Interconnections and Contacts)- 43 Thin Film Active Components- 431 Thin Film Transistor (TFT)- 432 Thin Film Diodes- 44 Thin Film Integrated Circuits- 45 Microwave Integrated Circuits (MICs)- 46 Surface Acoustic Wave (SAW) Devices- 461 Introduction- 462 SAW Transducer- 463 SAW Delay Line- 464 SAW Band-Pass Filter- 465 SAW Pulse-Compression Filter- 466 SAW Amplifier- 467 SAW Guiding Components- 468 Other Applications- 47 Charge-Coupled Devices (CCDs)- 471 Introduction- 472 Principle- 473 Applications- 48 Thin Film Strain Gauges- 49 Gas Sensors- 5 Magnetic Thin Film Devices- 51 Magnetic Thin Films- 511 Introduction- 512 Uniaxial Anisotropy (UA)- 513 Domains and Domain Walls- 514 Switching in Thin Films- 52 Applications- 521 Computer Memories- 522 Domain-Motion Devices- 523 Thin Film Magnetic Heads- 524 Magnetic Displays- 6 Quantum Engineering Applications- 61 Introduction- 62 Basic Concepts- 63 Superconductivity in Thin Films- 64 S-N Transition Devices- 641 Switching Devices- 642 Cryotron Amplifiers- 643 Computer Memory Devices- 65 Superconductive Tunneling Devices- 651 Quasiparticle (Giaever) Tunneling- 652 Pair (Josephson) Tunneling- 653 SQUIDs- 654 Applications of SQUIDs- 655 Superconducting Electronics- 66 Miscellaneous Applications- 7 Thermal Devices- 71 Introduction- 72 Thermal Detectors- 721 Bolometers and Thermometers- 722 Thermocouples and Thermopiles- 723 Pyroelectric Detectors- 724 Absorption-Edge Thermal Detectors- 73 Thermal Imaging Applications- 74 Photothermal Conversion- 741 Metallic Surfaces- 742 Metal-Semiconductor Tandems- 743 Metal-Semiconductor Mixed Coatings- 744 Interference Stacks- 745 Particulate Coatings- 746 Topological Coatings- 8 Surface Engineering Applications- 81 Introduction- 82 Surface Passivation Applications- 821 Coatings of Reaction Product- 822 Metallic Coatings- 823 Inorganic Coatings- 824 Organic Coatings- 83 Tribological Applications- 831 Wear-Resistant Coatings- 832 Lubricating Coatings- 84 Decorative Applications- 85 Miscellaneous Applications- 851 Adhesion-Promoting Coatings- 852 Preparation of Heterogeneous Catalysts- 853 Preparation of Nuclear Fuels- 854 Fabrication of Structural Forms- 855 Biomedical Applications- References

Manufacture of thin film semiconductor device

Abstract: PURPOSE: To turn a gate electrode into salicide, and reduce gate line resistance, by forming a high melting point metal film on a polycrystalline silicon gate electrode, and annealing the film. CONSTITUTION: After a gate oxide film is formed on a solid-phase epitaxy silicon thin film formed on a quartz substrate, a polycrystalline silicon film is deposited, and a polycrystalline silicon gate electrode 2-5 is formed by patterning. Impurities are ion-implanted, and a source region 3-6 and a drain region 3-7 are formed in a self-alignment manner. A high melting point metal film 3-9 is formed. The polycrystalline silicon gate electrode 2-5 is turned into salicide by annealing, and a salicide layer 3-10 is formed. By selectively eliminating the high melting point metal, a salicide gate electrode 3-12 is formed. After a contact hole is formed in an interlayer insulating film 3-13, a source electrode and a drain electrode are formed, and a thin film transistor whose gate line resistance is small is formed. COPYRIGHT: (C)1995,JPO

Display process and apparatus thereof incorporating overlapping of color filters

Abstract: A display apparatus comprises a first substrate provided with a thin film transistor array as a driving switching element and a second substrate provided with another electrode, and produces a display by electro-optical change generated between these substrates. Visibility of the display is improved in such a way that rays of light incident on the display apparatus are converted into diffusion light. Photoconductive material, in particular amorphous silicon, can be used by covering semiconductive portions of the thin film transistor array of the display apparatus with an intercepting member. In a display apparatus using a thin film transistor array as a driving switching element, a conductive surface electrically insulated from gate lines on a substrate on where the gate lines for the thin film transistor array are formed, such conductive surface acts as a counter electrode of capacitors for storing charge. Therefore the counter electrode of capacitors is separately formed from gate lines, and writing driving voltage can be set without taking effects of voltage change of gate lines into consideration. Shading layers comprising a plurality of color filters also cover each of the thin film transistors.

Method for manufacturing semiconductor Bi-CMOS device

Abstract: A method for forming a Bi-CMOS structure, wherein a vertical npn transistor and CMOS transistors are formed on a single semiconductor substrate, is disclosed. After forming a p-type epitaxial silicon layer on a p-type silicon substrate with a plurality of n+ -type buried layers therein, n-type wells are formed to extend to the n+ -type buried layers. Selective oxidation is performed to form field oxide films so as to define an n-type element region for the npn transistor, an n-type element region for the p-channel MOS transistor, and a p-type element region for the n-channel MOS transistor. An oxide film as a gate oxide film for the CMOS is formed on the surfaces of all the element regions. After forming a p-type active base region of the npn transistor by ion-implantation of boron, an emitter electrode comprising an arsenic-doped polysilicon layer is formed in contact with the p-type active base region. Gate electrodes of the CMOS are formed and have a low resistance due to doping with phosphorus and/or arsenic. Using the emitter electrode as a diffusion source, an n-type emitter region is formed. Boron is then ion-implanted to simultaneously form a p+ -type external base region and p+ -type source and drain regions of the p-channel MOS transistor. Phosphorus is ion-implanted to form an n+ -type collector contact region and n+ -type source and drain regions of the n-channel MOS transistor.

Manufacture of thin film transistor

Abstract: PURPOSE:To enable to inhibit the generation of the defect of short circuiting between a semiconductor film and a gate electrode by a method wherein an opaque gate electrode is formed on a transparent substrate, and the substrate is coated with a negative resist, which is then exposed and developed; thereafter, a gate insulation film is deposited on the substrate by etching an insulation film. CONSTITUTION:The opaque gate electrode 9 of chromium, aluminum silicon, molybdenum, or the like is formed on a transparent plate 8 of quartz or sapphire. Next, after the insulation film 10 of SiOx or SiNx is deposited, it is coated with the negative resist 11 with a coater and the like and irradiated (exposed) with light 12 from back of the transparent substrate 8. Then, the insulation film is etched with the negative resist as a mask, resulting in resist exfoliation; thereafter, the gate insulation film 14 of SiOx or SiNx is deposited. The semiconductor film 15 of amorphous Si or poly Si and the source electrode 16 and the drain electrode 17 of aluminum silicon of aluminum are formed.

The effect of surface states and fixed charge on the field effect conductance of amorphous silicon

Abstract: We have developed a computer program to calculate the field effect conductance for an amorphous semiconductor including the effects of surface states and fixed charge at both surfaces of the thin semiconductor film. For undoped films with a bulk density of states of less than 1017 cm−3 eV−1, the space‐charge region extends to a depth of 0.5 μm. A complete description of the potential distribution in the semiconductor must include the contribution of surface charge from the surface opposite the gate electrode. This is of practical importance in thin film transistors, for example, where different transistor structures and processing of devices can affect the charge density of this surface.

A thin film MOS transistor and an active matrix liquid crystal display device

Abstract: A thin film MOS transistor includes a silicon layer (202) whose thickness, at least in the channel region is less than 2500 ANGSTROM . The silicon layer may be a polycrystalline silicon layer and its thickness in the channel region may be less than its thickness in the source and drain regions. Such thin film MOS transistors may be used in active matrix liquid crystal display devices having a plurality of picture elements arranged in a matrix, each picture element having a thin film MOS transistor as a switching element.

Thin film transistors

Abstract: The thin film transistor comprises a plurality of individual thin film transistors on a common insulating substrate with the plurality of individual thin film transistors being connected together in series. The gate electrode of each individual transistor of the plurality of thin film transistors is connected to form one common gate electrode for the overall transistor. Leakage current in the OFF condition is substantially reduced. Identical performance is achieved from the transistor with interchangeability in designating source and drain terminals, when a symmetry is provided such that the i-th transistor in a series of N is physically identical to the (N-i+1)-th transistor in the overall transistor.

Method of manufacturing thin film transistors and transistors made thereby

Abstract: An improved method of manufacturing thin film transistors A gate metal is patterned to form a gate electrode and a drain, gate and source contact pad for the transistor To reduce shorts and capacitance between the gate and the source or the drain, an intermetal dielectric is patterned to form a central portion over a planar portion of the gate region and to cover any exposed gate edges

Matrix panel with an active driving system

Abstract: In the matrix, a positive type liquid crystal of the twisted nematic type is driven by a thin film transistor arranged on a transparent substrate. The polarity of the video signal, originally generated for a cathode ray tube, is inverted within a driving circuit and the inverted negative video signal is used to drive the positive type liquid crystal display. In the range of voltages of the video signal which correspond to the white level, the active matrix panel is driven by stretching the voltage of the video signal such that comparable voltage-contrast characteristics are achieved with the liquid crystal display as with the cathode ray tube. Leakage current of the thin film transistor during off-periods is reduced by setting a gate voltage during the off-period which is within the range of voltage level of the power source.

A thin film field-effect transistor and a process for producing the same

Abstract: A thin film transistor according to the invention comprises: a glass substrate; a gate electrode which is formed on the glass substrate; a source electrode; a drain electrode; an insulating film which covers at least said gate electrode; and, an amorphous semiconductor layer which is formed on said insulating film, and which comprises a first portion having said source electrode thereon, a second portion having said drain electrode thereon, and a third portion which is between the first and second portions, is located above the gate electrode, and klwhich is thin thickness capable of permeating light of photo lithography therethrough.

Thin film transistor

Abstract: PURPOSE:To obtain the TFT having excellent characteristics by a method wherein a semiconductor layer is formed using an amorphous silicon layer, and a gate insulating layer is formed by a silicon nitride film layer which was formed by performing a plasma CVD method using mixed gas of SiH4, N2 and H2. CONSTITUTION:Glass is used for a substrate, Mo is vapor-deposited in the thickness of approximately 1,500Angstrom using an electron beam, and a gate electrode is formed on the substrate by performing an ordinary photo-etching method. Then, a silicon nitride film of 1,500Angstrom in thickness is formed in a reaction chamber using a capacity coupling type RF plasma CVD device. Subsequently, electric charge is brought to a stop, a reaction chamber is made vacuous to the degree of 1X10 Torr, substrate temperature is set at 250 deg.C, and SiH4 gas is sufficiently filled in the reaction chamber. Glow discharge is started again, the discharge is brought to a stop when an amorphous silicon layer is formed at 2,000Angstrom , the substrate temperature is lowered to 200 deg.C or below, and the sample is picked out. After Al has been vapor-deposited to approximately 3,000Angstrom in thickness using a vacuum-deposition method, a source and drain electrode is formed.

Manufacture of thin film transistor

Abstract: A thin film transistor is disclosed which has an insulator substrate, a gate electrode, a semiconductor layer and a source/drain electrode disposed on the insulator substrate. The source/drain electrode is patterned through a combination of mask deposition technique and photo-lithography technique.

High current thin film transistor

Abstract: A new and improved thin film field effect transistor has increased operating current and speed. The transistor includes a drain, an insulator, and a source formed in layers and vertically arranged with respect to a substrate and each other. The drain, however, and source layers form a plurality of non-coplanar surfaces with respect to the substrate. The device further includes a deposited semiconductor material overlying the non-coplanar surfaces to form a plurality of current conduction channels between the drain and source. A gate insulator overlies the semiconductor material, and a gate electrode overlies the gate insulator. The devices can also include carrier injection structure including a doped semiconductor material electrically coupled to the drain, the source, and the deposited semiconductor material for increasing the injection of current conduction carriers in the current conduction channels.

Method of making a high performance, small area thin film transistor

Abstract: A method of making a high performance, small area thin film transistor having a drain region, an insulating layer, and a source region forming a non-coplanar surface with respect to a substrate is disclosed. The insulative layer is formed in between the source and drain regions. A deposited semiconductor overlies the non-coplanar surface to form a current conduction channel between the drain and source. A gate insulator and gate electrode overly at least a portion of the deposited semiconductor adjacent thereto. The non-coplanar surface can be formed by utilizing a dry process to simultaneously etch through several layers in a continuous one-step process. A second dielectric layer may be formed above the three previous layers. This decouples the gate electrode from the source region by creating two capacitances in series, thereby limiting the capacitance between the gate electrode and the source region.

Thin film transistor having polycrystalline silicon layer with 0.01 to 5 atomic % chlorine

Abstract: A semiconductor element having a main part of a polycrystalline silicon semiconductor layer containing 0.01 to 5 atomic % of chlorine atoms.

Glow discharge polycrystalline silicon thin-film transistors

Abstract: Thin‐film transistors were fabricated from polycrystalline silicon films which were produced by glow discharge decomposition of silane at 500 °C on thermal oxidized silicon substrates. The dependence of the crystalline and electrical properties was observed for thicknesses from about 500 to 4500 A. As the film grew thicker, the strongly (110) oriented polycrystalline structures became predominant. The conductivity changed from 4×10−9 to 10−6 (Ω cm)−1 and the activation energy from 0.57 to 0.5 eV. The field‐effect mobility of these thin‐film transistors also varied with the thickness of the film.

Thin film transistor

Abstract: PURPOSE:To obtain a transistor which does not decrease in the performance even in the state that a light is emitted by forming a gate electrode on a substrate, forming source and drain electrodes through an amorphous Si layer to dispose the gate electrode between the source and drain electrodes, covering the entire surface with a nitrided film, and forming a light shielding film between the source and drain electrodes. CONSTITUTION:An Si3N4 film 1b for preventing the emission of Na ions from a glass plate is covered on the both front and back surfaces of a glass substrate 1a, a gate electrode 2 is formed with Cr at the center of the film 1b of the surface, and the entire surface including the electrode is covered with a gate insulating layer 3 made of Si3N4. Then, an amorphous Si layer 4 is grown on the layer 3, Cr is deposited only on the surface layer, and source and drain electrodes 5, 6 are formed through a photocomposing step in the state to dispose the electrode 2 between the electrodes 5 and 6. At this time an Ar laser light which is continuously oscillated is emitted to the layer 4 to alter the layer 4 of the part opposed to the electrode 2 into recrystallized polycrystalline Si, the entire surface is covered with an Si3N4 film 7, an Al light shielding film 8 is formed between the electrodes 5 and 6, and the entirety is protected by a PIQ film 9.

Method for manufacturing semiconductor devices

Abstract: A method for forming a Bi-CMOS structure, wherein a vertical npn transistor and CMOS transistors are formed on a single semiconductor substrate, is disclosed. After forming a p-type epitaxial silicon layer (33) on a p-type silicon substrate (31) with a plurality of n +- type buried layers (32 1 , 32 2 ) therein, n-type wells (35 1 , 35 2 ) are formed to extend to the n + -type buried layers (32 1 , 32 2 ). Selective oxidation is performed to form field oxide films (41) so as to define an n-type element region for the npn transistor, an n-type element region for the p-channel MOS transistor, and a p-type element region for the n-channel MOS transistor, and a p-type element region for the n-channel MOS transistor. An oxide film (42) as a gate oxide film for the CMOS is formed on the surfaces of all the element regions. After forming a p-type active base region (43) of the npn transistor by ion-implantation of boron, an emitter electrode (46) comprising an arsenic-doped polysilicon layer is formed in contact with the p-type active base region (43). Gate electrodes (47 1 , 47 2 ) of the CMOS are formed and have a low resistance due to doping with phosphorus and/or arsenic. Using the emitter electrode (46) as a diffusion source, an n-type emitter region (49) is formed. Boron is then ion-implanted to simultaneously form a p + -type external base region (50) and p + -type source and drain regions (51, 52) of the p-channel MOS transistor. Phosphorus is ion-implanted to form an n + -type collector contact region (53) and n + -type source and drain regions (54, 55) of the n-channel MOS transistor.

Manufacture of substrate for semiconductor device

Abstract: PURPOSE:To reduce the degree of roughness on the surface of a single crystal Si film on which an insulating film and a selectively provided epitaxial film are coexisted by a method wherein a machine polishing method of a very slow speed and of an excellent controllability is used. CONSTITUTION:A perpendicular-shaped insulating film 2 of 2mum in height and 0.5mum or thereabout in width is provided on a single crystal Si substrate, and a single crystal epitaxial film 3 is formed using SiH2Cl2 and HCl gas as raw material. At this time, the roughness of 4,000Angstrom or thereabout is generated on the surface of the film 3. A machine polishing work is performed by applying pressure of 110g/cm at the low speed of 100Angstrom /min using a weak alkali solution wherein pulverized silica powder of 100Angstrom or less in diameter is suspended. As a result, the roughnened part on the surface of the film 3 is removed, and the plane and warpless surface of 100Angstrom or below can be obtained within the substrate. A high density IC can be formed using this substrate.

Method of manufacturing flat panel backplanes, display transistors and displays made thereby

Abstract: An improved method of manufacturing active matrix display backplanes with thin film transistors thereon and a drive scheme therefor. A refractory metal covers the indium tin oxide (ITO) layer, patterned to form a gate electrode for the transistors and to protect the pixel pad ITO during formation of the transistors. To reduce shorts and capacitance between the gate and the source or the drain, an intermetal dielectric is patterned to form a central portion over a planar portion of the gate region and to cover any exposed gate edges.

Thin film transistor

Abstract: PURPOSE:To completely eliminate the disconnection of aluminum wirings due to improper coverage of an interlayer insulating film by forming the surface of a polycrystalline silicon film formed on a transparent substrate on an oxidized silicon film, thereby reducing the side etching amount and reducing the overhang state under the polycrystalline silicon film as small as possible. CONSTITUTION:The surface of a polycrystalline silicon film formed on the overall surface of a glass substrate 11 is oxidized, thereby forming an oxidized film 19. After the island 12 of the polycrystalline silicon film is then formed, the surface is oxidized as a gate film 13, and a gate electrode 14 is formed on the oxidized silicon film. With the electrode 14 as a mask oxidized films 13, 19 are etched to diffuse source and drain. Since the polycrystalline silicon film is presented in the base, oxidized silicon films are grown from both the island of the upper polycrystalline silicon film and the base of the gate electrode and lower polycrystalline silicon film through an oxidizing step. Then, an interlayer insulating film 16 is formed, a contacting hole is then opened, and aluminum wirings 17 are formed.

Thin film transistor

Abstract: PURPOSE:To improve the operating characteristics of a thin film transistor and to further improve the reliability and the yield at the manufacturing time of a thin film transistor by forming to cover a semiconductor layer in the size and position of a gate electrode CONSTITUTION:The gate electrode of a thin film transistor is formed slightly larger than a semiconductor layer 2 The relationship between the size and the position of these two members as seen from the surface of a substrate and the vertical direction is such that the layer 2 is completely enclosed by a gate electrode 1 (ie, the layer 2 is not extended from the electrode 1) When the size and the position of the electrode 1 are formed to cover the layer 2 as described above, the resistance (Roff) of the layer 2 when a light is emitted from the side of the electrode decreases Further, the step coverage of an insulating layer 5 interposed between the both layers is improved, and the occurrence rate of short circuits between the electrode 1 and a source electrode 3 can be reduced

Transistor having emitter self-aligned with an extrinsic base contact and method of making it

Abstract: A vertical bipolar transistor structure has an extrinsic base region (4) covered by a metal silicide (eg WSi 2 ) layer (6) and a doped (eg with boron) polysilicon layer (7). The metal silicide and polysilicon layers (6, 7) have an opening therein with which the emitter (3) and intrinsic base region (2) of the transistor are aligned. The vertical bipolar transistor structure can be produced by a method including delimiting a transistor area in a semiconductor substrate, depositing in succession over the the transistor area a silicide layer (6), a doped polysilicon layer (7) and a silicon dioxide layer (8), forming an aperture through the silicon dioxide, the doped polysilicon and the silicide layers, forming an insulating layer (8A) over the transistor area and driving in dopant from the polysilicon layer to form an extrinsic base region (4), removing the insulating layer from the base of the aperture but not from the sidewall of the aperture and forming an intrinsic base region and an emitter aligned with the aperture and the extrinsic base region.

High performance, small area thin film transistor

Abstract: A high performance, small area thin film transistor has a drain region, an insulating layer, and a source region at least portions of the edge of which form a non-coplanar surface with respect to a substrate. The insulative layer is formed in between the source and drain regions. A deposited semiconductor overlies the non-coplanar surface to form a current conduction channel between the drain and source. A gate insulator and gate electrode overly at least a portion of the deposited semiconductor adjacent thereto. The length of the current conduction channel is determined by the thickness of the insulative layer and therefore can be made short without precision photolithography. The non-coplanar surface can be formed by utilizing a dry process to simultaneously etch through several layers in a continuous one-step process. A second dielectric layer may be formed above the three previous layers. This decouples the gate electrode from the source region by creating two capacitances in series, thereby limiting further the capacitance between the gate electrode and the source region.

p-type thin-film transistors with vacuum-deposited crystallized copper-doped germanium films

Abstract: Copper-doped 10-nm-thick vacuum-deposited Ge films between vitreous aluminosilicate insulator films can be crystallized at 400°C, with hole mobilities of 80 cm2/V.s. They yield stable p-type TFT's with 105on/off ratio which are process-compatible with n-type CdSe TFT's and thus usable for complementary on-board shift registers in active matrix displays.