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Showing papers on "Thin-film transistor published in 1984"


Patent
23 Mar 1984
TL;DR: In this article, a transition metal oxide (WO3) was used as a semiconductor layer to obtain a transparent thin-film transistor with memorizing property and large ON-current.
Abstract: PURPOSE:To obtain a transparent thin film transistor having a large ON-current and a memorizing property by a method wherein a transition metal oxide is used as a semiconductor layer. CONSTITUTION:A gate 2 is formed on a substrate 1, then an SiO2 film 3 is deposited on the whole surface, a semiconductor layer 4 is formed, and a source electrode 5 and a drain electrode 6 are formed. Then, an SiO2 film 7 is provided in such a manner that it will not be formed on the electrode 6, and a thin film transistor TFT is formed. In this constitution, a transition metal oxide which is WO3 in other words is used. When WO3 is used for the film 4, its ON-current is approximately two figures higher when compared with the TFT whereon an amorphous semiconductor layer is used. Also, as the WO3 is transparent, a transparent TFT is obtained when a transparent electrode is used for electrodes 2, 5 and 6. Besides, a WO3 thin film can maintain the donor position in the film and the width of a depletion layer for a fixed period even after voltage is cut off, and a memorizing property can also be given to the film.

508 citations


Patent
16 Aug 1984
TL;DR: In this paper, a thin-film transistor having a source zone (10), a drain zone (11), and a channel zone (9), and also a source electrode (15, a drain electrode (16) and a gate electrode (13), has been extended so as to cover the channel zone and thereby prevent the entry of light into the channel Zone (9) and the generation of a light-induced current associated therewith.
Abstract: In a thin-film transistor having a source zone (10), a drain zone (11) and a channel zone (9), and also a source electrode (15), a drain electrode (16) and a gate electrode (13), the source electrode (15) or the drain electrode (16) has been extended so as to cover the channel zone (9) and thereby prevent the entry of light into the channel zone (9) and the generation of a light-induced current associated therewith.

107 citations


Journal ArticleDOI
TL;DR: The history of the transistor was traced from early and unsuccessful Bell Labs experiments, through its brief resurgence in the 1960's as a competitor to the MOSFET, its second disappearance from public view followed by years of hibernation at Westinghouse Labs, its emergence in the 1970's, as a candidate for forming very large area integrated circuits for flat panel displays, leading to the present era of intensive, worldwide exploitation as a device which has at last found a suitable problem to solve as mentioned in this paper.
Abstract: The thin film transistor was the first solid-state amplifier ever patented, but has found no practical application until quite recently. The history of this device is traced from the early and unsuccessful Bell Labs experiments, through its brief resurgence in the 1960's as a competitor to the MOSFET; its second disappearance from public view followed by years of hibernation at Westinghouse Labs; its emergence in the 1970's as a candidate for forming very large area integrated circuits for flat panel displays, leading to the present era of intensive, worldwide exploitation as a device which has at last found a suitable problem to solve. The present state of the art of TFT's made of CdSe, poly- and amorphous silicon is reviewed, particularly as it pertains to their current predominant use in high resolution/high performance liquid crystal displays, followed by some views on the future for TFT's in active matrices and, possibly, in other "human size" or macro-electronic components and systems.

106 citations


Journal ArticleDOI
TL;DR: In this article, the authors show that the degree of current crowding is governed by the voltage dependence of the current flowing from the n+ contact to the conducting channel, which is a space-charge-limited current whose magnitude depends on the bulk density of states in the undoped intrinsic layer.
Abstract: Amorphous silicon staggered‐electrode thin‐film transistors (TFT’s) can show current crowding near the origin in the output characteristics. The degree of current crowding is governed by the voltage dependence of the current flowing from the n+ contact to the conducting channel. This current is a space‐charge‐limited current whose magnitude depends on the bulk density of states in the undoped intrinsic layer. For a 0.5‐μm‐thick i layer, calculations predict negligible current crowding for N(E) 3×1016 cm−3 eV−1. Experimental results are consistent with N(E) in the range 1016 cm−3 eV−1–2×1016 cm−3 eV−1. This is lower than the value derived from the transfer characteristic of the TFT (∼1017 cm−3 eV−1), which is evidence for an inhomogeneous distribution of deep gap states through the 0.5‐μm film of α‐Si:H.

57 citations


Patent
07 May 1984
TL;DR: In this article, the light shielding film was used as a photoresist to make a TFT without using poison gas, which is easier than using amorphous insulating film mainly comprising of Ge as a material for light shielding.
Abstract: PURPOSE: To manufacture a TFT without using any poison gas easier than using amorphous insulating film mainly comprising Ge as a material for a light shielding film by means of forming the light shielding film of an opaque organic film. CONSTITUTION: A Cr gate electrode 2 is provided on a glass sheet 1, a poly Si 4 and an N type Si:H fine crystal 5 are laminated on an SiO 2 gate insulating film 3, and Al source.drain electrodes 6, 7 are formed. Next, overall surface is coated with light shielding film 8 mixed with black pigment as a photoresist. Through these procedures, the light shielding film 8 can be formed without using any poison gas such as German and silane etc., to manufacture a TFT easily. COPYRIGHT: (C)1988,JPO&Japio

54 citations


Patent
05 Oct 1984
TL;DR: In this article, the authors proposed to make an operation speed of a driving TFT faster than that of a switching TFT without generating a ununiformity of a thin film and reducing the image quality.
Abstract: PURPOSE: To make an operation speed of a driving TFT faster than that of a switching TFT without generating a ununiformity of a thin film and reducing the image quality, by making a second semiconductor thin film thicker than a first one which is formed on the same substrate where the second semiconductor thin film is formed. CONSTITUTION: About 30,000 pieces of switching TFTs (thin film transistors) 20 are arranged in the form of a matrix in an area 2 on a glass substrate 1 and about 3,000 pieces driving TFT's 30 are arranged in an area 3. Each of the TFTs 20 is a multi-crystal silicon film 200 formed on the substrate 1, having a gate electrode 5 on it with a gate film 4 put between. In a like manner, each of the TFTs 30 is a multi-crystal silicon film 300 formed on the substrate 1, having a gate electrode 5 on it with a gate film 4 put between. Each TFT 20 and 30 also have source areas 21 and 31, drain areas 22 and 32 and channel areas 23 and 33 respectively. By making the film 300 thicker than the film 200, the operation speed of the TFT 30 can be faster than that of the TFT 20 without injuring the uniformity of the characteristics of the TFTs 30 and without increasing the reverse leak current of the TFTs 20. COPYRIGHT: (C)1989,JPO&Japio

53 citations


Patent
12 Mar 1984
TL;DR: In this article, a thin-film transistor of an inverted-staggered structure is modified so that one of the corners overlaps the source and the drain electrodes while three others overlap neither the source nor the drain electrode.
Abstract: A thin-film transistor of an inverted-staggered structure includes a semiconductor layer with a channel portion, a protective insulating film extending on the channel portion of the semiconductor layer, a source electrode, and a drain electrode. The protective insulating film has a rectangular shape with four corners, and each of two of the corners overlaps one of the source electrode and the drain electrode while two others of the corners overlap neither the source electrode nor the drain electrode. The thin-film transistor may be modified so that one of the corners overlaps one of the source electrode and the drain electrode while three others of the corners overlap neither the source electrode nor the drain electrode.

53 citations


Journal ArticleDOI
TL;DR: In this paper, a 2 µm-thick device layer with a 2 inch diameter is formed on a quartz glass substrate without significant degradation in transistor characteristics, and the fundamental processes supporting this technique are wafer thinning using chemi-mechanical polishing and wafer fastening.
Abstract: A device layer transfer technique, a new technique for transferring a thin device layer fabricated on the silicon wafer onto an insulating substrate, is described The fundamental processes supporting this technique are wafer thinning using chemi-mechanical polishing and wafer fastening A 2 µm-thick device layer with a 2 inch diameter is formed on a quartz glass substrate without significant degradation in transistor characteristics

42 citations


Patent
06 Jul 1984
TL;DR: An electric circuit member comprises a substrate provided with a thin film transistor array thereon, an inorganic insulating layer formed over said thin-film transistor array and an organic insulating surface formed over the inorganic layer as mentioned in this paper.
Abstract: An electric circuit member comprises a substrate provided with a thin film transistor array thereon, an inorganic insulating layer formed over said thin film transistor array and an organic insulating layer formed over said inorganic insulating layer.

41 citations


Patent
01 Mar 1984
TL;DR: In this paper, a multilayer structure formed by laminating an a-Si film, a high-melting point metal film and an aluminum film was proposed to suppress the operation of the P channel without modifying significantly the manufacturing process.
Abstract: PURPOSE:To enable to suppress the operation of the P channel without modifying significantly the manufacturing process by a method wherein the respective structure of the source and drain electrodes of an FET is made into a multilayer structure formed by laminating an a-Si film, a high-melting point metal film and an aluminum film in an order of the a-Si film, the high-melting point metal film and the aluminum film. CONSTITUTION:A high-melting point metal 12 of a thin film is formed on the substrate, whereon a patterning of an a-Si film 4 has been finished, using a vacuum evaporating apparatus of a sputtering device, and successively, a source electrode 6 and a drain electrode 7, both made of Al and so forth, are coated on the high-melting point metal 12 by a vacuum evaporating method, a supptering method and so forth. After a resist for the patterns of the source and drain electrodes 6 and 7 was left in the photo process, an etching is performed on the source and drain electrodes 6 and 7, and successively, an etching is performed on the high-melting point metal 12 and an FET is formed. So long as the high-melting point metal 12 is a metal to form a Schottky barrier when the metal has come into contact with the a-Si film 4, that will do. Particularly, it is desirable that metals of more than one, which are chosen from a metal group of Cr, Ta, W, Ni, Mo and Pt, are used for the manufacture of the high-melting point metal 12. It is desirable that the film thickness of the high-melting point metal 12 is made into a thickness of 1-100Angstrom .

39 citations


Patent
29 Oct 1984
TL;DR: In this article, a method of manufacturing a thin film transistor array is simplified by processes to form source and drain electrodes at least of ITO film for pixel electrodes on a gate insulating film covering gate electrode and to form islands of an amorphous semiconductor film and a light shield film in the same masking process on the source and the drain electrodes.
Abstract: A method of manufacturing a thin film transistor array is simplified by processes to form source and drain electrodes at least of ITO film for pixel electrodes on a gate insulating film covering gate electrode and to form islands of an amorphous semiconductor film and a light shield film in the same masking process on the source and the drain electrodes.

Patent
Yoshitaka Tsunashima1
02 May 1984
TL;DR: In this paper, a method of manufacturing an insulated-gate field-effect transistor on a silicon substrate at high density for large scale integration is disclosed, where the source and drain regions of the transistor are formed by implanting low density impurity ions into the silicon substrate and then heating the substrate at a temperature in the range of 900° to 1300° C.
Abstract: A method of manufacturing an insulated-gate field-effect transistor on a silicon substrate at high density for large scale integration is disclosed. The source and drain regions of the transistor are formed by implanting low density impurity ions into the silicon substrate and then heating the substrate at a temperature in the range of 900° to 1300° C. Thereafter, additional ions are implanted into the source and drain regions, and the substrate is heated at a second temperature of 700° C., or lower, to provide good ohmic contact between metal electrodes and the source and drain regions. In addition, the sheet resistivity of the source and drain regions is small so that high speed operation of the transistor is achieved.

Journal ArticleDOI
TL;DR: A detailed review of thin-film transistor technology with a detailed emphasis on amorphous silicon (a−Si:H) devices is given in this paper. But the authors focus on the interface effects and the gate dielectric.
Abstract: This paper reviews thin film transistor technology with a detailed emphasis on amorphous silicon (a‐Si:H) devices. The fabrication and large area technology issues are described. The materials parameters that affect device performance are dominated by interface effects and the gate dielectric. The problem of characterizing the interfaces is discussed. Applications in liquid crystal displays (LCD) and image sensors are described. It is concluded that there is considerable promise for this rapidly expanding technology.

Patent
Naoki Yokoyama1
05 Dec 1984
TL;DR: A compound semiconductor integrated circuit device includes a heterojunction bipolar transistor (B) which has three compoundsonductor layers (12, 13, 14) of alternate conductivity types, one of which layers (14) provides a channel region or a channel-electron-supplying region of a field effect transistor (F).
Abstract: A compound semiconductor integrated circuit device includes a heterojunction bipolar transistor (B) which has three compound semiconductor layers (12, 13, 14) of alternate conductivity types, one of which layers (14) provides a channel region or a channel-electron-supplying region of a field effect transistor (F). In this way both bipolar transistors and FET transistors can be provided in one integrated circuit device.

Patent
13 Feb 1984
TL;DR: In this article, a display pattern additive-color-mixed by using at least three liquid crystal panels which are driven by an active matrix and independently control the radiation of additive three primary colors is presented.
Abstract: PURPOSE:To obtain a new useful projection device free from visual angle dependency, by obtaining a display pattern additive-color-mixed by using at least three liquid crystal panels which are driven by an active matrix and independently control the radiation of additive three primary colors. CONSTITUTION:A TFT is constituted by succeesively patterning and piling up a gate electrode 11, gate insulating film 12, semiconductor film 13, source electrode 14, and drain electrode 15 on a transparent insulating substrate 10 of glass, etc. A light shield and orientation film is further installed to the substrate, on which the TFT is formed, to drive a liquid crystal. Then the substrate of a counter electrode is prepared by installing a transparent conductive film and orientation film for orienting liquid crystal to the surface of a transparent substrate, such as glass, etc. These two substrates are stuck together with a spacer in between and liquid crystal is injected into the space between the substrates. Such a liquid crystal panel is prepared by three for red.green. blue colors. Those three liquid crystal panels are not set by laying each picture element accurately one on top of the other, but set by shifting each picture element in two directions by about the 1/3 of the picture element pitch.

Patent
31 Aug 1984
TL;DR: In this paper, an amorphous silicon compound layer between an insulating film of a semiconductor layer and an ultrafine crystal silicon compound layers was proposed to enhance the electron mobility.
Abstract: PURPOSE:To enhance the electron mobility by forming an amorphous silicon compound layer between an insulating film of a semiconductor layer and an ultrafine crystal silicon compound layer. CONSTITUTION:A metal layer 2 is selectively coated on an insulating substrate 1. Then, a gate insulating layer 3, an amorphous silicon compound semiconductor layer 14, an ultrafine crystal silicon compound conductor layer 24, and an insulating layer 5 are sequentially coated on the entire surface. Then, a portion to become TFT channel in which the layer 5 is superposed on the layer 2 is allowed to remain, the layers 14, 24 are selectively exposed, and an amorphous silicon compound semiconductor layer (n -muC layer) 6 which includes an impurity is coated on the entire surface. Then, the layers 6, 24, 14 are selectively removed, an insulating layer is included in the remaining portion 5' to form insularly. Further, after the hole 7 is formed on the layer 3, a metal layer 9 is coated on the overall surface, source and drain wirings 8 are formed partly on the layer 6' coated on the layers 14', 24', and gate wirings 9 are formed to include the hole 7. With the source and drain wirings 8 as a mask an n type muC layer on the layer 5' is removed.

Patent
Toshio Yanagisawa1
20 Aug 1984
TL;DR: In this paper, the authors present an active matrix type display apparatus which in- dudes a first electrode substrate (15) having a transparent insulation substrate (16) on which a thin film transistor (11) selectively driven by a transparent display pixel electrode (12) is formed, and a connecting portion (10) for connecting the thin-film transistor with the transparent display pixels (12), and a display medium (14) sandwiched between the first and second electrode substrates (15, 17), an electrically conductive light shielding layer (28) which is fixed at a predetermined
Abstract: @ In an active matrix type display apparatus which in- dudes a first electrode substrate (15) having a transparent insulation substrate (16) on which a thin film transistor (11) a transparent display pixel electrode (12) selectively driven by the thin film transistor (11) and a connecting portion (10) for connecting the thin film transistor (11) with the transparent display pixel electrode (12) are formed, a second electrode substrate (17) having another transparent insulation substrate (18) on which an opposing electrode (13) formed of a transparent conductive film is formed, and a display medium (14) sandwiched between the first and second electrode substrates (15, 17), an electrically conductive light shielding layer (28) which is fixed at a predetermined potential is provided on each of thin film transistor portions of the first electrode substrate (15), and a part of the light shielding layer (28) opposes a part of the transparent display pixel electrode (12) through an insulation film (29) so as to form a supplemental storage capacitor

Journal ArticleDOI
M. J. Powell1
TL;DR: In this article, the authors show that the density of electron states is influenced by the gate insulator interface and there is probably a decreasing density of states away from this interface, which is responsible for the observed threshold voltage instability.
Abstract: Amorphous silicon thin film transistors have been fabricated with a number of different structures and materials. To date, the best performance is obtained with amorphous silicon - silicon nitride thin film transistors in the inverted staggered electrode structure, where the gate insulator and semiconductor are deposited sequentially by plasma enhanced chemical vapour deposition in the same growth apparatus. Localised electron states in the amorphous silicon are crucial in determining transistor performance. Conduction band states (Si-Si antibonding σ*) are broadened and localised in the amorphous network, and their energy distribution determines the field effect mobility. The silicon dangling bond defect is the most important deep localised state and their density determines the prethreshold current and hence the threshold voltage. The density of states is influenced by the gate insulator interface and there is probably a decreasing density of states away from this interface. The silicon dangling bond defect in the bulk amorphous silicon nitride also leads to a localised gap state, which is responsible for the observed threshold voltage instability. Other key material properties include the fixed charge densities associated with primary passivating layers placed on top of the amorphous silicon. The low value of the bulk density of states in the amorphous silicon layer increases the sensitivity of device characteristics to charge at the top interface.

Patent
12 Mar 1984
TL;DR: In this paper, two TFTs (T21A and T21B) are provided for one picture element (for example, C21), and their sources are connected to a common signal line Y1, and gates are connected with scanning lines (X2 and X3) which are adjacent to each other with the picture element between them.
Abstract: PURPOSE:To improve considerably the yield of a TFT array by providing two TFTs per one picture element and connecting their gate electrodes to two scanning lines which are adjacent to each other with the picture element between them. CONSTITUTION:Two TFTs (T21A and T21B) are provided for one picture element (for example, C21), and their sources are connected to a common signal line Y1, and gates are connected to scanning lines (X2 and X3) which are adjacent to each other with the picture element between them, and drains are connected to the picture element electrode of the picture element C21. If short-circuit occurs between the gate and the source of the TFT T21B because of a process defect, a line defect is generated to make an evil case. At this time, the gate of the TFT T21B is disconnected from the scanning line X3. The method where a laser beam is irradiated to the gate part to evaporate a metal of the gate connecting part, or the like is used as the disconnecting means, and the gate of each TFT is so formed that it is easily cut in a connection part 28 to the scanning line.

Journal ArticleDOI
TL;DR: In this article, a 10×10 TFT matrix has been fabricated on transparent glass substrates using low temperature (below 600 ˚°C) processes and the field effect mobility of the TFT is 40 cm2/V 2 at a gate voltage of 10 V, and the response time is less than 10 ns.
Abstract: Thin‐film transistors (TFT’s) have been fabricated on molecular‐beam‐deposited (MBD) polycrystalline silicon (poly‐Si) on transparent glass substrates using low temperature (below 600 °C) processes. The field‐effect mobility of the TFT is 40 cm2/V s at a gate voltage of 10 V, and the response time is less than 10 ns. Output characteristics of the TFT’s depend on the poly‐Si film thickness. The threshold gate voltage and the field‐effect mobility become lower and higher, respectively, with increasing film thickness. These results can be explained in terms of the thickness‐dependent crystallinity of the surface region in the MBD poly‐Si film. A 10×10 TFT matrix has been fabricated, and by combining the TFT matrix with a twisted‐nematic liquid‐crystal layer, a transmissive‐type active matrix liquid‐crystal display panel has been fabricated. This poly‐Si TFT matrix has proved to be compatible with a liquid‐crystal cell from the viewpoints of both device fabrication and transistor characteristics.

Patent
Hiroshi Iwasaki1
03 Oct 1984
TL;DR: In this article, a semiconductor integrated circuit device consisting of a bipolar transistor and a field effect transistor is described, in which a gate electrode (38, 39) and a collector electrode (402) of the bipolar transistor are formed from a common electrode layer (102) of a high impurity concentration, and in which the collector region (242) of bipolar transistor comprises a region (100) having a conductivity type the same as that of the collector regions (242).
Abstract: A semiconductor integrated circuit device is disclosed which comprises a bipolar transistor and a field effect transistor, in which a gate electrode (38, 39) of the field effect transistor and a collector electrode (402) of the bipolar transistor are formed from a common electrode layer (102) of a high impurity concentration, and in which the collector region (242) of the bipolar transistor comprises a region (100) of a high impurity concentration having a conductivity type the same as that of the collector region (242) of the bipolar transistor.

Journal ArticleDOI
TL;DR: In this paper, a super-thin polysilicon film on a quartz substrate has been fabricated for flat panel matrix displays and the field effect mobility is more than 20 cm2/Vs at the poly-silicon thickness of 150-200 A. The thickness of the film had an important role in improving the electrical properties.
Abstract: N-channel MOS FET's have been fabricated in super-thin polysilicon film on quartz substrate. The thickness of the film had an important role in improving the electrical properties. Moreover, grain boundary passivation by the hydrogen from a plasma-SiN film has been developed to increase the field effect mobility. The field effect mobility is more than 20 cm2/Vs at the polysilicon thickness of 150–200 A; and threshold voltage and leakage current are reduced to 6 V and 10-13 A/µm, respectively. The device obtained in this work can be used not only for flat panel matrix displays but also for other applications.

Patent
25 Jan 1984
TL;DR: In this paper, the authors proposed a method to obtain the transistor of high OFF resistance by a method wherein the semiconductor layer to be turned to a channel is covered by a metal thin film when a transparent electrode is formed, and the transparent electrode and the metal thin material located on the semiconducted layer are removed simultaneously, thereby enabling to eliminate the contamination of semiconductor generating when the electrode was formed.
Abstract: PURPOSE:To obtain the transistor of high OFF resistance by a method wherein the semiconductor layer to be turned to a channel is covered by a metal thin film when a transparent electrode is formed, and the transparent electrode and the metal thin film located on the semiconductor layer are removed simultaneously, thereby enabling to eliminate the contamination of semiconductor generating when the electrode is formed. CONSTITUTION:An Mo gate electrode 2 is provided on the insulated substrate 1 consisting of glass, and an Si3N4 film 4 to be turned to a gate insulating film and an amorphous semiconductor film 5 are laminated and coated on the whole surface including said gate electrode 2. Then, the layer 5 is left as a channel only at the position corresponding to the electrode 2 by performing an etching on the film 5, and the layer 5 is surrounded by an electrode thin film 6 consisting of Mo. Subsequently, a transparent electrode 3 consisting of indium oxide-tin is coated on the whole surface, an aperture is provided on the layer 5, the film 6 exposed in the aperture is removed by performing an etching, and the remaining film 6 is used as an electrode 7 and a drain 8 respectively. A high density transistor suitable for a liquid crystal indicating device can be obtained by performing the above-mentioned procedures.

Patent
18 Jul 1984
TL;DR: In this paper, a thin film transistor is formed in the layer 2 of an amorphous Si or polycrystalline Si, and a gate electrode 4, a drain electrode 5 and a source electrode 6 interposing the gate electrode between them are provided on the surface of the layer thereof interposing an insulating film 3 between them.
Abstract: PURPOSE:To improve crystallinity, and to obtain an FET having the favorable characteristic by a method wherein a recess part is formed on the surface of a substrate consisting of an insulating material, a semiconductor film is grown on the whole surface containing the recess part thereof, annealing is performed to bury a part of the semiconductor film in the recess part, and a thin film transistor is formed in the place thereof. CONSTITUTION:A recess part 10 is provided according to etching, etc., in an insulating substrate 1 consisting of quartz, Pyrex glass, etc., and a semiconductor layer 2 of amorphous Si or polycrystalline Si is grown on the whole surface containing the recess part thereof. Then the layer 2 is selectively etched to leave the layer 2 only on the recess part 10, while at this time, the surface of the layer 2 burying the recess part 10 is not flattened, and protrusion parts 2a, 2b are generated at the edge parts. Therefore, the protrusion parts are molten according to the annealing of a beam to remove the protrusion parts 2a, 2b, and at the same time, the layer 2 is buried satisfactorily in the recess part 10 to enhance crystallinity. After then, a thin film transistor is formed in the layer 2 thereof, and a gate electrode 4, and a drain electrode 5 and a source electrode 6 interposing the gate electrode between them are provided on the surface of the layer thereof interposing an insulating film 3 between them.

Patent
05 Jul 1984
TL;DR: In this article, the authors proposed to obtain a bright display with a high aperture rate of each picture element, by arranging thin film transistors TRs which switch a liquid crystal into an array on one substrate constituting a display panel and arranging a photodetecting circuit on the other substrate so that this circuit faces the array.
Abstract: PURPOSE:To attain a bright display with a high aperture rate of each picture element, by arranging thin film transistors TRs, which switch a liquid crystal, into an array on one substrate constituting a display panel and arranging a photodetecting circuit on the other substrate so that this circuit faces the array. CONSTITUTION:An MOS TR constituted with a gate electrode 13, a gate insulating film 14, a semiconductor film 15 consisting of amorphous material or the like, a source electrode 16, and a drain electrode 17 is formed on a substrate 11 consisting of a transparent insulating material, and a liquid crystal driving transparent electrode 18 is connected to the electrode 17. A color filer 19 is provided on the MOS TR and the electrode 18 for every picture element. Another MOS TR constituted with a gate electrode 20, a gate insulating film 21, a semiconductor film 22, a source electrode 23, and a drain electrode 24 is formed on a substrate 12 which faces the substrate 11 and consists of a transparent insulating material, and a diode 25 is connected to the electrode 24 and is connected to an earth electrode 27 through an ohmic junction layer 26. The liquid crystal driving array and the photodetecting array are formed independently of each other in this manner to attain a bright display with a high aperture rate of each picture element.

Journal ArticleDOI
Fujio Okumura1, S. Kaneko1
TL;DR: In this article, an amorphous Si:H linear image sensor operated by a-Si:H TFT array has been proposed, which consists of photodiode array, TFT arrays, matrix circuit, charge transfer capacitor, and external circuit.
Abstract: An amorphous Si:H linear image sensor operated by a-Si:H TFT array has been proposed. This sensor consists of photodiode array, TFT array, matrix circuit, charge transfer capacitor, and external circuit. Mobility for TFT is 0.6 cm2/V.s and 5 µsec/bit read out time was obtained in the conventional matrix mode scanning. Moreover, a novel driving method is applied in order to improve the effective operation speed and an investigation for TFT noise was performed. Experimental data confirm the validity of the concept.

Patent
16 Feb 1984
TL;DR: In this article, a substrate is formed using the sintered body having Al2O3 or the Al 2O3 wherein a small quantity of MgO is added as a component, and after a conact hole has been provided through the intermediary of an interlayer insulating film, an Al electrode 107 is formed.
Abstract: PURPOSE:To simplify the working and handling processes as well as to contrive reduction in production cost by a method wherein a substrate is formed using sintered ceramic. CONSTITUTION:A substrate 101 is formed using the sintered body having Al2O3 or the Al2O3 wherein a small quantity of MgO is added as a component. After a polycrystalline silicon 102 has been deposited on the ceramic substrate 1, a gate oxide film 104 and a gate electrode 105 are formed by performing a thermal oxidization method and using polycrystalline silicon, and a source and drain layer 103 is formed by performing an ion implantation. Then, after a conact hole has been provided through the intermediary of an interlayer insulating film 106, an Al electrode 107 is formed. As the substrate 101 has a light transmissibility in the same degree as quartz glass, its cost is low, it can be sintered, it can be formed into desired thickness, size and form, and the handling of which can be done in an easy manner.

Journal ArticleDOI
C. Hyun, Michael Shur, M. Hack, Z. Yaniv, V. Cannella 
TL;DR: In this article, it was shown that the field effect mobility in amorphous silicon alloy thin-film transistors in the above threshold regime is dependent on the gate voltage with an exponent close to 2.85.
Abstract: We present experimental evidence to show that the field‐effect mobility in amorphous silicon alloy thin‐film transistors in the above threshold regime is dependent on the gate voltage. The current‐voltage transistor characteristics exhibit a power law dependence on gate voltage with an exponent close to 2.85.

Patent
18 Jun 1984
TL;DR: In this paper, a polysilicon layer is recrystallized and delineated to form the gate for one transistor and the source, channel and drain for the complementary transistor which is totally formed using isolating field oxide as its substrate.
Abstract: The invention relates to the process for manufacturing and the structure of stacked transistors on a silicon substrate wherein a polysilicon layer is employed which is recrystallized and delineated to form the gate for one transistor and the source, channel and drain for the complementary transistor which is totally formed using isolating field oxide as its substrate.

Journal ArticleDOI
TL;DR: In this paper, p-channel MOS transistors have been obtained by lateral chemical vapor deposition (CVD) epitaxial overgrowth of buried oxide layers and subsequent lateral isolation with refilled trenches.
Abstract: Completely dielectrically isolated, p-channel MOS transistors have been obtained by lateral chemical vapor deposition (CVD) epitaxial overgrowth of buried oxide layers and subsequent lateral isolation with refilled trenches. The transistor characteristics are similar to those in bulk control wafers. Isolation between the device island and the substrate is approximately 1012Ω.