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Showing papers on "Thin-film transistor published in 1986"


Journal ArticleDOI
TL;DR: In this article, a 500-1000-A-thick a-Si:H was successfully crystallized by XeCl excimer laser (308nm) annealing without heating a glass substrate.
Abstract: Mo-gate n-channel poly-Si thin-film transistors (TFT's) have been fabricated for the first time at a low processing temperature of 260°C. A 500-1000-A-thick a-Si:H was successfully crystallized by XeCl excimer laser (308nm) annealing without heating a glass substrate. TFT's were fabricated in the crystallized Si film. The channel mobility of the TFT was 180cm2/V.s when the a-Si:H was crystallized by annealing with a laser having an energy density of 200 mJ/cm2. This result shows that high-speed silicon devices can be fabricated at a low temperature using XeCl excimer laser annealing.

400 citations


Journal ArticleDOI
TL;DR: In this article, the authors showed that the sub-threshold slope of transistors made in thin silicon films can be obtained (62 mV/ decade) when the silicon film thickness is smaller than the maximum depletion depth in the transistor channel.
Abstract: Silicon-on-insulator (SOI) n-channel transistors have been made in thin (90 nm) silicon films Both modeling and experimental results show that excellent subthreshold slopes can be obtained (62 mV/ decade) when the silicon film thickness is smaller than the maximum depletion depth in the transistor channel For comparison, the subthreshold slope of transistors made in thicker films is also reported

263 citations


Patent
Toshio Yanagisawa1
29 Sep 1986
TL;DR: In this paper, an active matrix type display apparatus is presented, which includes a first electrode substrate having a transparent insulation substrate on which a thin film transistor is driven by the thin file transistor and a connecting portion for connecting the transistor with the transparent display pixel electrode.
Abstract: In an active matrix type display apparatus which includes a first electrode substrate having a transparent insulation substrate on which a thin film transistor a transparent display pixel electrode selectively driven by the thin file transistor and a connecting portion for connecting the thin film transistor with the transparent display pixel electrode are formed, a second electrode substrate having another transparent insulation substrate on which an opposing electrode formed of a transparent conductive film is formed, and a display medium sandwiched between the first and second electrode substrates, an electrically conductive light shielding layer which is fixed at a predetermined potential is provided on each of thin film transistor portions of the first electrode substrate, and a part of the light shielding layer opposes a part of the transparent display pixel electrode through an insulation film so as to form a supplemental storage capacitor.

174 citations


Journal ArticleDOI
TL;DR: It is suggested that the behavior may involve metastable dangling bonds generated within the amorphous silicon as a consequence of the field-effect-induced increase in electron concentration, which constitutes an important new instability mechanism forAmorphous-silicon thin-film transistors.
Abstract: When a positive gate voltage is applied to an amorphous-silicon thin-film transistor, electrons become trapped in states close to the silicon-dielectric interface. This is studied by a new technique involving the transient discharge current produced under illumination. It is suggested that the behavior may involve metastable dangling bonds generated within the amorphous silicon as a consequence of the field-effect-induced increase in electron concentration. This constitutes an important new instability mechanism for amorphous-silicon thin-film transistors.

129 citations


Patent
28 Nov 1986
TL;DR: In this paper, a polycrystalline silicon diode, which functions as a heat-sensitive element, is formed on the insulation film, and a control section comprising a lateral type, MOS transistor, is also formed.
Abstract: A semiconductor substrate has a power region and a control region. The control region is located in the center portion of the substrate, and the power region surrounds the control region and is separated therefrom. A vertical type, MOS transistor, i.e., an active semiconductor element, is formed on the power region. An insulation film is formed on part of the control region. A polycrystalline silicon diode, which functions as a heat-sensitive element, is formed on the insulation film. A control section comprising a lateral type, MOS transistor is also formed on the control region. The lateral type, MOS transistor is connected to receive a signal form the polycrystalline silicon diode. Further, a polycrystalline silicon resistor, which determines a circuit constant, is formed on the insulation film. The MOS transistor protects the active semiconductor element in response to a signal supplied from the heat-sensitive element showing that the temperature of the semiconductor substrate has risen above a predetermined value. For example, the active semiconductor element may be disabled until the detected temperature drops below a predetermined value.

119 citations


Patent
04 Jun 1986
TL;DR: A semiconductor integrated circuit device and a method of manufacturing the same, wherein an MIS type memory transistor of a two-layered gate electrode structure is formed on the surface of a semiconductor substrate, and an MIS-type transistor for a low voltage having a comparatively thin gate oxide film and a MIS type transistor for high voltage with a comparatively thick gate oxide films are formed around the memory transistor.
Abstract: A semiconductor integrated circuit device and a method of manufacturing the same, wherein an MIS type memory transistor of a two-layered gate electrode structure is formed on the surface of a semiconductor substrate, and an MIS type transistor for a low voltage having a comparatively thin gate oxide film and an MIS type transistor for a high voltage having a comparatively thick gate oxide film are formed around the memory transistor.

117 citations


Patent
29 Sep 1986
TL;DR: In this article, an insulated gate field effect transistor is constructed by forming a non-single crystalline semiconductor film of a first conductivity type on an insulating substrate with the gate electrode functioning as a mask to selectively crystallize the source and drain regions.
Abstract: A method of manufacturing an insulated gate field effect transistor by forming a non-single crystalline semiconductor film of a first conductivity type on an insulating substrate where the semiconductor film includes hydrogen or fluoride, forming a gate insulating film on part of the semiconductor film to be the gate region, forming a gate electrode on the insulating film, inverting the conductivity type of the part of the conductor film to be the source and grain regions by ion doping of impurity corresponding to the second conductivity type opposite to the first conductivity type with the gate electrode functioning as a mask, and then exposing the non-single-crystalline semiconductor film to illumination with the gate electrode functioning as a mask to selectively crystallize the source and drain regions.

107 citations


Patent
29 Aug 1986
TL;DR: In this paper, a thin-film transistor (TFT) of a self-aligned structure is described, where a pair of a source electrode and a drain electrode are formed in alignment with a gate electrode and in contact with low resistance areas formed at both side portions of a semiconductor layer deposited on an insulating substrate.
Abstract: A thin film transistor (TFT) of a self-aligned structure, wherein a pair of a source electrode and a drain electrode are formed in alignment with a gate electrode and in contact with low resistance areas formed at both side portions of a semiconductor layer deposited on an insulating substrate. The low resistance areas are formed by the diffusion of metal atoms through heat-treatment.

82 citations


Journal ArticleDOI
TL;DR: In this paper, a super-thin-film transistor (SFT) was fabricated on quartz at a low temperature process below 610°C using Si+ ion implanted amorphization and subsequent solid phase growth.
Abstract: Advanced polysilicon SFT's (Super-thin-Film Transistor) were fabricated on quartz at a low temperature process below 610°C. Using the technique of Si+ ion implanted amorphization and subsequent solid phase growth and making a super-thin-film structure, superior electrical characteristics such as high electron mobility of 60 cm2/(Vs) were obtained. The oscillation of a 19 stage ring oscillator with a channel length of 8.4 µm was observed. Propagation delay time of 8.13 ns/stage was attained. The device is expected to be applied to monolithic liquid-crystal-display on low temperature glass and three dimensional LSI technology.

77 citations


Journal ArticleDOI
TL;DR: The presence of a floating substrate in SOI transistors gives rise to a decrease of threshold voltage when drain voltage is increased as discussed by the authors, which brings about a dramatic decrease of the so-called "kink effect".
Abstract: The presence of a floating substrate in SOI transistors gives rise to a decrease of threshold voltage when drain voltage is increased. When the devices are made in a very thin silicon film, the latter is completely depleted when the device is in the 'on' state, and no part of the film can act as a floating substrate. This brings about a dramatic decrease of the so-called 'kink effect'.

75 citations


Patent
21 Apr 1986
TL;DR: In this paper, a thin film transistor is connected to a picture element displaying electrode formed on an insulating base plate so that a voltage is applied to the electrode, and a source bus line is formed between the gate and drain electrodes.
Abstract: A thin film transistor is connected to a picture element displaying electrode formed on an insulating base plate so that a voltage is applied to the electrode. The thin film transistor comprises a gate electrode, one or more drain electrodes connected to the picture element displaying electrode and a source bus line which -applies a voltage to one or more source electrodes connected thereto, the source bus line functioning by itself as a source electrode, wherein the one drain electrode is formed between the source bus line and one of the one source electrode connected to the source bus line, or between the source electrodes adjacent to each other.

Patent
M. Kinugawa1
14 Jul 1986
TL;DR: In this article, a monocrystalline silicon substrate having a (110) crystal plane is prepared and a CMOS transistor is formed on this substrate, where the channel length is 1.5 μm or less and the velocity saturation phenomenon of electrons is outstanding.
Abstract: A monocrystalline silicon substrate having a (110) crystal plane is prepared. A CMOS transistor is formed on this substrate. An N channel MOS transistor and a P channel MOS transistor are formed in the surface of the semiconductor substrate. In each of these transistors the channel length is 1.5 μm or less and the velocity saturation phenomenon of electrons is outstanding.

Patent
15 Dec 1986
TL;DR: In this article, the authors proposed a method where a high resistance semiconductor thin film, a gate insulating film and a gate electrode are successively formed on the side face where main electrode regions are multilayer-stacked through an insulating material.
Abstract: PURPOSE:To enable to reduce the length of channel without performing a special microscopic processing by a method wheren a high resistance semiconductor thin film, a gate insulating film and a gate electrode are successively formed on the side face where main electrode regions are multilayer-stacked through an insulating film. CONSTITUTION:The first main electrode thin film region 3, an insulating film 17 and the second main electrode thin film region 2 are successively stacked on the surface of a substrate 1 having the surface consisting at least of an insulator, and a high resistance semiconductor thin film 5 is formed on the side face of stacked region 3, film 17 and the region 2 in such a manner that at least both ends of the film 5 come in contact with the regions 2 and 3. A gate electrode 4 is provided on the surface of the thin film 5 through the intermediary of a gate insulating film 6. The channel length of said thin film transistor is mostly determined by the thickness of the film 17, and an arbitrary value can be selected. Especially, a short channel thin film transistor can be accomplished easily. Besides, as no outside light is projected directly on the thin film 5 even when amorphous Si is used for the thin film 5, it is unnecessary that a light-shielding film is provided.

Journal ArticleDOI
TL;DR: In this article, a new theory of aSi thin-film transistor operation is presented, which predicts two new regimes of operation which occur at very high densities of the induced charge in the a•Si TFT channel.
Abstract: A new theory of a‐Si thin‐film transistor (TFT) operation is presented. In addition to the below‐ and above‐threshold regimes described previously, it predicts two new regimes of operation which occur at very high densities of the induced charge in the a‐Si TFT channel. In a crystallinelike regime the free‐electron concentration exceeds the localized charge concentration at the a‐Si‐insulator interface. In a transitional regime (at lower densities of the induced charge) almost all localized states in the energy gap of amorphous silicon near the interface are filled. In the crystallinelike regime, the field‐effect mobility is close to the band mobility and the operation of an a‐Si TFT is truly similar to the operation of a crystalline field‐effect transistor. Our estimates show that the gate voltage necessary to achieve the crystallinelike regime is about 50 V for an a‐Si TFT with an insulator 1000 A thick and a relative permittivity of approximately 3.9.

Journal ArticleDOI
TL;DR: Mo-gate n-channel poly-Si TFTs have been fabricated for the first time at a low processing temperature of 26°C in this article, where a-Si:H was successfully crystallized by pulsed XeCl excimer laser (308nm) annealing without heating the glass substrate.
Abstract: Mo-gate n-channel poly-Si TFTs have been fabricated for the first time at a low processing temperature of 26°C. 500 to 1000A thick a-Si:H was successfully crystallized by pulsed XeCl excimer laser (308nm) annealing without heating the glass substrate. The channel mobility of the TFT was 180 cm2/V.sec when the a-Si:H was annealed at energy density of 200 mJ/cm2.

Patent
Alt Paul Matthew1
22 Dec 1986
TL;DR: In this paper, a conductive strip is used to test an array of TFT devices prior to the final fabrication of the TFT array into a completed flat panel display, so that nonfunctioning or out of specification arrays can be identified at an early point in the manufacturing cycle.
Abstract: An array of thin film transistor (TFT) devices is provided with a conductive region, such as a strip, for temporarily coupling a floating pel eletrode of each of the plurality of TFT devices to a conductor on an underlying substrate. The conductor may be a row or column metalization line associated with an adjacent row or column of the array. The conductive strip may therefore be utilized, in conjunction with appropriate voltage potentials and test circuitry, to test each of the TFT devices prior to the final fabrication of the TFT array into a completed flat panel display. Thus, nonfunctioning or out of specification arrays may be identified at an early point in the manufacturing cycle of the display. The strip may be comprised of amorphous silicon which is illuminated during the test in order to reduce the intrinsic resistance of the strip. The strip may also be comprised of a layer of metalization, which layer is removed from the array at the completion of the test.

Patent
14 Aug 1986
TL;DR: In this paper, a gate insulation film, a high-resistance semiconductor thin film and a second conductive film 8 are deposited successively in that order to form an island region 10 consisting of the films 8, 4 and 3.
Abstract: PURPOSE:To decrease the number of masking processes and to decrease the wiring resistance, by forming an island region for the purpose of providing an opening in a gate insulation film on a specific electrode and by connecting the island region to the specific electrode by means of a conductive film. CONSTITUTION:An insulating substrate 1 is provided thereon with a first conductive electrode 2 and a specific electrode 7. After that, a gate insulation film 3, a high- resistance semiconductor thin film 4 and a second conductive film 8 are deposited successively in that order. The films are then selectively etched to form an island region 10 consisting of the films 8, 4 and 3. The island region 10 has an overlapped portion 20 with the electrode 7. Third conductive films 25 and 26 are deposited and selectively etched to form drain and source electrodes 5 and 6, respectively. Simultane ously with the films 25 and 26, the exposed film 8 is also selectively etched away so that each of the electrodes 5 and 6 consists of the two layers, namely the electrode 5 consists of the film 25 and the second conductive film 15 while the electrode 6 consist of the film 26 and the second conductive film 16. The electrode 6 is connected to the electrode 7 through the overlapped portion 20. According to such construction, the transistor device can be produced by at least three masking processes. Further, the wiring resistance can be decreased and the external connection can be realized easily.

Patent
07 Apr 1986
TL;DR: In this paper, a thin film transistor formed on an insulating sulstrate is disclosed in which metal silicide layers are formed in a thin-film made of a monocrystalline, polycrystalline or amorphous semiconductor material, to be used as source and drain regions.
Abstract: A thin film transistor formed on an insulating sulstrate is disclosed in which metal silicide layers are formed in a thin film made of a monocrystalline, polycrystalline, or amorphous semiconductor material, to be used as source and drain regions, and further a gate electrode includes a metal silicide layer.

Journal ArticleDOI
TL;DR: In this paper, a polycrystalline silicon thin-film transistor (TFT) technology using a potentially low-cost glass substrate is reported, which is made using modified conventional n-channel MOS processes at temperatures of 800°C or less, with a final hydrogen implantation step.
Abstract: A new polycrystalline silicon thin-film transistor (TFT) technology using a potentially low-cost glass substrate is reported. Transistors are made using modified conventional n-channel MOS processes at temperatures of 800°C or less, with a final hydrogen implantation step. These transistors show leakage currents of 2 × 10-11A/µm of channel width, ON-to-OFF current ratios of 1 × 104at V ds = 9.0 V, and good dc stability. This combination of polycrystalline silicon transistors on potentially low-cost glass substrates offers a new option in the choice of active device technology for large-area flat-panel liquid crystal displays (LCD's).

Patent
03 Oct 1986
TL;DR: A thin-film transistor comprises a source electrode and a drain electrode formed in a spaced-apart relation to each other on a substrate, a semiconductor layer formed over the source and drain electrodes, a gate insulating film formed on the semiconductor layers and a gate electrode on the gate INSulating film as discussed by the authors.
Abstract: A thin-film transistor comprises a source electrode and a drain electrode formed in a spaced-apart relation to each other on a substrate, a semiconductor layer formed over the source and drain electrodes, a gate insulating film formed on the semiconductor layer and a gate electrode on the gate insulating film. First and second ohmic contact layers are formed in the entirety of the surface regions of the semiconductor layer which are in contact with the source and drain electrodes.

Patent
20 Mar 1986
TL;DR: In this article, a superlattice constituted by alternately laminating a large number of a-Si:H layers and aSiNx:H layer is employed as a semiconductor layer in a thin-film transistor using an amorphous semiconductor layers.
Abstract: PURPOSE:To obtain the titled transistor, photoconductivity thereof is inhibited and which is difficult to be subject to the effect of stray light and displays stable performance characteristics, by using a superlattice constituted by alternately laminating a large number of a-Si:H layers and a-SiNx:H layers as a semiconductor layer. CONSTITUTION:A superlattice 3 organized by alternately laminating a large number of a-Si:H and a-SiNx:H is employed as a semiconductor layer in a thin-film transistor using an amorphous semiconductor layer. A gate electrode G is formed at a predetermined position on a substrate 1 consisting of glass, etc., a gate insulating film 2 composed of a-SiO2, etc. is laminated on the gate electrode and a-Si:H layers and a-SiNx:H layers having prescribed layer thickness (such as 10Angstrom -100Angstrom ) are laminated alternately in a large number, and the superlattice 3, the whole layer thickness thereof is brought to approximately 2,500Angstrom , is shaped in a stratified manner. A source electrode S and a drain electrode D are formed at predetermined positions on the superlattice 3, and carriers flowing in the superlattice 3 are controlled by applied voltage to the gate electrode G between the source electrode S and the drain electrode D.

Patent
07 Jul 1986
TL;DR: In this paper, the authors proposed to reduce operating time and costs by removing n aSi and a-Si layers located at a display section through a dry process using source and drain electrodes as masks.
Abstract: PURPOSE:To reduce operating time and costs by removing n a-Si and a-Si layers located at a display section through a dry process using source and drain electrodes as masks. CONSTITUTION:A gate electrode 12 is formed on a transparent insulating substrate 11, and gate insulating film 13, a-Si layer 14, n a-Si layer 14' and a single-or double-layered metal film (electrode material) are formed in the form of films on the gate electrode 12. Subsequently, source and drain electrodes 15 and 16 are patterned using a photolithographic technique, and n a-Si layer 14' and a-Si layer 14 located at an indication part are removed by a dry process using the electrodes 15 and 16 as masks. After that, display electrode 17, source electrode 15 and drain electrode 16 are formed and the n a-Si layer 14' exposed at a channel part is removed by a dry process to form a surface protecting film 18. Thus, a thin film transistor 19 is obtained.

Patent
29 Dec 1986
TL;DR: In this paper, a dot matrix display panel with a thin-film transistor array substrate is presented, where a source electrode and a drain electrode come into contact with the semiconductor layer in a region covering the gate electrode and gate insulating layer.
Abstract: A dot matrix display panel with a thin film transistor and the manufacturing method therefor, the panel being so constructed that a gate insulating layer and a semiconductor layer are provided as one laminated film substantially equal in the size thereto on an insulating substrate having a gate electrode and in a region of the substrate except for the peripheral portion thereof, and a source electrode and a drain electrode come into contact with the semiconductor layer in a region covering the gate electrode and gate insulating layer so as to constitute a thin film transistor array substrate, so that a display medium is sandwiched between the array substrate and the substrate having a transparent electrode.

Patent
Tuan Hsinhg Chien1
24 Oct 1986
TL;DR: In this article, the authors proposed an addressing circuit for large area transducer arrays, which includes at least one thin-film transistor having a resistive path between the transistor gate electrode and one or both of the transistor's other two terminal electrodes in order to provide current leakage paths for equalizing the potential between the gate and the other two terminals during an electrostatic discharge.
Abstract: An electrostatic discharge protection network for large area transducer arrays (32) in which each transducer has associated therewith an addressing circuit for changing the state of the transducer element. Each addressing circuit includes at least one thin film transistor (10) having a resistive path (30) provided between the thin film transistor gate electrode and one or both of the transistor's other two terminal electrodes in order to provide current leakage paths for equalizing the potential between the gate electrode and the other two terminals during an electrostatic discharge.

Journal ArticleDOI
TL;DR: In this paper, the photo field effect in amorphous silicon thin-film transistors has been studied and it has been shown that illumination always produces a change in the band bending and a consequent redistribution of the space charge.
Abstract: Amorphous silicon thin‐film transistors show a marked photosensitivity, with the illumination producing an increase in the off‐current and a negative shift of the threshold voltage. Here we present the results of a complete theory of this photo‐field effect, which includes the steady state flux of electrons and holes perpendicular to the source‐drain current path. We show that illumination always produces a change in the band bending and a consequent redistribution of the space charge. The theory gives an excellent agreement with the experimental results using a simple model for the density of states in the amorphous silicon.

Patent
14 Mar 1986
TL;DR: In this article, an array of thin film transistors is fabricated by forming a plurality of spaced closely adjacent metallic source and drain electrodes on an array area of a transparent substrate, forming semiconductor layers on the substrate between each adjacent pair of source/drone electrodes in overlapping relation to the edges of each such pair, covering the semiconductor layer with a gate insulation film that extends over substantially all of the array area, forming a transparent gate electrode layer over the gate insulation, and covering the transparent gate electrodes layer with photosensitive resin layer which is then exposed to light through the transparent
Abstract: An array of thin film transistors is fabricated by forming a plurality of spaced closely adjacent metallic source and drain electrodes on an array area of a transparent substrate, forming semiconductor layers on the substrate between each adjacent pair of source and drain electrodes in overlapping relation to the edges of each such pair, covering the semiconductor layers with a gate insulation film that extends over substantially all of said array area, forming a transparent gate electrode layer over the gate insulation film, covering the transparent gate electrode layer with a photosensitive resin layer which is then exposed to light through the transparent substrate and transparent gate electrode layer with the metallic source and drain electrodes acting as masks, developing the photosensitive resin layer to remove portions thereof other than the exposed portions, and etching the transparent gate electrode with the remaining portions of the resin layer serving as masks thereby to form the gate electrodes of the thin film transistors in the array.

Patent
16 Oct 1986
TL;DR: In this paper, a roughness is formed in the channel region between the source and drain electrodes in the direction of a channel width W, but this is caused by triangular pillar-like oxide films between the transparent substrate 1 and the gate electrode 6.
Abstract: PURPOSE:To set the drain current at a desired value by a method wherein the channel length-width ratio is changed without increasing the area of the TET by forming a roughness in the channel region between the source and drain electrodes. CONSTITUTION:A semiconductor layer 2 consisting of a-Si, for example, is formed on a light-transmitting substrate 1, such as a glass substrate. Then, a source electrode 3 and a drain electrode 4 are formed on the side of a first main surface 21 of the semiconductor layer 2 and a gate electrode 6 is formed on the side of a second main surface 22 of the semiconductor layer through a gate insulating film 5. Moreover, the gate electrode 6 is connected to a gate bus and a signal bus and the drain and source electrodes 4 and 3 are each connected to each transparent display electrode 7. A roughness is formed in the channel region between the source and drain electrodes 3 and 4 in the direction of a channel width W, but this is caused by triangular pillar-like oxide films 10 between the transparent substrate 1 and the gate electrode 6.

Patent
24 Jun 1986
TL;DR: In this paper, a thermal CVD of high-order silane such as trisilane or higher was used as a channel semiconductor film of a thin-film transistor.
Abstract: PURPOSE:To perform stable operation characterized by high mobility, by using a silicon film made by thermal CVD of high-order silane such as trisilane or higher as a channel semiconductor film of a thin film transistor. CONSTITUTION:On an insulating substrate 1, a gate 2 comprising Ni, W, Mo and the like is formed by evaporation, sputtering and the like. A gate insulating film 3 such as a silicon oxide film and silicon nitride film is laminated by a CVD method and the like on the gate 2. A silicon film 4 of high-order silane such as trisilane or higher is formed by a thermal CVD method on the film 3. A source 5 and a drain 6, which have doublelayer structure of a P-or N-type low resistance semiconductor film and a metal film, are formed. An inverted staggered type thin film transistor is formed. The silicon film 4 is formed as follows: the substrate is heated to a temperature of about 400 deg.C; the high order silane such as the trisilane or higher is introduced in a chamber 7; and the film 4 is formed on the surface of the substrate by thermal decomposition reaction on the substrate.

Patent
14 Aug 1986
TL;DR: In this paper, a method for producing buried oxide layers in selected portions of a semiconductor substrate including the steps of applying a patterned mask made from a high-density material over a semiconducted substrate and selectively forming buried oxide layer by oxygen ion implantation was proposed.
Abstract: A method for producing buried oxide layers in selected portions of a semiconductor substrate including the steps of applying a patterned mask made from a high-density material over a semiconductor substrate and selectively forming buried oxide layers by oxygen ion implantation. The high-density material of the mask is preferably tungsten, but can also be made from other suitable materials such as silicon nitride. A MOS transistor is made by the process of the present invention by applying the high-density mask material over the gate of the transistor, and forming buried oxide layers by ion implantation beneath only the source region and drain region of the transistor. The completed MOS transistor has the characteristics of reduced drain and source capacitance, reduced leakage, and faster response, but does not suffer from the floating-body effect of MOS transistors made by SOI processes.

Patent
01 Apr 1986
TL;DR: In this article, a self-aligned TFT array for liquid crystal display devices and a method of manufacturing the array is described, where a protective insulating layer on a semiconductor layer is exactly aligned with a gate electrode.
Abstract: A self-aligned TFT array for liquid crystal display devices and a method of manufacturing the array are disclosed. A protective insulating layer on a semiconductor layer is exactly aligned with a gate electrode. A self-alignment method is used for patterning the protective insulating layer and an impurity-doped semiconductor layer on the semiconductor layer. No lift-off process is necessary.