Showing papers on "Thin-film transistor published in 1987"

Bias dependence of instability mechanisms in amorphous silicon thin‐film transistors

Abstract: We have measured the bias dependence of the threshold voltage shift in a series of amorphous silicon‐silicon nitride thin‐film transistors, where the composition of the nitride is varied. There are two distinct instability mechanisms: a slow increase in the density of metastable fast states and charge trapping in slow states. State creation dominates at low fields and charge trapping dominates at higher fields. The state creation is found to be independent of the nitride composition, whereas the charge trapping depends strongly on the nitride composition. This is taken as good evidence that state creation takes place in the hydrogenated amorphous silicon (a‐Si:H) layer, whereas the charge trapping takes place in the a‐SiN:H. The metastable states are suggested to be Si dangling bonds in the a‐Si:H, and the state creation process similar to the Staebler–Wronski effect. The confirmation of state creation in a thin‐film transistor means that states can be created simply by populating conduction‐band states i...

Resolution of amorphous silicon thin-film transistor instability mechanisms using ambipolar transistors

Abstract: Bias stress measurements on amorphous silicon‐silicon nitride ambipolar thin‐film transistors give clear evidence for the co‐existence of two distinct instability mechanisms: the metastable creation of states in the a‐Si:H layer and charge trapping in the a‐SiN:H layer. The creation of metastable states in the a‐Si:H is found to dominate at low positive bias, while charge trapping in the nitride dominates at larger positive bias and negative bias.

Vertical type MOS transistor and method of formation thereof

Abstract: A vertical MOS transistor having its channel length determined by the thickness of an insulating layer provided over a semiconductor substrate, rather than by the depth of a trench in which the transistor is formed. As a result, the characteristics of the transistor as relatively unaffected by doping and heat-treatment steps which are performed during formation. Also, the transistor may be formed so as to occupy very little surface area, making it suitable for application in high-density DRAMs. 0O048455372

High-performance thin-film transistors in low-temperature crystallized LPCVD amorphous silicon films

Abstract: Thin-film transistors (TFT's) were fabricated in low-temperature (550°C) crystallized amorphous LPCVD silicon films. The performance of these devices was found to depend upon the deposition temperature. Low threshold voltages and effective mobilities as high as 32 cm2/V.s are reported for devices fabricated in 150-nm-thick films with maximum processing temperature of 860°C. The performance of these devices is shown to be far superior to devices fabricated in as-deposited polycrystalline silicon films.

Thin film transistor array for liquid crystal display panel

Abstract: A thin film transistor array board includes an insulator substrate, a matrix of gate electrodes formed on the insulator substrate and covered with a gate insulator film, a matrix of semiconductor islands formed on the gate insulator film positioning on the gate electrodes, source wirings connected to the source regions of the semiconductor islands, drain wirings connected in common to the drain regions of the semiconductor islands aligned in the same line in parallel with the columns of the gate electrode matrix, a second insulator film covering the whole surface including the drain wirings, the source wirings, the semiconductor islands and the pixel electrodes, the second insulator film having grooves exposing the drain wirings and auxiliary wirings formed in the grooves in contact with the drain wirings.

Thin film semiconductor device and method of manufacturing the same

Abstract: Complementary thin film transistors (C-TFT) formed on an insulating substrate, comprising a pair of highly resistive n-type silicon islands (2, 20), a pair of heavily doped n-type regions (12, 13) formed on one (2) of the islands to form source and drain regions of n-channel TFT, a pair of contacts (170, 180) formed on the surface of the other island (20) and establishing a high potential barrier when the underlying region is of n-type and a low potential barrier when the underlying region is inverted to be of p-type. The process for manufacturing complementary TFTs can be simplified significantly.

Bipolar junction transistor on silicon carbide

Abstract: The invention comprises a bipolar junction transistor formed in silicon carbide. By utilizing high temperature ion implantation of doping ions, the base and emitter can be formed as wells, resulting in a planar transistor. Mesa-type transistors are also disclosed.

Method of manufacturing a thin film transistor

Abstract: A method of manufacturing a thin film transistor comprises the steps of forming a gate electrode on one surface of a transparent substrate, forming on the substrate an insulating layer and a semiconductor layer in the named order to cover the gate electrode, and depositing a positive photoresist layer on the semiconductor layer. Thereafter, the photoresist layer is exposed by irradiating from the other surface of the substrate so as to use the gate electrode as a mask. Therefore, if the positive photoresist layer is developed, the unexposed portion remains on the semiconductor layer to correspond to the gate electrode. Then, the semiconductor layer is etched using the remaining photoresist as a mask so as to form a semiconductor island on the insulating layer, and source and drain electrodes are formed on the semiconductor island.

Method for production of thin film transistor array substrates

Abstract: A method of production of active matrix display substrates using thin film transistors and more particularly to a method for production of substrates for liquid-crystal display use. The active matrix substrate using the thin film transistor is produced by the mask processes of smaller number. The process of the present invention can reduce the number of the masks, by one, of the active matrix substrate using the inverted staggered thin film transistor which requires the masks from five levels to six levels. Further improvements reduce the number of the masks to four levels from three levels, thus contributing greatly towards lower cost, improved yield.

Semiconductor memory device

Abstract: PURPOSE:To provide a semiconductor memory device integrated with a high density by a method wherein a capacitor is provided in a groove formed in a semiconductor substrate and a transistor is provided on an insulating layer formed selectively on the semiconductor substrate and the capacitor and the adjoining transistor are connected by the region of the semiconductor substrate adjacent to the side wall of the insulating layer. CONSTITUTION:An N type diffused region, which is to be one of the electrodes of a capacitor is connected to the source region of a TFT by single crystal 4 and the connection is secured. Moreover, the connection can be formed by a self-alignment manner with a part of a mask pattern for a trench and a part of a mask pattern for a transistor overlapping each other. As a transistor provided on an SiO2 layer 3 has an SOI structure, a space required for separating elements can be small. In other words, the transistor and the capacitor are separated by the side of the depth direction and the side of the horizontal direction of the SiO2 layer 3 which is selectively formed and to be a field oxide film. Moreover, as the separation between capacitors is achieved by a P-N junction including a P type region 2, the element separating structure of this DRAM is very simple.

Thin film transistor

Abstract: The thin film transistor comprises source and drain regions, a channel forming region formed between the source and drain regions, a first (main) gate for turning on or off the transistor, and in particular at least one second (sub-) gate for reducing turn-off leakage current. When the n-channel transistor is turned off, for example, a negative voltage is applied to the main gate to form a p-channel layer in the channel forming region under the main gate and a positive voltage is applied to the subgate to form an n-channel layer in the channel forming region under the subgate, for instance, so that a pn junction can be formed between under the main gate and the subgate to reduce the turn-off leakage current. The above-mentioned disclosure can be clearly applied to p-channel transistors. Further, the above four-terminal transistor can be simply modified to a three-terminal transistor by connecting the main gate to the subgate via a diode or a capacitor or by directly connecting the drain region to the subgate. Further, the above three-terminal transistor can be manufactured in accordance with only the ordinary device manufacturing process.

Thin film transistor

Abstract: PURPOSE:To obtain a vertical TFT which is made of amorphous semiconductor and is operated with a high speed and has a high ON/OFF ratio by a method wherein a gate electrode forms a Schottky junction with an amorphous semiconductor in the boundary in a channel part and forms an MIS junction with the amorphous semiconductor in the boundary in the part other than the channel part with an insulating film between. CONSTITUTION:A 1st main electrode 20 formed on an insulating substrate 10, amorphous semiconductor layers 30 and 70 formed on the electrode 20, 2nd main electrodes 90 selectively formed on them, gate electrodes 50 formed in the amorphous semiconductor layers 30 and 70 and insulating films 40 and 60 which are formed on the gate electrodes 50 on at least one of the 1st electrode 20 side and the 2nd electrode 90 side are provided. The gate electrode 50 forms Schottky junctions with the amorphous semiconductor 70 in the boundaries in channel parts in which carriers travel and, moreover, forms MIS junctions with the amorphous semiconductor layers 30 and 70 in the boundaries in the parts other than the channel parts. With this constitution, a leakage current into the gate electrode can be minimized so that a TFT with a high speed operation and a high ON/OFF ratio can be realized.

Manufacture of thin film transistor

Abstract: PURPOSE:To avoid an abnormal boundary in a channel part where carriers flow and obtain a thin film transistor with a vertical structure which has excellent device characteristics by a method wherein the boundary between amorphous silicon layers which is formed in the channel part is made to be a boundary of N type/N type. CONSTITUTION:1st main electrode 20 is formed on an insulating substrate 10 and 1st amorphous silicon layer 30 which is doped with N-type impurity with a high concentration is formed on the main electrode 20 and further 2nd amorphous silicon layer 40 which is not doped dr is doped with N-type impurity with a low concentration. Then gate electrodes 50 are selectively fo.med and the 2nd amorphous silicon layer 40 is etched with those electrodes 50 as a mask as deep as reaching the 1st amorphous silicon layer 30 and further parts of the 1st amorphous silicon layer 30 are etched. Then 3rd amorphous silicon layer 60 which is not doped or is doped with N-type impurity with a low concentration is formed over the whole surface and further 4th amorphous silicon layer 70 which is doped with N-type impurity with a high concentration is formed on the 3rd layer 60 and 2nd main electrode 80 is selectively formed on the 4th layer 70.

Polycrystalline CdSe films for Thin Film Transistors.

Abstract: Abstract In this paper X-ray, ESCA, TEM and electrical measurements on evaporated CdSe films, used in thin film transistors (TFT), are reported. Special attention has been paid to semiconductor films obtained from recrystallized mixtures of CdSe and 1–2% In 2 Se 3 . Such films might be represented as (3CdSe) x (In 2 Se 3 ) 1- x . Doping the CdSe evaporation source with In yields 20 μm self-aligned TFTs with excellent characteristics: electron mobility in the evaporated thin films increases from 20–50 cm 2 /V · s for undoped films to more than 100 cm 2 /V · s for doped films. DC stability behaviour is also improved: the TFT current drop after 180 s is reduced from 30% to less than 5%.

High‐performance thin‐film transistors from optimized polycrystalline silicon films

Abstract: The performance of thin‐film transistors fabricated in unrecrystallized (small‐grain) polcrystalline silicon is shown to be greatly improved by depositing the films at much lower pressures than normally used in the low‐pressure chemical vapor deposition process Electronic measurements on completed devices are presented and related to the film structure by transmission electron microscopy examination

Manufacture of thin film semiconductor device

Abstract: PURPOSE:To improve the contact between a source region and a drain region and to improve the characteristics of a TFT, when the source and drain regions are annealed with a beam and the resistances of the regions are made low, by making the temperature of the regions higher than other parts, and selectively performing the annealing. CONSTITUTION:For an insulating substrate 1, glass without alkali is used. As a semiconductor film 2, amorphous silicon is deposited. Then, a semiconductor film 2 is annealed with an energy beam 3. As a result, the semiconductor film 2 is crystallized, and a recrystallized semiconductor film 21 is formed. Then, a low resistance semiconductor film 4 and a high melting point metal film 5 are deposited. Only a source region 6 and a drain region 7 are made to remain, and etching is performed. Then, the source region 6 and the drain region 7 are annealed. Absorption only at the source region 6 and the drain region 7 can be made large owing to the temperature distribution at the high melting point metal film 5 at the time of annealing. Therefore, fusing can be selectively performed. The source and the drain can be sufficiently activated. A reflecting film or a reflection preventing film is deposited in addition to the high melting point metal film 5, and the selective annealing can be performed. In this way, the source and drain regions are combined with the high melting point metal film, the reflection preventing film and reflecting film, and therefore the efficient activation becomes possible.

Thin film transistor

Abstract: PURPOSE:To simplify a manufacturing process by a method wherein a gate electrode or source and drain electrodes provided on the side of a picture element electrode directly above a substrate is (are) composed of a double-layer structure (double-layer structures) of a transparent conductor layer and a metal layer (transparent conductor layers and metal layers) CONSTITUTION:A transparent conductor layer 12 is formed over the whole surface of a transparent substrate 1 and a metal layer 13 is formed on it Then the transparent conductor layer 12 and the metal layer 13 are etched and patterned into the forms of a picture element electrode 3 and a gate electrode 2 Then a silicon nitride layer to be a gate insulating film 4 and an amorphous silicon hydride layer to be a semiconductor layer 5 are successively formed over the whole surface and further a phosphorus-doped amorphous silicon hydride layer to be an n type layer 6 is formed and those layers are etched to be patterned and, at the same time, to form a contact hole 9 Then an aluminum layer to be a source electrode 7 and a drain electrode 8 is formed and then the metal film 13, the silicon nitride film, the amorphous silicon hydride film and the like are removed by etching and a passivation film 10 and a light shield 11 are formed

Thin-film transistor

Abstract: PURPOSE:To prevent the characteristics of a transistor from deteriorating due to the response property of an OFF current value to light in a thin film transistor formed using a polycrystalline Si layer as an active layer on a transparent insulating substrate by a method wherein a light-shielding layer is provided on the surface on the side opposite to the surface, whereon the transistor is constituted, of the substrate. CONSTITUTION:An active polycrystalline Si layer 2, a gate insulating film 3 and a gate electrode 4 are laminated in order on the surface of a transparent insulating substrate 1, an interlayer insulating film 5 is provided on these and moreover, a metal wiring 6 is provided to constitute a thin film transistor. A light-shielding layer 7 is provided on the side opposite to the side of the surface of the substrate 1, whereon such a transistor is provided, that is, on the rear of the substrate 1. By forming this layer 7 using poly Si, the layer 7 functions as a light-shielding layer to light from the rear and shows the same photo absorption as that of the active layer. Thereby, the trouble die to the response property of an OFF current value to light is prevented and the OFF current value is kept at a low value and is stabilized.

Modeling of ambipolar a-Si:H thin-film transistors

Abstract: Ambipolar hydrogenated amorphous silicon thin-film transistors are capable of both n- and p-channel device operation. Essential to the fabrication of such devices are ohmic source-drain contact regions and a high-quality low fixed charge gate insulator. A simple model has been developed to describe the output drain current versus drain voltage characteristics of these ambipolar devices, The model involves only the numerical integration of an interpolated sheet conductance function. By using the appropriate flat-band voltage, the model accurately predicts the experimental output drain current characteristics for both n- and p-type operation.

Thin film transistor

Abstract: PURPOSE:To make characteristics of a mass display element stable by screening semiconductor element portions as well as source and drain electrode portions by insulated films. CONSTITUTION:After forming a gate electrode 2 on a glass substrate 1, the gate electrode deposits continuously a gate insulated film 3, a non-doping a-Si semiconductor film 4, and a protective insulated film 5 on all the surface of substrate and causes the protective insulated film to be patterned. Then, phosphorus-doped n -a-Si films 6 are adhered and both n -a-Si film 6 and a-Si semiconductor film4 are etched by an identical regist pattern. In addition, metals or metallic oxide films, of which the a-Si semiconductor film 4 and source and drain electrodes 8 and 9 are composed are shielded by the insulated films 7. This arrangement makes characteristics of mass display elements stable.

A model of current—Voltage characteristics in polycrystalline silicon thin-film transistors

Abstract: An empirical model for the current-voltage characteristics of polycrystalline silicon thin-film transistors is presented. The model was constructed based on the premise that the potential barrier height at the grain boundary depends on both the gate and drain voltages. Polycrystalline silicon film transistors having a coplanar structure were fabricated. Measurements demonstrated excellent agreement with calculations for n-channel devices. In addition, carrier-trap density and grain-boundary mobility, which have strong influences on electrical characteristics, were obtained from this model.

Subthreshold model of a polycrystalline silicon thin‐film field‐effect transistor

Abstract: A model is presented for the subthreshold current versus gate voltage of a polycrystalline silicon thin‐film field‐effect transistor. It utilizes the experimentally observed exponential density of states of polycrystalline silicon grain boundaries and is based on an earlier model of M. Shur and M. Hack [J. Appl. Phys. 55, 3831 (1984)] which they applied to hydrogenated amorphous silicon. Experimental subthreshold curves are presented along with the corresponding curves predicted by the model. In addition current activation data are shown to fit the model. The primary fitting parameter is the density of states at the valence band.

Manufacture of thin-film transistor

Abstract: PURPOSE: To improve a thin film transistor remarkably in an electrical property and stability by a method wherein a gate insulator layer is formed in such a process that insulator, or metal or semiconductor constituting insulator is sputtered by an ion beam as the surface of a substrate on which the gate insulator layer is to be formed is irradiated by ultraviolet rays and spouted by gas. CONSTITUTION: A first gate insulator film 3 is formed in such a manner that a beam of Ar + , O + , or mixed these ions is irradiated from an ion beam device 21 onto a sputtering target 2, for example, under such a condition that a beam voltage is 500V and a beam current is 200mA so as to sputter Al or Al oxide from the sputtering target 2. Moreover, the face of a substrate 1 is irradiated and spouted by ultraviolet rays and oxygen gas respectively through an ultraviolet ray source and an oxygen outlet 23. In this process, oxygen can be activated in reaction by irradiating ultraviolet rays whose wavelength is 130nm∼300nm. By these processes, as oxygen is sufficiently supplied, the insulator film 3 whose composition is close to a stoichiometric composition can be obtained, which is dense and very small in oxygen deficiency inside the film. COPYRIGHT: (C)1989,JPO&Japio

Optical reading of quantum well device

Abstract: Optical apparatus wherein narrow line width light from a source is directed through the substrate of a semiconductor structure and reflected from the gate electrode of a field effect transistor element fabricated on the surface of the semiconductor structure. A quantum well layer serves as the current channel for the field effect transistor, and charge carriers from a doped semiconductor layer provide high mobility carriers in the quantum well layer. Changes in the potential between the gate and source electrodes of the field effect transistor cause the normal pinchoff of carriers in the quantum well layer thereby causing changes in the absorption characteristic presented by the quantum well layer. By directing light from the source at the gate electrode through the substrate of the semiconductor structure, a photodetector can be positioned so as to detect a change in light which has passed twice through the quantum well layer, thereby detecting a change in the electrical state of the field effect transistor.

Laser-recrystallized polycrystalline-silicon thin-film transistors with low leakage current and high switching ratio

Abstract: Laser-recrystallized polycrystalline-silicon thin-film transistors (poly-Si TFT's) with offset-gate structures have been fabricated on quartz substrates. Offset-gate structures make it possible to reduce leakage currents to as low as 5 × 10-14A/µm at V D = 10 V, more than two orders of magnitude lower than that in conventional-structure poly-Si TFT's. Optimization of the dopant concentration in offset-gate regions minimizes degradation of drive current, enabling high switching ratios exceeding 108. Calculations based on the quasi-two-dimensional model indicate that the reduction in leakage current is due to a decrease in lateral electric field strength in the drain depletion region.

Instability mechanism in hydrogenated amorphous silicon thin‐film transistors

Abstract: The degradation of hydrogenated amorphous silicon under an applied field is studied in an amorphous silicon thin‐film transistor. A possible mechanism for metastable defect creation due to trapping of electrons at weak bonds together with a bond‐switching event is investigated. The energy for the bond‐switching process is assumed to be supplied thermally. The rate equation is set up and it is shown that this new model for defect creation is capable of describing the experimentally observed slow field‐effect current transients at various temperatures.

CMOS circuits made in thin SIMOX films

Abstract: MOS transistors and ring oscillators have been fabricated in thin (100 nm) SIMOX films. As has been theoretically predicted, no 'kink' effect is observed in the n-channel devices, the inverse subthreshold slope is lower than in bulk devices (70mV/decade against HOmV/decade in bulk), and the dependence of threshold voltage on gate length is much less pronounced than in the bulk.

Experimental considerations in the quest for a thin-film superconducting field-effect transistor

Abstract: Trilayer structures, comprising a thin-film In/InO x superconductor separated from an Al gate electrode by an overgrown dielectric, have been studied to ascertain the feasibility of electric-field control of superconductivity for device applications, Modulation of the areal charge density of 50-A thick In/InO x films has been found to cause more than a 350Ω/ box$^b$ change in the sheet resistance near the midpoint of the resistive transition in one film and the creation of ~10Ω/ box$^b$ of resistance from the superconducting state of a second film. We report on efforts to increase this modulation by decreasing the electron density of unperturbed films, improving the charge storage capabilities of the thin-film gate dielectrics, and improving the carrier mobility which has been found to be sensitive to interface preparation. Device implications, based on these results, are also discussed.

Amorphous Silicon Superlattice Thin Film Transistors

Abstract: A new type of thin film transistor (TFT) has been fabricated using hydrogenated amorphous silicon (a-Si:H)/silicon nitride (a-Si1-xNx:H) multilayer structures. The field effect mobility of the superlattice TFT was 0.74 cm2/Vs, while that of an a-Si:H TFT with the active layer produced by the same deposition conditions as the superlattice was 0.13 cm2/Vs. The increase in the field effect mobility for the superlattice was interpreted in terms of the quantum size effects in the a-Si:H potential well.

Thin film transistor

Abstract: PURPOSE:To make an ON/OFF ratio sufficiently large even at the time of light irradiation by composing a gate insulating film out of an insulating layer consisting of a substance of small light transmittivity. CONSTITUTION:This device is composed of a gate electrode consisting of a pattern of chromium thin film formed on a light-transmitting glass substrate 1, a gate insulating film 3 consisting of a black tantalum oxide layer and a semiconductor active layer 4 consisting of an amorphous silicon I layer which are laminated on said gate electrode 2 in order, and a source electrode 5 and a drain electrode further formed with an interval on the substrate. If light enters from the substrate side, the tantalum oxide film prevents the light from entering into the semiconductor layer and no photocurrent is produced. Thus, as the gate insulating film intercepts the light so as to prevent photoconductive effect in the semiconductor layer, an ON/OFF ratio at the time of light irradiation can be improved.