Showing papers on "Thin-film transistor published in 1988"
TL;DR: In this article, an offset structure that has an n/sup -/ region between channel and source-drain electrodes has been proposed to reduce anomalous leakage current from n-channel polycrystalline-silicon thin-film transistors.
Abstract: In order to reduce anomalous leakage current from n-channel polycrystalline-silicon thin-film transistors (poly-Si TFTs), an offset structure that has an n/sup -/ region between channel and n/sup +/ source-drain electrodes has been proposed. Drain-current measurements of the poly-Si TFT prove that the offset structure is effective in reducing the anomalous leakage current, and that the optimization of the offset length and the doping concentration in the offset region enlarge the ON/OFF current ratio. Implantation of 5*10/sup 13/ cm/sup -2/ phosphorus ions in the offset region makes the ON/OFF current ratio more than one order of magnitude larger than that of conventional structure TFTs. >
130 citations
CNET1
TL;DR: In this paper, a field effect transistor has been fabricated with organic semiconductors: scandium diphthalocyanine (DTHC) and nickel phTHC (PHC), and the electrical characteristics are studied in air atmosphere.
Abstract: A field effect transistor has been fabricated with organic semiconductors: scandium diphthalocyanine and nickel phthalocyanine. The electrical characteristics are studied in air atmosphere. The influence of the diphthalocyanine film thickness has been detected.
94 citations
Patent•
01 Nov 1988
TL;DR: In this article, a thin-film transistor array is defined as a plurality of transistors arranged in the shape of an array on a substrate each transistor includes a gate electrode, a first insulating layer, a semiconducting layer, an additional source electrode and a drain electrode stacked sequentially one on another.
Abstract: A thin film transistor array in which a plurality of thin film transistors arranged in the shape of an array on a substrate each transistor includes a gate electrode, a first insulating layer, a semiconducting layer, a second insulating layer, a source electrode and a drain electrode stacked sequentially one on another such that the first insulating layer and the second insulating layer are interposed at an overlap portion between a gate bus bar for connecting the gate electrodes in common and a source bus bar for connecting the source electrodes in common.
91 citations
Patent•
04 Oct 1988TL;DR: In this paper, the authors proposed a solid state image sensor consisting of a plurality of sensing cells, each formed of a switching transistor and a thin film sensing device, arranged in a line or a matrix.
Abstract: A solid state image sensor including a plurality of sensing cells, each formed of a switching transistor and a thin film sensing device, arranged in a line or a matrix. The switching transistor is a thin film transistor (TFT) of polycrystalline silicon and the thin film sensing device utilizes a layer of amorphous silicon formed on a lower electrode which is electrically connected to the drain of the switching.
82 citations
TL;DR: In this paper, an increase in drain saturation current for MOS transistors in ultrathin silicon-on-insulator (SOI) films is predicted, compared to similar transistors on bulk or thick SOI films.
Abstract: Based on substrate-charge considerations, an increased drain saturation current for MOS transistors in ultrathin silicon-on-insulator (SOI) films is predicted, compared to similar transistors in bulk or thick SOI films. For typical parameters of 200-A gate oxide with a channel doping of 4*10/sup 16/ cm/sup -3/, the drain saturation current in ultrathin SOI transistors is predicted to be approximately 40% larger than that of bulk structures. An increase of approximately 30% is seen in measurements made on devices in 1000-A SOI films. >
80 citations
Patent•
[...]
28 Nov 1988
TL;DR: In this paper, a picture element electrode is placed on a polysilicon thin film, and a common electrode is provided to conduct to the common electrode through a metallic part and the contact hole, respectively.
Abstract: PURPOSE:To add a sufficiently large capacity in parallel to a capacity of a liquid crystal without lowering a numerical aperture, by placing a picture element electrode on a polysilicon thin film, and connecting the polysilicon thin film layer to a common electrode. CONSTITUTION:A polysilicon thin film 3 is deposited on an insulating substrate 1, impurities are diffused, and thereafter, an insulating film 4 is formed, a polysilicon thin film 5, a gate insulating film 6, and a gate electrode 7 are formed, an ion implantation is executed, a contact hole is opened in a layer insulating film 8, and a data line 9 and a picture element electrode 10 are made to conduct to a TFT. On the other hand, an opposed substrate is provided with a common electrode 11, fixed by a space holding part 13, and a terminal 12 is made to conduct to the common electrode 11 and the polysilicon thin film 3 through a metallic part 14 and the contact hole, respectively. Accordingly, the polysilicon thin film 3 and the common electrode 11 are in the same potential, and an active matrix element is shielded electrostatically. Also, the capacity between the polysilicon thin film 3 and the picture element electrode 10 is added in parallel to the capacity of a liquid crystal, therefore, a time constant of a virtual liquid crystal becomes several times and the display performance is improved remarkably.
75 citations
04 Oct 1988
TL;DR: In this article, it is demonstrated that it is possible to use TFTs (thin-film transistors) to construct CMOS inverters operating at 40 V, and the authors discuss qualitatively and quantitatively the changes which take place in the grain boundary trap density on removal of HCl during gate oxidation and on grain boundary passivation by hydrogenation.
Abstract: It is demonstrated that it is possible to use TFTs (thin-film transistors) to construct CMOS inverters operating at 40 V In addition, the authors discuss qualitatively and quantitatively the changes which take place in the grain boundary trap density on removal of HCl during gate oxidation and on grain boundary passivation by hydrogenation Quantitative measurements of I/sub DS/ as a function of V/sub G/ show that the removal of HCl during gate oxidation of polysilicon lowers the grain boundary trap density by about one third This is a small but still significant improvement in addition to the reductions by factors of 6 to 9 obtained through hydrogenation The activation energy for source-drain conduction at low values of V/sub G/ was measured to be 055 eV and indicates that conduction is controlled by the supply of carriers from mid-gap grain boundary states The activation energy of dual gated devices is twice that for a single gated structure, since at values of V/sub G/ close to the conduction minimum, both gates equally control conduction >
75 citations
Patent•
10 Mar 1988TL;DR: In this article, a thin film transistor and a method of fabricating the transistor was described, and the gate electrode was made small in thickness so that active hydrogen for hydrogenating passivation can penetrate in a surface layer of channel region having substantially uniform thickness.
Abstract: A thin film transistor and a method of fabricating the transistor are disclosed. The gate electrode of this thin film transistor is made small in thickness so that active hydrogen for hydrogenating passivation can penetrate in a surface layer of channel region having substantially uniform thickness, through the gate electrode. Thus, hydrogenation can be effectively carried out for the thin film transistor, independently of the length of a channel formed in the transistor.
73 citations
Patent•
[...]
19 Jan 1988
TL;DR: In this paper, a gate electrode is formed on Corning #7059 glass by a mixture of a polyimide precursor and stearyl alcohol having a mol ratio of 1:1 by an LB method.
Abstract: PURPOSE:To manufacture an amorphous thin film transistor having the low threshold value of a gate voltage with a good yield rate, by using a thin film of a polyimide precursor as a gate insulating film. CONSTITUTION:A gate electrode 2 is formed on Corning #7059 glass. A mixture of a polyimide precursor and stearyl alcohol having a mol ratio of 1:1 is deposited thereon by an LB method. The device is heated, and a polyimide thin film 3 is formed. Then, silane gas is decomposed by discharging using a CVD apparatus, and an amorphous Si thin film 4 is formed on the polyimide thin film 3. The polyimide thin film, which is prepared by discharging using imide forming reaction, has excellent heat resistance, mechanical characteristics and chemical resistance. The film also has excellent electric insulation property. The film is very thin. With this FET, the thinner the gate insulating film, the lower the threshold voltage value.
71 citations
TL;DR: In this paper, X-ray, ESCA, TEM and electrical measurements on evaporated CdSe films, used in thin-film transistors (TFT), are reported.
64 citations
Patent•
[...]
21 Jan 1988
TL;DR: In this article, a thin film transistor with an active layer consisting of amorphous silicon carbide (a-Si 1-x C x ) formed between source and drain electrodes is presented.
Abstract: A thin film transistor having an active layer (19, 24) comprising amorphous silicon carbide (a-Si 1-x C x ) formed between source and drain electrodes (14,15), a gate insulating film (17) formed in contact with the active layer (19, 24) and a gate electrode (18) formed in contact with the gate insulating film (17), the active layer. The gate insulating layer (17, 23) can be made of an amorphous silicon carbide layer having a carbon content greater than the carbon content of the active layer (19, 24). The active layer (24) can further ba a laminated structure of well layers and barrier layers, both made of hydrogenated amorphous silicon carbide with different carbon content, or a laminated structure of well layers made of hydrogenated amorphous silicon and barrier layers made of hydrogenated amorphous silicon carbide.
TL;DR: A thin-film transistor structure was designed using poly(3-methylthiophene) in its oxidized (highly conducting: σ ≈ × 10 4 S/m) state as source and drain contacts as discussed by the authors.
Patent•
26 Oct 1988
TL;DR: In this paper, the authors proposed a method to prevent the generation of a short-circuit between a gate bus line and a drain bus line by a method wherein, after the gate bus and a gate electrode are formed on an insulative substrate, side etchings are further performed in a degree that an insulating film on the gate electrode is removed.
Abstract: PURPOSE: To prevent the generation of a short-circuit between a gate bus line and a drain bus line by a method wherein, after the gate bus line and a gate electrode are formed on an insulative substrate 1, side etchings are further performed in a degree that an insulating film on the gate electrode is removed. CONSTITUTION: An NiCr film 11 is formed on a glass substrate (a transparent insulative substrate) 1 and moreover, an SiNX film 12 is formed as an insulating film. Then, unnecessary parts are selectively removed. Subsequently, side etchings are performed in a degree that the film 12 is removed from the upper part of a gate electrode to form an interlayer insulating film 8 on the film 11 constituting a gate bus line GB. Then, an SiNX film (a gate insulating film) 2, an operating semiconductor layer 3 and an insulating film 4 are formed. Subsequently, a contact layer 6 and a metal film 7 for drain and source electrode use are formed and source and drain electrodes S and D and a drain bus line DB are formed. In an obtained TFT, as the SiNX film 8, which is used as the interlayer insulating film, is interposed between the gate and drain bus lines GB and DB in addition to the film 2, the risk of the generation of a short-circuit between the bus lines is significantly reduced. COPYRIGHT: (C)1990,JPO&Japio
Patent•
NEC1
TL;DR: In this paper, a thin-film transistor array used for a liquid crystal display device uses a plurality of transistor structures as switches between a video signal line and a pixel electrode which is controlled with a control signal applied through a scanning line.
Abstract: A thin-film transistor array used for a liquid crystal display device uses a plurality of transistor structures as switches between a video signal line and a pixel electrode which is controlled with a control signal applied through a scanning line, each of transistor structures having a plurality of thin-film transistors connected in series and parallel and having gates commonly connected to the same scanning line. An example of each transistor structure has four thin-film transistors and has a parallel connection of two sets of series connections of two thin-film transistors or a series connection of two sets of parallel connections of two thin-film transistors.
Patent•
07 Sep 1988TL;DR: In this article, a TFT with a transparent insulative substrate, a gate electrode formed on the substrate, gate insulating film formed on at least the gate electrode, a semiconductor film formed at a position on the gate and a transparent electrode connected to the source electrode.
Abstract: A TFT of the present invention includes a transparent insulative substrate, a gate electrode formed on the substrate, a gate insulating film formed on at least the gate electrode, a semiconductor film formed at a position on the gate insulating film corresponding to the gate electrode, source and drain electrodes arranged on the semiconductor film so as to form a channel portion, a transparent insulating film covering the source and drain electrodes and the semiconductor film, and a transparent electrode connected to the source electrode. A through hole is formed in the transparent insulating film above the source electrode. The transparent electrode is formed on a portion of the transparent insulating film except for a portion above the channel portion on the semiconductor film.
Patent•
IBM1
TL;DR: In this paper, the authors proposed a method to eliminate crosstalk between data lines and pixel cells in a thin-film transistor/liquid crystal display by applying a data signal to a given data line for a time period less than the standard scan line period of the display.
Abstract: The elimination of crosstalk between data lines and pixel cells in a thin film transistor/liquid crystal display is accomplished by applying a data signal to a given data line for a time period less than the standard scan line period of the display, and applying a crosstalk compensation signal to the given data line for the remainder of the scan line period.
Patent•
NEC1
TL;DR: In this article, a semiconductor device provided with an improved thin film transistor which is formed on an insulating layer is described, which comprises a gate electrode, semiconductor film, a source region and a drain region formed in the semiconductor films, a junction between the drain regions and a channel being not overlapped with the gate electrode.
Abstract: There is disclosed a semiconductor device provided with an improved thin film transistor which is formed on a semiconductor substrate via an insulating layer and which comprises a gate electrode, a semiconductor film, a source region and a drain region formed in the semiconductor film, a junction between the drain region and a channel region being not overlapped with the gate electrode.
Patent•
28 Jul 1988TL;DR: In this paper, a production method for producing a semiconductor device by growing a crystalline compound semiconductor on a monocrystalline silicon substrate is described, which is comprised of a step for forming a transition domain varying from a monogeneous silicon layer to a polycrystalline semiconductor layer in the silicon substrate by implanting oxygen ions into the substrate and annealing the substrate.
Abstract: A production method for producing a semiconductor device by growing a crystalline compound semiconductor on a monocrystalline silicon substrate is comprised of a step for forming a transition domain varying from a monocrystalline silicon layer to a polycrystalline silicon layer in the silicon substrate by implanting oxygen ions into the silicon substrate and annealing the silicon substrate and a step for depositing a compound semiconductor layer on the silicon substrate.
Patent•
25 May 1988TL;DR: A thin film transistor comprises a substrate, a semiconductor layer comprising a polycrystalline silicon containing 3 atomic % or less of hydrogen provided on the substrate, and a source region and a drain region provided in the surface part of the semiconductor layers as discussed by the authors.
Abstract: A thin film transistor comprises a substrate, a semiconductor layer comprising a polycrystalline silicon containing 3 atomic % or less of hydrogen provided on said substrate, a source region and a drain region provided in the surface part of said semiconductor layer, an insulating layer provided on said semiconductor layer at the portion between these two regions, a gate electrode provided on said insulating layer, a source electrode forming an electrical contact with the source region and a drain electrode forming an electrical contact with the drain region, the overlapping portions between said gate electrode through the insulating layer beneath said gate electrode and the source region and between said gate electrode through the insulating layer beneath said gate electrode and the drain region begin 2000 Å or less in width.
11 Dec 1988
TL;DR: In this article, an analytic model which can accurately calculate the characteristics of polysilicon TFTs was developed, and the theoretical currentvoltage curves were compared with measured data, and correlations with trap density and device performance were investigated.
Abstract: An analytic model which can accurately calculate the characteristics of polysilicon TFTs was developed. The theoretical current-voltage curves were compared with measured data, and correlations with trap density in polysilicon film and device performance were investigated. Good agreement was obtained between theoretical and measured results. It was also found that on-current was improved by reducing the densities near the band edges in a forbidden gap. This effect was realized by optimizing the film deposition temperature or by using laser annealing. A hydrogenation effect reduced the density near the midgap, which improved off-current. The TFTs were successfully applied in grey-scale liquid-crystal displays (LCDs) with fully integrated drive circuits. >
Patent•
14 Apr 1988TL;DR: In this article, a heterojunction bipolar transistor has an emitter which comprises an expitaxial layer of silicon grown on a silicon and germanium base layer, and the active region of the transistor comprises a semiconductor having a silicon/silicon and Germanium strained lattice.
Abstract: A heterojunction bipolar transistor has an emitter which comprises an expitaxial layer of silicon grown on a silicon and germanium base layer. The active region of the transistor comprises a semiconductor having a silicon/silicon and germanium strained lattice and the silicon and germanium base layer is grown on a silicon substrate while maintaining commensurate growth. The lattice strain is such as to produce a predetermined valence band offset at the emitter/base junction. The mobility in the base is also enhanced over that of an unstrained alloy of the same composition.
Patent•
08 Jun 1988TL;DR: In this paper, the structure of a thin-film semiconductor device for improving the characteristic of a display device and its structure relative to the dominant orientation of a poly-Si film as an active layer of a TFT was described.
Abstract: This invention relates to a thin film semiconductor device and a method for fabricating it, and more particularly a thin film semiconductor device suitably applicable to a display device in an active matrix system and a method for fabricating it. In this invention, the structure of a thin film semiconductor device for improving the characteristic thereof and particularly the structure relative to the dominant orientation of a poly-Si film as an active layer of a thin film transistor (TFT) is disclosed. A method for fabricating a thin film semiconductor device which is capable of forming a poly-Si film at a relatively low process temperature is disclosed. Further, a display device in an active matrix system which provided high performance and high image quality is disclosed. The poly-Si film having a dominant orientation of (111) is formed by forming a poly-Si film on the semiconductor substrate at a temperature up to 570° C. and annealing the substrate at a temperature up to 640° C.
Patent•
23 Feb 1988
TL;DR: In this article, the authors proposed to suppress an increase in the drain current value for stable manufacture of the little transistor by lowering local level density on the side of a valence electron zone of an amorphous silicon n-type conductive layer.
Abstract: PURPOSE:To suppress an increase in the drain current value for stable manufacture of the little transistor, by lowering local level density on the side of a valence electron zone of an amorphous silicon n-type conductive layer. CONSTITUTION:A (PH3)/(SiH4) gas introducing ratio at the time of piling an amorphous silicon n-type conductive layer (a-Si(n) layer) 24 is made under 1X10 , the density of a local level 29 on the side of the valence electron zone 28 in an a-Si(n) layer 24 is lowered, positive hole implantation through this level comes to be suppressed, the value of Ioff (drain current) is suppressed under 10 A. Accordingly, in order that Ioff may manufacture a controllable a-Si(n) layer, the (PH3)/(SiH4) gas introducing ratio can be set up in the range above 3X10 and under 1X10 . The phosphor concentration in the a-Si(n) layer at this time is above 6X10 and under 2X10 in the P/Si ratio by SIMS analysis and specific resistance is 2X10 OMEGA.cm or above and 2X10 OMEGA.cm or below.
TL;DR: In this article, high-voltage thin-film transistors (TFTs) fabricated using CW-Ar laser annealed polycrystalline silicon have an offset gate structure between the source and gate and between the gate and drain.
Abstract: High-voltage thin-film transistors (TFTs) fabricated using CW-Ar laser annealed polycrystalline silicon have an offset gate structure between the source and gate and between the gate and drain. The breakdown voltage, transconductance, and leakage current in various size TFTs are described. These TFTs exhibited n-channel enhancement characteristics with a low-threshold voltage, and a breakdown voltage above 100 V could be obtained at an offset gate length of 20 mu m. Active TFT circuits were fabricated with these high-voltage Si TFTs. These high-voltage TFT circuits can drive thin-film EL (electroluminescent display) at low signal voltage. >
Patent•
10 Jun 1988
TL;DR: A liquid crystal display element for matrix display is characterized by a thin metallic film for smoothing path lines for the source electrodes, formed of the same material as that forming the gate electrodes in a plane as discussed by the authors.
Abstract: A liquid crystal display element for matrix display, employing, as address elements, thin film transistors each having a layered arrangement of a gate electrode, an insulating film, a semiconductor film, a source electrode, a drain electrode and a display picture element electrode formed in that order on an insulating substrate The liquid crystal display element is characterized by a thin metallic film for smoothing path lines for the source electrodes, formed of the same material as that forming the gate electrodes in a plane including the gate electrodes
Patent•
22 Dec 1988TL;DR: In this article, a method and means for assuring the presence of a constant RMS voltage waveform on the data lines in a thin-film transistor matrix addressed liquid crystal display is presented.
Abstract: In a liquid crystal display, and more particularly, in a thin film transistor matrix addressed liquid crystal display, a method and means are provided for assuring the presence of a constant RMS voltage waveform on the data lines. This eliminates uncertainty in the voltage levels on a pixel element caused by parasitic capacitance effects between the data lines and the pixel electrodes. The present invention is also particularly applicable to both binary level and gray scale level devices. Means for carrying out the present method are illustrated in both analog and digital form.
Patent•
21 Mar 1988
TL;DR: In this article, a complementary insulated-gate field effect transistor including insulated gate field effect transistors of p-channel and n-channel types was proposed to prevent the threshold voltage in the n-Channel and p-Channel transistors from scattering widely.
Abstract: In a complementary insulated-gate field effect transistor including insulated-gate field effect transistors of p-channel and n-channel types, a portion of the insulating material layer to be used to form the n-channel transistor is formed to be thicker than a portion thereof to be used to form the p-channel transistor, and a portion of the electrode material layer to be used to constitute the p-channel transistor is formed to be longer along the channel than a portion thereof to be used to constitute the n-channel transistor. This prevents the threshold voltage in the n-channel and p-channel transistors from scattering widely. Alternatively, the ion peak concentration of the ions implanted in the semiconductor substrate and the insulating material layer is located in the proximity of the boundary between the insulating material layer and the semiconductor substrate in the portion to be used to constitute the n-channel transistor, and is located in the semiconductor substrate apart from the insulating material layer in the portion to be used to constitute the p-channel transistor. This also enables the threshold voltage in the n-channel and p-channel transistors to be precisely controlled in the manufacturing processes.
Patent•
04 Feb 1988TL;DR: In this paper, vertical gate thin film transistors are integrated into an actively addressable liquid crystal array to provide the switching function for charging each pixel element and any desired peripheral transistor circuitry.
Abstract: Vertical gate thin film transistors are integrated into an actively addressable liquid crystal array to provide the switching function for charging each pixel element and any desired peripheral transistor circuitry. One of the conductive plates of each pixel of the array includes an extended portion. The address lines for the switching/charging transistors form a grid between the rows and columns of pixels and each intersection of the grid lies on an extended portion of a pixel element with the drain of the associated transistor formed directly on the extended portion. The source of the transistor is that portion of one set of address lines lying superjacent but insulated from the transistor drain. The gate of the transistor is that portion of the second set of address lines which is adjacent but insulated from the edges of the source and drain, lying essentially perpendicular to the substrate. Additional transistors for the peripheral circuitry are formed by the same process steps which form the pixel elements and the switching transistor.
TL;DR: In this article, a charge transport and trapping model for thin nitride-oxide stacked films between silicon substrates and polysilicon gates is proposed, where electron trapping reduces the leakage current and helps to lower the incidence of early failures for thin oxide stacked films.
Abstract: A charge transport and trapping model for thin nitride-oxide stacked films between silicon substrates and polysilicon gates is proposed. Nitride-oxide stacked films can be thought of as an oxide film with electron trapping at the nitride/oxide interface. The density of electron trapping is determined by the current-continuity requirement. The electron trapping reduces the leakage current and helps to lower the incidence of early failures for nitride-oxide stacked films. >
Patent•
09 Mar 1988
TL;DR: In this article, a high voltage MOS field-effect semiconductor device consisting of a first MOS FET and a second FET is presented. But the first FET operates at a lower voltage than the second one.
Abstract: A high voltage MOS field-effect semiconductor device comprising, as formed on a single seimconductor substrate a high voltage first MOS field-effect transistor and a conventional second MOS field-effect transistor operable at a lower voltage than the first transistor. The semiconductor substrate is covered with an aluminum or like conductor layer over the region thereof where the conventional second field-effect transistor is located.