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Showing papers on "Thin-film transistor published in 1993"


Patent
09 Feb 1993
TL;DR: In this paper, an impurity containing silicon film is formed by a chemical vapor deposition method between a source electrode and a drain electrode of a thin film transistor and a silicon film connected to these electrodes, and a flow rate of impurity-containing gas is regulated so that impurity density becomes larger as approaching to the source and the drain electrode, a leakage current in an OFF-state of the transistor is reduced.
Abstract: A crystal silicon film deposited on an insulating film made of a binary system material or a binary system semiconductor film formed by an atomic layer deposition method has a grain as large as approximately 200 nm. Thus, the mobility of carriers is increased. The crystal silicon thereof is grown within a temperature range of 250° C. to 400° C. Accordingly, when a planar type thin film transistor, an inverted stagger type thin film transistor or a stagger type thin film transistor is formed using crystal silicon formed on these films made of a binary system material, transistor characteristics thereof are improved. Further, when an impurity containing silicon film is formed by a chemical vapor deposition method between a source electrode and a drain electrode of a thin film transistor and a silicon film connected to these electrodes, and a flow rate of impurity containing gas is regulated so that impurity density becomes larger as approaching to the source electrode and the drain electrode, a leakage current in an OFF-state of the transistor is reduced. Since the impurity containing silicon film is grown by a chemical vapor deposition method in this case, the impurity density thereof can be controlled easily and the control accuracy is also improved.

261 citations


Patent
21 Jan 1993
TL;DR: In this paper, the authors proposed a method of providing a first and a second Silicon-on-Insulator (SOI) wafer, wherein each SOI wafer includes a silicon layer separated from a bulk silicon substrate by a layer of dielectric material, typically SiO2.
Abstract: A method of providing a first and a second Silicon-on-Insulator (SOI) wafer, wherein each SOI wafer includes a silicon layer separated from a bulk silicon substrate by a layer of dielectric material, typically SiO2. Next, at least one electrical feedthrough is formed in each of the silicon layers and active and passive devices are formed in each of the thin silicon layers. Next, interconnects are formed that overlie the silicon layer and are electrically coupled to the feedthrough. One of the wafers is then attached to a temporary substrate such that the interconnects are interposed between the thin silicon layer and the temporary substrate. The bulk silicon substrate of the wafer having the temporary substrate is then etched to expose the dielectric layer. Further interconnects are then formed through the exposed dielectric layer for electrically contacting the at least one feedthrough. This results in the formation of a first circuit assembly. A next step then couples the further interconnects of the circuit assembly to the interconnects of the second SOI wafer, the second SOI wafer having a bulk substrate, a dielectric layer overlying a surface of the substrate, and a layer of processed silicon overlying the dielectric layer. The temporary substrate is then removed. Additional circuit assemblies may then be stacked and interconnected to form a 3d integrated circuit.

253 citations


Patent
03 Mar 1993
TL;DR: In this paper, a patterning of the deposition of the nucleating site forming material on the glass substrate was proposed to selectively crystallize only in areas in contact with the forming material.
Abstract: A fabrication process polycrystalline silicon thin film transistors commences with the deposition of an ultra-thin nucleating-site forming layer onto the surface of an insulating substrate (e.g., 7059 glass). Next, an amorphous silicon film is deposited thereover and the combined films are annealed at temperatures that do not exceed 600° C. By patterning the deposition of the nucleating site forming material on the glass substrate, the subsequently deposited amorphous film can be selectively crystallized only in areas in contact with the nucleating-site forming material.

251 citations


Journal ArticleDOI
TL;DR: In this paper, the electrical properties of silicon nitride/amorphous silicon structures were investigated using thin film transistors (TFTs) and metal insulator semiconductor (MIS) devices employing either a top nitride (TN) or bottom nitride(BN) as gate insulator.
Abstract: The electrical properties of silicon nitride/amorphous silicon structures were investigated using thin film transistors (TFTs) and metal insulator semiconductor (MIS) devices employing either a top nitride (TN) or bottom nitride (BN) as gate insulator. The density of states (DOS) deduced from the subthreshold transfer characteristic of the TFTs is one to two orders of magnitude higher than that obtained from quasistatic C(V) measurements on the MIS structures. This difference is discussed by considering the different thickness of the a‐Si:H layers of the two devices and the role of a fixed charge at the rear interface. Both techniques indicate a DOS in BN devices which is only slightly lower than in TN devices, by less than a factor of two. The measured field effect mobility of BN TFTs is about 70% higher. The differences in the measured field effect mobility for TN and BN configuration are discussed and ascribed to the source and drain parasitic resistances. The conclusion is verified by the fabrication of a TN TFT with a pure phosphine rear surface treatment, which exhibits performance comparable to BN TFTs.

241 citations


Journal ArticleDOI
TL;DR: In this article, a new fabrication process for polycrystalline silicon thin film transistors on 7059 glass substrates is reported, which has the advantages of short processing time and low processing temperature (≤600°C).
Abstract: A new fabrication process for polycrystalline silicon thin film transistors on 7059 glass substrates is reported. This unique fabrication process has the advantages of short processing time and low processing temperature (≤600 °C). The processing is based on the key step of using an ultrathin Pd layer, introduced to the surface of the glass prior to the deposition of an a‐Si:H film, to reduce the crystallization time and temperature. It is also based on using an electron cyclotron resonance hydrogen plasma to reduced the passivation time. The n‐channel TFTs produced by this new fabrication process have mobilities of 20 cm2/V s, and off‐currents of 0.5 pA/μm.

207 citations


Journal ArticleDOI
TL;DR: In this paper, a thin-film transistor with high carrier mobility has been fabricated using precursor-route poly(2,5thienylenevinylene) (PTV) as semiconductor.
Abstract: A thin‐film transistor (TFT) with high carrier mobility has been fabricated using precursor‐route poly(2,5‐thienylenevinylene) (PTV) as semiconductor. The carrier mobility has been determined to be 0.22 cm2/V s, which is in the same level of that of amorphous silicon TFT. It has also been made clear that the carrier mobility is linearly proportional to the conversion ratio from the insulated precursor polymer to π‐conjugated PTV. The π‐conjugation length is crucial to obtain high carrier mobility in π‐conjugated polymer TFT.

206 citations


Patent
Hisatoshi Mori1, Syunichi Sato1, Naohiro Konya1, Ichiro Ohno1, Hiromitsu Ishii1, Kunihiro Matsuda1 
12 Jan 1993
TL;DR: A thin-film transistor as discussed by the authors comprises a gate electrode formed on a glass substrate, a gate insulating film formed essentially over an entire surface of the substrate to cover the gate electrode, and a drain electrode and a source electrode spaced a specified distance apart on the semiconductor film.
Abstract: A thin-film transistor comprises a gate electrode formed on a glass substrate, a gate insulating film formed essentially over an entire surface of the substrate to cover the gate electrode, a non-single-crystal silicon semiconductor film placed on the gate insulating film to cover the gate electrode; and a drain electrode and a source electrode spaced a specified distance apart on the semiconductor film and electrically connected to the semiconductor film so as to form the channel region of the transistor. The gate electrode is made of titanium-containing aluminum.

166 citations


Patent
01 Apr 1993
TL;DR: A TFT array has a plurality of gate lines and drain lines formed on a transparent insulating substrate The gate lines intersect with the drain lines TFTs are formed at the intersections of the gate line and the drain line.
Abstract: A TFT array has a plurality of gate lines and a plurality of drain lines formed on a transparent insulating substrate The gate lines intersect with the drain lines TFTs are formed at the intersections of the gate lines and the drain lines An opaque film is formed above the gate lines, the drain lines, and the TFTs, allowing no passage of light passing through the gaps between the transparent electrode, on the one hand, and the gate and drain lines, on the other hand Therefore, when the TFT array is incorporated into a liquid-crystal display, the display will display high-contrast images

139 citations


Patent
24 Sep 1993
TL;DR: In this paper, a thin film transistor structure for a liquid crystal display device of the active matrix type, wherein leak current is suppressed to stabilize the threshold voltage and the dispersion in the gate capacitance coupling and the channel length are minimized, is disclosed.
Abstract: A thin film transistor structure for a liquid crystal display device of the active matrix type, wherein leak current is suppressed to stabilize the threshold voltage and the dispersion in the gate capacitance coupling and the channel length are minimized, is disclosed. The liquid crystal display device comprises a substrate having picture element electrodes arranged in a matrix and switching elements for driving the picture element electrodes, another substrate having opposing electrodes thereon and opposed to the former substrate, and a liquid crystal layer held between the substrates. Each switching element has a multi-gate structure wherein two thin film transistors are connected in series and gate electrodes are electrically connected to each other. Each thin film transistor has a lightly doped drain structure wherein a low density impurity region of the same conductivity type as that of a source region or a drain region is provided at least between the source or drain region and a channel region. At least one of a plurality of such low density impurity regions may have a length or a density different from that of the other low density impurity regions so as to assure sufficient on-current while suppressing the leak current.

135 citations


Journal ArticleDOI
M. Hack1, A.G. Lewis1, I.-W. Wu1
TL;DR: In this article, experimental data showing the degradation in performance of polysilicon thin-film transistors (TFTs) under a variety of bias stress conditions are presented. And it is shown that stressing under transient conditions leads to a more severe performance degradation than stressing under comparable steady state conditions.
Abstract: Experimental data showing the degradation in performance of polysilicon thin-film transistors (TFTs) under a variety of bias stress conditions are presented. A model is proposed to explain these effects whereby device performance degrades due to changes in the effective density of defect states in the material. Unlike single-crystal devices which degrade from hot-carrier effects, poly-Si TFTs are believed to degrade primarily due to the presence of high carrier densities in the channel. Good agreement between computer simulations of the device characteristics and experimental data ia demonstrated. It is shown that stressing under transient conditions leads to a more severe performance degradation than stressing under comparable steady-state conditions. >

121 citations


Patent
29 Nov 1993
TL;DR: In this article, a vertical field effect transistor (1400) and diode (1450) were formed on a single III-V substrate and the diode cathode and the transistor drain or collector were formed in a common layer (1408).
Abstract: A vertical field effect transistor (1400) and diode (1450) formed on a single III-V substrate. The diode cathode and the transistor drain or collector may be formed in a common layer (1408).

Patent
30 Mar 1993
TL;DR: In this paper, a three-dimensional multichannel structure of a thin-film transistor gate with a 3D multi-channel structure is described, where the source/drain electrodes are formed so as to be spaced from and opposite to each other on a substrate, and the whole outer layer of each sub-semiconductive layer is used as channel regions.
Abstract: A thin film transistor gate structure with a three-dimensional multichannel structure is disclosed. The thin film transistor gate structure according to the present invention comprises source/drain electrodes formed so as to be spaced from and opposite to each other on a substrate; semiconductive layers, comprised of a plurality of sub-semiconductive layers, each formed in a row, each end of the sub-semiconductive layers being in ohmic-contact with the source/drain electrodes; gate insulating layers surrounding each of the semiconductive layers; and gate electrodes surrounding each of the gate insulating layers. Accordingly, the whole outerlayers of each sub-semiconductive layer surrounded by the gate electrodes serve as channel regions. As a result, the effective channel area increases, thereby improving the channel conductance and current driving ability.

Patent
23 Mar 1993
TL;DR: In this paper, the inverted stagger type thin-film transistor can be pre-processed using a gate insulating film with an impurity to form source, drain, and channel forming regions, and conducting a laser annealing to them.
Abstract: In an inverted stagger type thin-film transistor, the preparing process thereof can be simplified, and the unevenness of the thin film transistor prepared thereby can be reduced That is, disclosed is a preparing method which comprises selectively doping a semiconductor on a gate insulating film with an impurity to form source, drain, and channel forming regions, and conducting a laser annealing to them, or a preparing method which comprises selectively doping the semiconductor region with an impurity by a laser doping method

Patent
03 Nov 1993
TL;DR: In this paper, a method of making a thin film transistor for driving a liquid crystal display comprising the steps of forming a gate electrode on a glass substrate and forming an insulating layer and an amorphous silicon layer in turn on said glass substrate, and scanning laser beams on the surface of said amorphized silicon layer with the end portions of the respective scanned laser beams being overlapped.
Abstract: The present invention provides a method of making a thin film transistor for driving a liquid crystal display comprising the steps of forming a gate electrode on a glass substrate and forming an insulating layer and an amorphous silicon layer in turn on said glass substrate and said gate electrode, and scanning laser beams on the surface of said amorphous silicon layer with the end portions of the respective scanned laser beams being overlapped. According to the method of making a thin film transistor for driving a liquid crystal display of the present invention, a thin film transistor suitable for HDTV, the field effect mobility of which is high, is achieved. Further, in making a thin film transistor, a separate processing step is not required and the number of processing steps can be reduced because constructional features of a TFT are utilized.

Patent
18 Oct 1993
TL;DR: In this paper, the authors proposed a nonvolatile random access memory (NVRAM) cell that employs an enhancement mode nMOS transistor made as an accumulation mode transistor, which is preferred to use a non-reentrant (edgeless) gate transistor structure to further reduce edge effects.
Abstract: A non-volatile random access memory (NVRAM) cell that utilizes a simple, single-transistor DRAM cell configuration. The present NVRAM employs an enhancement mode nMOS transistor made as an accumulation mode transistor. The transistor has an n-type silicon carbide channel layer on a p-type silicon carbide buffer layer, with the channel and buffer layers being on a highly resistive silicon carbide substrate. The transistor also has n+ source and drain contact regions on the channel layer. A polysilicon/oxide/metal capacitor is preferably used which has a very low leakage current. Furthermore, this type of capacitor can be stacked on top of the transistor to save area and achieve high cell density. It is preferred to use a non-reentrant (edgeless) gate transistor structure to further reduce edge effects.

Journal ArticleDOI
TL;DR: In this paper, the authors evaluated the uniformity of thin film transistor (TFT) characteristics by varying the channel size and found that uniformity was degraded as channel length decreased and width fell below 1 µm, while high performance characteristics such as sharp gate voltage swing below 100 mV/dec and high mobility as high as 100 cm2/Vs near room temperature.
Abstract: Uniformity of thin film transistor (TFT) characteristics was evaluated by varying the channel size As channel length decreased and width fell below 1 µm, uniformity was degraded drastically A few samples showed high-performance characteristics such as sharp gate voltage swing below 100 mV/dec and high mobility as high as 100 cm2/Vs near room temperature Upon evaluation of their temperature dependence, the conduction mechanism showed not polycrystalline but single-crystal-like properties in the lattice scattering The improved TFTs are thought to have been formed in grain boundary-free crystal grains

Patent
05 May 1993
TL;DR: In this paper, a semiconductor substrate is provided which has a semiconduct on insulator structure but in which can be formed a thin film integrated circuit having electrical characteristics and microstructure equal to or of greater density than a silicon integrated circuit formed using a bulk single crystal silicon wafer.
Abstract: A semiconductor substrate is provided which has a semiconductor on insulator structure but in which can be formed a thin film integrated circuit having electrical characteristics and microstructure equal to or of greater density than a silicon integrated circuit formed using a bulk single crystal silicon wafer. The semiconductor substrate has a structure which is formed of a sequentially layered single crystal silicon thin film sandwiched between a thermally oxidized silicon film and a silicon oxide or silicon nitride film, an element smoothing layer, a fluoro-epoxy series resin adhesive layer, and a supporting substrate. The single crystal silicon thin film can have integrated circuit devices formed in a sub-micron geometry similar to that of a bulk single crystal silicon. A transparent glass or a bulk single crystal silicon wafer can be used as a supporting substrate. Therefore the semiconductor thin film can integrate a highly fine, dense and compact semiconductor integrated circuit or semiconductor optical element. The semiconductor thin film element has a transparent optical detection region or optical modulation region with 100 million pixels or more.

Journal ArticleDOI
TL;DR: In this article, a novel excimer laser crystallization method based on dual-beam irradiation was proposed to reduce the solidification velocity of the top Si layer by heating the bottom Si layer of the Si/SiO/sub 2/Si/glass substrate structure.
Abstract: High-mobility poly-Si thin-film transistors (TFTs) were fabricated by a novel excimer laser crystallization method based on dual-beam irradiation. The new method can reduce the solidification velocity of the top Si layer by heating the bottom Si layer of the Si/SiO/sub 2//Si/glass substrate structure by means of laser irradiation not only from the front side but also from the back side. The grain size of poly-Si film was enlarged up to 2 mu m. The field-effect mobilities of the TFT exceeded 380 cm/sup 2//V-s for electrons and 100 cm/sup 2//V-s for holes. >

Patent
18 Aug 1993
TL;DR: In this paper, the formation of arrays of thin film transistors (TFT's) on silicon substrates and the dicing and tiling of such substrates for transfer to a common module body are described.
Abstract: The invention relates to the formation of arrays of thin film transistors (TFT's) on silicon substrates and the dicing and tiling of such substrates for transfer to a common module body. TFT's activate display electrodes formed adjacent the transistors after the tiles have been transferred. The invention can be used in a liquid crystal display and may include one or more light shielding layers.

Patent
01 Mar 1993
TL;DR: In this paper, a dual-gate thin-film transistor is fabricated on a first island of polysilicon (29) over the dielectric layer (25), which is formed over the monocrystalline silicon.
Abstract: A method for fabricating a dual gate thin film transistor using a power MOSFET process having a first gate area (22) made from a monocrystalline silicon. A dielectric layer (25) is formed over the monocrystalline silicon. A first gate electrode (58) contacts the first gate area (22). A thin film transistor is fabricated on a first island of polysilicon (29) over the dielectric layer (25). The thin film transistor has a second gate electrode (55), and drain and source electrodes (56, 57) wherein the drain and source electrodes (56, 57) contact different portions of the first island of polysilicon (29). Preferably, the first gate electrode (58) is coupled to the second gate electrode (55).

Patent
16 Nov 1993
TL;DR: In this paper, an amorphous silicon film is formed on a glass substrate by a CVD method, and then the island regions of the polycrystalline silicon regions are arranged in a line and apart with each other in a predetermined distanced by intermittently irradiating laser pulses.
Abstract: An amorphous silicon film is formed on a glass substrate by a CVD method, and then the island regions of the amorphous silicon film is changed to a plurality of polycrystalline silicon regions which are arranged in a line and apart with each other in a predetermined distanced by intermittently irradiating laser pulses each having the same dimensions as those of the island region onto the amorphous silicon film, using a laser beam irradiating section. Switching elements including the island regions as semiconductor regions are formed by etching and film-forming process to constitute a driving circuit section. The section is divided to gate driving circuit sections and source driving circuit sections for driving thin film transistors formed in a pixel region.

Patent
John Martin Shannon1
12 Mar 1993
TL;DR: In this paper, the use of an excimer laser beam annealing was proposed for the fabrication of an LCD device comprising a picture-element array of MIM type devices in the unconverted material and TFT driver circuitry in the crystalline silicon material.
Abstract: Body portions (36) of semiconductor crystalline silicon material of sufficient quality to form high-mobility TFTs (thin-film transistors) and other semiconductor devices of a driver circuit are formed by depositing on a substrate (14) a layer of insulating silicon-based non-stoichiometric compound material (32) and then converting this material (32) into the semiconductive crystalline material (36) by heating with an energy beam (40), for example from an excimer laser. The use of an energy beam (40) permits easy localization of the heating (and consequent conversion) both vertically and laterally. The deposition (e.g. by plasma-enhanced chemical vapour deposition) and the beam annealing can both be carried out without heating the substrate (14) to high temperatures, and so a glass or other low-cost substrate (14) can be used. An unconverted part (32a) underlying the crystalline silicon body portion (36) can form at least part of a gate insulator of the TFT. The deposited non-stoichiometric compound material may be of a type suitable for forming a MIM-type switching device so that unconverted areas (42) of the insulating material ( 32) may be retained for that purpose. This permits the fabrication of an LCD device comprising a picture-element array of MIM type devices in the unconverted material (32) of the layer and TFT driver circuitry in the crystalline silicon material (36) of the layer.

Patent
18 Nov 1993
TL;DR: In this paper, the authors proposed a method for producing an active matrix substrate using a thin film transistor having a gate electrode on an insulating substrate covered with a gate insulating layer.
Abstract: A method for producing an active matrix substrate using a thin film transistor having a gate electrode on an insulating substrate covered with a gate insulating layer, a semiconductor layer on the gate insulating layer, a channel protective layer on the semiconductor layer, a drain electrode having a portion overlying the gate electrode with the interposition of the gate insulating layer, the semiconductor layer and the channel protective layer, and a source electrode having a portion overlying the gate electrode with the interposition of the gate insulating layer, the method enhancing the transistor characteristics of the active matrix substrate with minimum leakage and the removal of an off-current generated from the presence of electrons and holes.

Journal ArticleDOI
TL;DR: In this paper, the morphology of polycrystalline films grown by low-pressure chemical-vapor deposition (LPCVD) is investigated by transmission electron microscopy (TEM) as a function of the film thickness, the deposition pressure, and the level of contamination.
Abstract: The morphology of polycrystalline films grown by low‐pressure chemical‐vapor deposition (LPCVD) is investigated by transmission electron microscopy (TEM) as a function of the film thickness, the deposition pressure, and the level of contamination. An orientation filtering mechanism, due to the growth‐velocity competition in the early stage of growth, is responsible for the preferred orientation of the films. The size of the crystallites, the surface roughness, and the type of the structural defects are investigated by combined cross‐sectional and plane‐view TEM analysis. In polycrystalline silicon thin‐film transistors (TFTs), the influence of surface roughness scattering on the mobility is investigated by measuring the effective electron mobility under high effective normal field at 295 and 77 K. Although the surface curvature is increased when the deposition pressure is decreased, the surface roughness scattering is constant in the deposition pressure range from 40 to 0.5 mTorr. By decreasing the deposi...

Patent
Jaewon Lee1
17 Dec 1993
TL;DR: In this article, a thin-film transistor was proposed to prevent the generation of a leakage current and to improve the operation stability of the transistor by using a reverse bias voltage suppression method.
Abstract: A thin film transistor wherein generation of a leakage current is prevented to improve the operation stability thereof and a method for manufacturing the same. A polysilicon layer is formed on an insulating layer. A gate insulating layer is formed on the polysilicon layer. A gate electrode having a barrier layer formed thereon is formed on the gate insulating layer. The sidewall surface portion of the gate electrode is anodic oxidized to form a metal oxide layer on the sidewall of the gate electrode. A lightly doped drain region having a lower impurity concentration than that of source and drain regions of the thin film transistor or an offset region wherein no impurity is doped is formed in a portion of the polysilicon layer under the metal oxide layer. The thin film transistor may be manufactured by a low temperature process, and leakage current is suppressed when a reverse bias voltage is applied. Therefore, the operation stability of the thin film transistor is improved.

Journal ArticleDOI
TL;DR: In this article, a two-dimensional nonplanar simulator for polycrystalline-silicon thin-film transistors (poly-Si TFTs) was developed, in which the influence of trapped charges and carrier scattering within the grain boundary region are incorporated into Poisson's equations and drift-diffusion current formulations, respectively.
Abstract: A two-dimensional nonplanar device simulator for polycrystalline-silicon thin-film transistors (poly-Si TFTs) was developed, in which the influence of trapped charges and carrier scattering within the grain boundary region are incorporated into Poisson's equations and drift-diffusion current formulations, respectively. With this simulator, the I-V characteristics of poly-Si TFT devices can be characterized. TFTs in polycrystalline silicon were fabricated to test the simulator. Special attention was paid to the conduction mechanism in poly-Si TFTs with large grain size. A concept called the pseudo-subthreshold region is presented to explain the observed behavior. The key factors affecting the pseudosubthreshold slope were investigated and elucidated using the simulator. >

Patent
06 Apr 1993
TL;DR: In this article, an improved method for manufacturing an insulated gate field effect transistor is described, which comprises the steps of forming a semiconductor film on an insulating substrate, forming a gate insulating film on the semiconductor substrate and anoding said gate electrode in order to coat an external surface of said gate electrodes with an oxide film thereof.
Abstract: An improved method for manufacturing an insulated gate field effect transistor is described. The method comprises the steps of forming a semiconductor film on an insulating substrate, forming a gate insulating film on said semiconductor film, forming a gate electrode on said gate insulating film with said gate insulating film inbetween, anoding said gate electrode in order to coat an external surface of said gate electrode with an oxide film thereof and applying a negative or positive voltage to said gate electrode with respect to said semiconductor film. Lattice defects and interfacial states caused by the application of a positive voltage during the anoding are effectively eliminated by the negative voltage application.

Patent
Kalluri R. Sarma1
29 Jul 1993
TL;DR: In this paper, a liquid crystal display where each pixel has a thin film transistor with a silicon pixel electrode is presented. And a doping and recrystallization of the silicon is effected to increase the electrical conductivity and light transmittance for the pixel electrode.
Abstract: A liquid crystal display wherein each pixel has a thin film transistor with a silicon pixel electrode. A doping and recrystallization of the silicon is effected to increase the electrical conductivity and light transmittance of the silicon adequately for the pixel electrode.

Journal ArticleDOI
TL;DR: In this article, the field-effect conductance activation energy as a function of the gate voltage was investigated for polycrystalline silicon thin-film transistors and an analytical expression for Ea was obtained for various models of the bulk and interface states.
Abstract: The field‐effect conductance activation energy Ea as a function of the gate voltage Vg is investigated for polycrystalline silicon thin‐film transistors. An analytical expression for Ea is obtained for various models of the bulk and interface states. Using a computer minimization program to fit the experimental Ea vs Vg data with the theory, the energy distribution of the bulk states and the interface states are separated for nonhydrogenated and hydrogenated polycrystalline silicon thin‐film transistors. In both cases, the bulk states have exponential band tails and a wide peak near the midgap and the interface states have an exponential distribution from the band edge.

Patent
24 Mar 1993
TL;DR: In this paper, the relationship between the distance d (cm) between electrodes and the frequency f (MHz) of the high frequency power source satisfies f(HMz)/d ( cm) < 30 HMz/cm.
Abstract: A method of manufacturing an amorphous silicon thin film exhibiting excellent quality for use in a TFT, a photosensor or a solar cell at a low cost by a plasma CVD method utilizing high frequency discharge, the method being consisting of steps of using a silicon compound such as SiH 4 as raw material gas, making the frequency f (MHz) of a high frequency power source to be 30 MHz or higher, and applying negative voltage to an electrode of a substrate if necessary. Furthermore, it is preferably that the relationship between the distance d (cm) between electrodes and the frequency f (MHz) of the high frequency power source satisfies f(HMz)/d (cm)<30 HMz/cm.