Showing papers on "Thin-film transistor published in 1995"

An analytical model for the above-threshold characteristics of polysilicon thin-film transistors

Abstract: An analytical model for the above-threshold characteristics of long-channel, small-grain and thin channel polysilicon thin film transistors (TFT's) is presented. This model is constructed by considering the barrier potential and the carrier trapping effect at grain boundaries of the channel. A band tail state located at E/sub c/-0.15 eV is taken into account to simulate the I-V characteristics. Based on the model, the theoretically simulated results show good agreement with experimental data of plasma-passivated and unpassivated TFT devices in a wide range of gate and drain biases and temperature. The correlation of transconductance to gate bias is also investigated. It is found that the decrease of grain-boundary barrier potential with gate voltage enhances the transconductance, while this enhancement effect becomes insignificant and causes a decrease of transconductance at high gate bias. >

Metal oxide semiconductor device forming a pn junction with a thin film transistor of metal oxide semiconductor of copper suboxide and manufacture thereof

Abstract: PURPOSE: To obtain an excellent PN junction by doping controlled metal oxide semiconductor with impurities, by controlling defects by introducing hydrogen or the like in the defects due to the excessive oxygen in a part of metal oxide semiconductor of copper suboxide or the like, and controlling the carrier density and the conductivity type. CONSTITUTION: A metal oxide semiconductor 25 is metal semiconductor obtained by oxidizing metal films 24, 24'. An insulating protective film is formed on the surfaces of an insulating film 26 and the metal oxide semiconductor 25. By leading out electrodes connected with source drain electrodes 24, 24', a transistor having a gate electrode 22 is formed. The carrier density and the conductivity type are controlled by eliminating oxygen defects. The P-type conductivity or the N-type conductivity, and the resistivity can be controlled by impurity doping. In these cases, ion implantation method or the like can be applied. Thereby a thin film transistor of high mobility can be formed in a large area by low temperature treatment.

C60 thin film transistors

Abstract: N‐channel field effect transistors with excellent device characteristics have been fabricated by utilizing C60 as the active element. Measurements on C60 thin films in ultrahigh vacuum show on‐off ratios as high as 106 and field effect mobilities up to 0.08 cm2/V s.

Polycrystalline silicon thin film transistors

Abstract: During the past decade there has been a rapid growth of interest in poly-Si for the active device layer in thin film transistors (TFTS) for active matrix flat-panel displays. Whilst the early work, demonstrating the high carrier mobility of these devices, employed processing temperatures of approximately 1000 degrees C and quartz susbtrates, this was soon followed by the investigation of lower-temperature processes which were compatible with the use of glass substrates. Some of the key aspects of this work are reviewed in this article: the preparation of the material by direct deposition and by crystallization from a-Si precursors, the characterization of the defect-induced trapping states within the material and their passivation, and the present understanding of the TFT leakage current mechanisms. This work is put into the context of the requirements for active matrix liquid-crystal displays, and, with the understanding and control of poly-Si which has been achieved to date, its application in this area can be expected to increase rapidly in the coming years.

A method of fabricating a TFT-EL pixel

Abstract: A method of making a 4-terminal active matrix electroluminescent device that utilizes an organic material as the electroluminescent medium is described. In this method, thin film transistors are formed from polycrystalline silicon at a temperature sufficiently low such that a low temperature, silica-based glass can be used as the substrate.

Pd induced lateral crystallization of amorphous si thin films

Abstract: A thin palladium layer (∼40 A) was selectively formed on top of amorphous silicon films before annealing and the effects of palladium layer on the crystallization behavior of the amorphous silicon films were investigated. It was observed that the amorphous silicon right under the Pd layer could be crystallized to grain sizes of several hundred angstroms by annealing at 500 °C. In addition, the area between the Pd thin pads, patterned by lithography, was found to be crystallized to grain sizes of a few tens of microns in length by the same annealing. Such lateral crystallization was found to reach more than 100 μm in some cases. The lateral crystallization phenomenon might be useful for the fabrication of low temperature polycrystalline‐Si thin film transistors, providing large‐grained Si films.

Method for manufacturing a semiconductor device using a catalyst

Abstract: A method for manufacturing a thin film transistor having a crystalline silicon layer as an active layer comprises the steps of disposing a solution containing a catalyst for promoting a crystallization of silicon in contact with an amorphous silicon film, crystallizing the amorphous silicon at a relatively low temperature and then improving the crystallinity by irradiating the film with a laser light. The concentration of the catalyst in the crystallized silicon film can be controlled by controlling the concentration of the catalyst in the solution.

Thin film transistor

Abstract: A thin film transistor comprises a dielectric substrate (1), a semiconductor layer (3) of poly-crystalline silicon layer having a drain region (8), an active gate region (4, 8-0), and a source region (7) placed on said substrate (1), a drain terminal (10) and a source terminal (10A) connected to said respective regions for external connection, a gate electrode (6) coupled with a part of said gate region (4) through a dielectric layer (4A), wherein length (d) of said gate electrode (6) is shorter than the length of gate region (4 plus 8-0), so that an offset region (8-0), where no gate electrode faces with said gate region, is produced.

High performance poly-Si TFTs fabricated using pulsed laser annealing and remote plasma CVD with low temperature processing

Abstract: Key technologies for fabricating polycrystalline silicon thin film transistors (poly-Si TFTs) at a low temperature are discussed. Hydrogenated amorphous silicon films were crystallized by irradiation of a 30 ns-pulsed XeCl excimer laser. Crystalline grains were smaller than 100 nm. The density of localized trap states in poly-Si films was reduced to 4/spl times/10/sup 16/ cm/sup -3/ by plasma hydrogenation only for 30 seconds. Remote plasma chemical vapor deposition (CVD) using mesh electrodes realized a good interface of SiO/sub 2//Si with the interface trap density of 2.0/spl times/10/sup 10/ cm/sup -2/ eV/sup -1/ at 270/spl deg/C. Poly-Si TFTs were fabricated at 270/spl deg/C using laser crystallization, plasma hydrogenation and remote plasma CVD. The carrier mobility was 640 cm/sup 2//Vs for n-channel TFTs and 400 cm/sup 2//Vs for p-channel TFTs. The threshold voltage was 0.8 V for n-channel TFTs and -1.5 V for p-channel TFTs. The leakage current of n-channel poly-Si TFTs was reduced from 2/spl times/10/sup -10/ A//spl mu/m to 3/spl times/10/sup -13/ A//spl mu/m at the gate voltage of -5 V using an offset gate electrode with an offset length of 1 /spl mu/m. >

Introduction to electronic devices

Abstract: Basics of Quantum Mechanics. Basics of Solid State Physics. Electrons and Holes in Semiconductors. Diodes and Contacts. Bipolar Junction Transistors. MOSFETs. Compound Semiconductor FETs and Thin Film Transistors (TFTs). Photonic Devices. Device Fabrication and Novel Devices. Appendices. Glossary. Index.

Field-effect transistor having a semiconductor layer made of an organic compound

Abstract: A field-effect transistor using a conjugated oligomer having an ionization potential of 4.8 eV or above in the semiconductor layer thereof works stably and has a long life-time and can be used in a liquid crystal display device as a switching element to give excellent contrast and good performances.

Transistor and process for fabricating the same

Abstract: A process for fabricating a thin film transistor, which comprises crystallizing an amorphous silicon film, forming thereon a gate insulating film and a gate electrode, implanting impurities in a self-aligned manner, adhering a coating containing a catalyst element which accelerates the crystallization of the silicon film, and annealing the resulting structure at a temperature lower than the deformation temperature of the substrate to activate the doped impurities. Otherwise, the catalyst element can be incorporated into the structure by introducing it into the impurity region by means of ion implantation and the like. Also a process for fabricating a thin film transistor, which comprises forming a gate electrode, a gate insulating film, and an amorphous silicon film on a substrate, implanting impurities into the amorphous silicon film to form source and drain regions as the impurity regions, introducing a catalyst element into the impurity region by adhering a coating containing the catalyst element of by means of ion doping and the like, and annealing the resulting structure at a temperature lower than the deformation temperature of the substrate to activate the doped impurities.

Method for forming polycrystalline thin film and method for fabricating thin-film transistor

Abstract: A method for forming a polycrystalline semiconductor thin film according to the present invention includes the steps of: forming a semiconductor thin film partially containing microcrystals serving as crystal nuclei for polycrystallization on an insulating substrate; and polycrystallizing the semiconductor thin film by laser annealing.

Method of making a semiconductor device having a gate all around type of thin film transistor

Abstract: A method of manufacturing a semiconductor device including forming an insulating film on a substrate; forming an opening in the insulating film by anisotropic etching; embedding a dummy member in the opening; forming a channel member over the insulating film and the dummy member; removing the dummy member to form a gap in the opening between the channel member and the substrate; and forming a thin film on the channel member and in the gap covering the channel member, the thin film being a control electrode of a transistor for forming channels on opposite sides of the channel member.

Transistor device employing crystallization catalyst

Abstract: A thin film transistor includes a crystallized amorphous silicon film having a gate insulating film and a gate electrode formed thereon. The device includes impurities implanted in a self-aligned manner and a catalyst that accelerates the crystallization of the silicon film. The catalyst is introduced in the silicon film by adhering a coating containing the catalyst element and annealing the resulting structure at a temperature lower than the deformation temperature of the substrate to activate the doped impurities. The catalyst element can also be incorporated into the silicon film by means of ion implantation and the like. Also disclosed is a thin film transistor, which comprises a gate electrode, a gate insulating film, an amorphous silicon film having impurities implanted therein to form source and drain regions as the impurity regions, and a catalyst element introduced into the impurity regions by adhering a coating containing the catalyst element or by means of ion doping and the like, wherein the resulting structure is annealed at a temperature lower than the deformation temperature of the substrate to activate the doped impurities.

Method for manufacturing a thin film transistor using catalyst elements to promote crystallization

Abstract: In a method for crystallizing an amorphous silicon film by a heat treatment that is effected for a duration of about 4 hours at about 550° C. using a catalyst element for accelerating the crystallization, the quantity of the catalyst element to be introduced into the amorphous silicon is precisely controlled. A resist mask 21 is formed on the surface of an amorphous silicon film 12 provided on a glass substrate 11, and an aqueous solution 14, e.g., an acetate solution, containing a catalyst element such as nickel at a concentration controlled in a range of from 10 to 200 ppm (need to be adjusted) is supplied dropwise thereto. After maintaining the state for a predetermined duration of time, the entire substrate is subjected to spin drying using a spinner 15. A thin film of crystalline silicon is finally obtained by applying heat treatment at 550° C. for a duration of 4 hours.

Electro-optical device constructed with thin film transistors

Abstract: An electro-optical device and a method for manufacturing the same are disclosed. The device comprises a pair of substrates and an electro-optical modulating layer (e.g. a liquid crystal layer having sandwiched therebetween, said pair of substrates consisting of a first substrate having provided thereon a plurality of gate wires, a plurality of source (drain) wires, and a pixel matrix comprising thin film transistors, and a second substrate facing the first substrate, wherein, among the peripheral circuits having established on the first substrate and being connected to the matrix wirings for the X direction and the Y direction, only a part of said peripheral circuits is constructed from thin film semiconductor devices fabricated by the same process utilized for an active device, and the rest of the peripheral circuits is constructed from semiconductor chips. The liquid crystal display device according to the present invention is characterized by that the peripheral circuits are not wholly fabricated into thin film transistors, but only those portions having a simple device structure, or those composed of a small number of devices, or those comprising an IC not easily available commercially, or those comprising an expensive integrated circuit, are fabricated by thin film transistors. According to the present invention, an electro-optical device is provided at an increased production yield with a reduced production cost.

Active matrix crystal display apparatus using thin film transistor

Abstract: In order to provide a liquid crystal display apparatus having bright image display and a preferable production yield, a gate insulating film under a transparent pixel electrode on a transparent substrate is provided with an aperture smaller than a plane area of the pixel electrode, a source electrode pattern under the pixel electrode is composed so as to cross the aperture, and thin film transistor (TFT) having a gate electrode of which end portion is tapered with a taper angle equal to or less than three times (where, less than 90°) of a taper angle at the end portion of a semiconductor pattern is provided.

Method of removing a catalyst substance from the channel region of a TFT after crystallization

Abstract: Method of fabricating a semiconductor device, such as a thin-film transistor, having improved characteristics and improved reliability. The method is initiated with formation of a thin amorphous silicon film on a substrate. A metallization layer containing at least one of nickel, iron, cobalt, and platinum is selectively formed on or under the amorphous silicon film so as to be in intimate contact with the silicon film, or these metal elements are added to the amorphous silicon film. The amorphous silicon film is thermally annealed to crystallize it. The surface of the obtained crystalline silicon film is etched to a depth of 20 to 200 Å, thus producing a clean surface. An insulating film is formed on the clean surface by CVD or physical vapor deposition. Gate electrodes are formed on the insulating film.

Semiconductor device including a silicon film having an irregular surface

Abstract: A thin film transistor with high performance and improved productivity is offered using crystalline silicon film. As the crystalline silicon film that constitutes the active layer of thin film transistor, the one which has irregularities of 100 to 700 Å in level difference is used. Such crystalline silicon film can be obtained by performing laser light irradiation.

Method of fabricating thin film semiconductor integrated circuit

Abstract: In a semiconductor integrated circuit, a plurality of thin film transistors (TFTs) are formed on the same substrate having an insulating surface. Since gate electrodes formed in the TFTs are electrically insulated each other, voltages are applied independently to gate electrodes in an electrolytic solution during an anodization, to form an anodic oxide in at least both sides of each gate electrode. A thickness of the anodic oxide is changed in accordance with characteristics of the TFT. A width of high resistance regions formed in an active layer of each TFT is changed by ion doping using the anodic oxide having a desired thickness as a mask.

Thin film transistor having crystalline semiconductor layer obtained by irradiation

Abstract: An amorphous semiconductor film having a thickness of 400Å or more is formed on an insulating surface and is wholly or selectively etched to form a region having a thickness 300Å or less. This is used as a channel-forming region in a TFT.

Method for fabricating thin film transistors

Abstract: In a fabrication of a semiconductor device, an amorphous semiconductor film is first formed on a substrate having an insulating surface. Then, a minute amount of catalyst elements for accelerating crystallization of the amorphous semiconductor film is supplied to at least a portion of a surface of the amorphous semiconductor film. A heat treatment is further conducted so that the supplied catalyst elements are diffused into the amorphous semiconductor film. Thus, the catalyst elements are introduced uniformly into the amorphous semiconductor film in a very minute amount or at a low concentration, resulting in polycrystallization of at least a portion of the amorphous semiconductor film. Utilizing the thus obtained crystalline semiconductor film on the substrate surface as an active region, a semiconductor device such as a TFT is fabricated. The introduction of the catalyst elements are conducted by various methods such as: a formation of a film containing a minute amount of the catalyst elements; application of a solution containing the catalyst elements in several spin coating cycles; diffusion of the catalyst elements through a buffer layer; dipping into a solution in which the catalyst elements are dissolved or dispersed; or formation of a plating layer containing the catalyst elements.

Semiconductor device having a plurality of crystalline thin film transistors

Abstract: A semiconductor circuit having a plurality of crystalline thin film transistors possessing different electrical characteristics which are formed on a substrate having an active matrix region and a driver circuit region. At least one first thin film transistor comprising a first crystalline silicon film is formed on the active matrix region of the substrate, while at least one second thin film transistor comprising a second crystalline silicon film is formed on the driver circuit region. The crystalline film of each of the first thin film transistors contains a catalyst element capable of promoting the crystallization of silicon at a higher concentration than the crystalline film of each of the second thin film transistors.

Electron mobility behavior in extremely thin SOI MOSFET's

Abstract: Extremely thin-film SOI MOSFET's with silicon film thickness down to 8 nm have been fabricated without inducing serious source/drain series resistance by employing a gate recessed structure. The influence of extremely thin silicon film on the electron mobility has been experimentally studied. The results show an abrupt mobility decrease in the device with less than 10 nm silicon film thickness. The measured mobility versus effective field below 10 nm silicon film thickness shows that a different scattering mechanism is involved in carrier conduction in 10 nm t/sub si/ region. The reasons for the mobility decrease have been examined from a device simulation and measurements. >

Band structures of organic thin-film transistor materials

Abstract: We report extended Huckel theory (EHT) band structure calculations for the high-temperature polymorph of α-6T (α-sexithiophene) and C60, two organic materials that have shown promising device characteristics, as the active element in thin-film transistors (TFTs). We also report calculations for α-3T and κ-(ET)2Cu(NCS)2[where ET = bis(ethylenedithio)tetrathiafulvalene] for comparison purposes. Both α-6T/HT and C60 show well developed band dispersions. Whereas C60 is an isotropic three-dimensional (3D) molecular solid, α-6T/HT shows a strongly 2D electronic structure, and the band structure is quite similar to that of the ET organic superconductors such as κ-(ET)2Cu(NCS)2. Factors important in determining the mobilities of organic semiconductors are reviewed.

Process for forming an integrated circuit comprising non-volatile memory cells and side transistors of at least two different types, and corresponding IC

Abstract: A process for forming an integrated circuit calls for the provision of at least one matrix of non-volatile memory cells including an intermediate dielectric multilayer comprising a lower silicon oxide layer, an intermediate silicon nitride layer and an upper silicon oxide layer. The process calls for the simultaneous provision in zones peripheral to the memory cells of at least one first and one second transistor type each having a gate dielectric of a first and a second thickness respectively. After formation of the floating gate of the cells with a gate oxide layer and a polycrystalline silicon layer and the formation of the lower silicon oxide layer and of the intermediate silicon nitride layer, the process in accordance with the present invention includes removal of said layers from the zones peripheral to the matrix, and formation of a first silicon oxide layer over the substrate in the areas of both types of transistor. The process further includes removal of the preceding layer from areas assigned only to the transistors of the second type; deposition of said upper silicon oxide layer over the memory cells, over the first silicon oxide layer in the areas of the transistors of the first type and over the substrate in the areas of the transistors of the second type; and formation of a second silicon oxide layer in the areas of both types of peripheral transistors.

Method of producing and arrangement containing self-amplifying dynamic MOS transistor memory cells

Abstract: To produce an arrangement containing self-amplifying dynamic MOS transistor memory cells which each comprise a selection transistor, a memory transistor and a diode structure, the selection transistor and the memory transistor being connected in series via a common nodal point and the diode structure being connected between the common nodal point and the gate electrode (10) of the memory transistor, the selection transistor and the memory transistor are formed as vertical MOS transistors. For this purpose a vertical sequence of suitably doped zones (2, 3, 4) in which trenches (5, 6) are produced and which are provided with gate dielectric (7, 8) and gate electrode (9, 10) is produced, in particular, by LPCVD epitaxy or by molecular-beam epitaxy.

Advanced TFT SRAM cell technology using a phase-shift lithography

Abstract: An advanced TFT memory cell technology has been developed for making high-density and high-speed SRAM cells. The cell is fabricated using a phase-shift lithography that enables patterns with spaces of less than 0.25 /spl mu/m to be made using the conventional stepper. Cell area is also reduced by using a small cell-ratio and a parallel layout for the transistor. Despite the small cell-ratio, stable operation is assured by using advanced polysilicon PMOS TFT's for load devices. The effect of the Si/sub 3/N/sub 4/ multilayer gate insulator on the on-current and the influence of the channel implantation are also investigated. To obtain stable operation and extremely low stand-by power dissipation, a self-aligned offset structure for the polysilicon PMOS TFT is proposed and demonstrated. A leakage current of only 2 fA/cell and an on-/off-current ratio of 4.6/spl times/10/sup 6/ are achieved with this polysilicon PMOS TFT in a memory cell, which is demonstrated in a experimental 1-Mbit CMOS SRAM chip that has an access time of only 7 ns. >

Process for formation of thin film transistor liquid crystal display

Abstract: A process for formation of a thin film transistor liquid crystal display is disclosed, in which an etch-back type 3-mask process or an etch stopper type 4-mask process is applied, so that the semiconductor layer of the thin film transistor can be isolated from the data line. Consequently, the optical leakage current which aggravates the performance of the transistor is inhibited. Further, the data line is composed of a material which has a low chemical reactivity with ITO, so that a corrosion due to a chemical reaction between the data line and ITO can be eliminated.