Showing papers on "Thin-film transistor published in 1998"

Temperature-independent transport in high-mobility pentacene transistors

Abstract: The charge-carrier transport mechanism in the organic semiconductor pentacene is explored using thin-film transistor structures. The variation of the field-effect mobility with temperature differs from sample to sample, ranging from thermally activated to temperature-independent behavior. This result excludes thermally activated hopping as the fundamental transport mechanism in pentacene thin films, and suggests that traps and/or contact effects may strongly influence the observed characteristics. These results also indicate that field-effect transistors may not be appropriate vehicles for illuminating basic transport mechanisms in organic materials.

Manufacturing method of active matrix substrate, active matrix substrate and liquid crystal display device

Abstract: A method of manufacturing an active matrix substrate is provided that uses a technique of transferring a thin film device. In forming thin film transistors and pixel electrodes on an original substrate before transfer, an insulator film such as an interlayer insulation film or the like, is previously removed before the pixel electrodes are formed. Further, the original substrate is separated by exfoliation to transfer the device to a transfer material to cause the pixel electrodes to partially appear in the surface or the vicinity of the surface of the device. This portion permits application of a voltage to a liquid crystal through the pixel electrode.

Organic smart pixels

Abstract: The fabrication and characteristics of organic smart pixels are described. The smart pixel reported in this letter consists of a single organic thin-film field effect transistor (FET) monolithically integrated with an organic light-emitting diode. The FET active material is a regioregular polythiophene. The maximum optical power emitted by the smart pixel is about 300 nW/cm2 corresponding to a luminance of ∼2300 cd/m2.

Organic thin-film transistors for organic light-emitting flat-panel display backplanes

Abstract: The performance of organic thin-film transistors (OTFTs) has improved significantly in the last several years and it now appears likely that they will find application in low-cost large-area electronic applications. Active-matrix displays are of special interest and integration of OTFTs with organic light-emitting devices (OLEDs) in all-organic displays is particularly attractive. The device requirements for active-matrix OLED displays are very similar to those of active-matrix liquid crystal displays (AMLCDs) and can be satisfied with OTFTs fabricated using stacked pentacene active layers. Such devices have demonstrated field-effect mobility near 1.5 cm/sup 2//V/spl middot/s, on/off current ratio near 10/sup 8/, near-zero threshold voltage, and subthreshold slope less than 1.6 V/decade. These characteristics are similar to those obtained with hydrogenated amorphous silicon (a-Si:H) devices and such devices would allow the use of polymeric substrates with advantages in weight, ruggedness, and cost compared to glass substrates currently used with a-Si:H devices in AMLCDs.

Electroluminescence device, electroluminescence apparatus, and production methods thereof

Abstract: An electroluminescence device having a transistor substrate comprising drain electrode pads, each being connected to a drain of a thin film transistor, and capacitors connected to the respective drain electrode pads, and an electroluminescence substrate comprising pairs of electrodes and electroluminescence members each provided between a pair of electrodes, arranged along a plurality of rows and columns, wherein the thin film transistor substrate and the electroluminescence substrate are placed opposite to each other so that the drain electrode pads and the electroluminescence members are opposed to each other, and wherein each drain electrode pad and one electrode of a pair of electrodes are connected through an adhesive electric connection member.

Thin-film semiconductor device including a semiconductor film with high field-effect mobility

Abstract: A thin film transistor includes: a substrate; a gate electrode, a source electrode and a drain electrode formed above the substrate; and an insulating film and a semiconductor film formed between the gate electrode, and the source electrode and the drain electrode, wherein the semiconductor film includes an i-type silicon film, and a portion of the semiconductor film within 50 nm from the insulating film has a microcrystalline structure having a conductivity of 5×10 −10 S/cm or more.

Synthesis, Solubility, and Field-Effect Mobility of Elongated and Oxa-Substituted α,ω-Dialkyl Thiophene Oligomers. Extension of “Polar Intermediate” Synthetic Strategy and Solution Deposition on Transistor Substrates

Abstract: Our investigation of thiophene oligomers as organic thin film transistor (TFT) semiconductors is extended to the hexamer with dodecyl and octadecyl end-substituents and with side chains containing ethereal oxygens. Two thiophene tetramers are studied as well. All of the new compounds are prepared via polar, monosubstituted half-oligomers that are purified, further elaborated, and dimerized. Properties are reported in comparison with the previously reported dihexyl compounds. All of the compounds form ordered films with orientation perpendicular to the substrate. For the hexamers, the longer chains decrease the TFT mobility of evaporated films, while the oxygens have very little electronic effect, even though the oxygen does cause an approximate doubling of the solubility. A tetramer with an ether side chain has a mobility below 0.01 cm2/Vs. Films were also cast from dilute solution and showed mobilities at or above 0.01 cm2/Vs in several cases. This casting process may be useful in devising all-liquid-pha...

Thin-film transistors based on organic conjugated semiconductors

Abstract: The use of organic semiconductors as active layers in thin-film transistors has raised in the recent years a large interest, both for the fundamental understanding of the charge transport processes in organic materials, and also for the potential applications of these devices in the new field of flexible electronics. Short conjugated oligomers have been shown to possess much higher field-effect mobilities than their parent conjugated polymers. The origin of such increase in the efficiency of charge transport is mainly attributed to the close-packing and long-range structural organization displayed in thin films of conjugated oligomers. The various routes for controlling this organization are described, which allow to realize liquid crystal-like two-dimensional structures for these semiconductors, whose carrier mobility has now become equivalent to that of amorphous silicon. It is also shown that the effect of conjugation length on carrier mobility is not as critical as previously thought, but the associated increase of the band gap energy effects the efficiency of charge injection at the metal/semiconductor interface. This problem can be answered by realizing a local doping of the semiconductor, which allows the injection of charge to operate through an efficient tunneling mechanism. Organic-based thin-film transistors have now become viable devices.

Electrical instability of hydrogenated amorphous silicon thin-film transistors for active-matrix liquid-crystal displays

Abstract: We investigated the threshold voltage shifts (ΔVT) of inverted-staggered hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) induced by steady-state (dc) and pulsed (ac) gate bias-temperature-stress (BTS) conditions. Our study showed that, for an equivalent effective-stress-time, ΔVT has an apparent pulse-width dependence under negative BTS conditions–the narrower the pulse width, the smaller the ΔVT. This gate-bias pulse-width dependence is explained by an effective-carrier-concentration model, which relates ΔVT for negative pulsed gate-bias stress to the concentration of mobile carriers accumulated in the conduction channel along the a-Si:H/gate insulator interface. In addition, our investigation of the methodology of a-Si:H TFT electrical reliability evaluation indicates that, instead of steady-state BTS, pulsed BTS should be used to build the database needed to extrapolate ΔVT induced by a long-term display operation. Using these experimental results, we have shown that a-Si:H TFTs have a satisfactory electrical reliability for a long-term active-matrix liquid-crystal display (AMLCD) operation.

A Novel Phase-Modulated Excimer-Laser Crystallization Method of Silicon Thin Films

Abstract: We propose a novel excimer-laser crystallization method that uses a phase-shift mask for large-grain growth of Si thin films on the glassy substrate. Due to interference effects of the laser light, the phase difference of light at the mask results in spatial modulation of light intensity at the sample surface, which triggers the lateral grain growth. Grains as large as 7 µm could be grown by a single-shot irradiation.

Method for forming a semiconductor device

Abstract: In accordance with embodiments of the present invention a trench-level dielectric film (26) and a via-level dielectric film (24) are formed overlying a semiconductor device substrate (10). A via opening (42) is etched in the trench-level dielectric film with a first etch chemistry that has a higher etch selectivity to the trench-level dielectric film (26) than to the via-level dielectric film (24). A trench opening (54) is patterned in a photoresist layer (52) overlying the trench-level dielectric film (26). The via-level dielectric film (24) is etched with a second etch chemistry to extend the via opening (42) into the via-level dielectric film (24). The trench-level dielectric film (26) is etched to form a trench opening.

CMOS integrated circuit including forming doped wells, a layer of intrinsic silicon, a stressed silicon germanium layer where germanium is between 25 and 50%, and another intrinsic silicon layer

Abstract: An integrated CMOS circuit, and method for producing same, including a semiconductor substrate having a p-channel MOS transistor and an n-channel MOS transistor formed therein and having a first silicon layer, a stressed Si 1-x Ge x layer and a second silicon layer which are preferably grown by selective epitaxy. In an ON state, a buried channel is formed in the stressed Si 1-x Ge x layer in the p-channel MOS transistor and a surface channel is formed in the second silicon layer in the n-channel MOS transistor.

a-Si:H TFTs made on polyimide foil by PE-CVD at 150 °C

Abstract: We have fabricated high-performance amorphous silicon thin-film transistors (a-Si:H TFTs) on 2 mil. (51 µm) thick polyimide foil substrates. The TFT structure was deposited by r.f.-excited plasma enhanced chemical vapor deposition (PECVD). All TFT layers, including the gate silicon nitride, the undoped, and the n+ amorphous silicon were deposited at a substrate temperature of 150°C. The transistors have inverted-staggered back-channel etch structure. The TFT off-current is ∼ 10−12 A, the on-off current ratio is > 107, the threshold voltage is 3.5 V, the sub-threshold slope is ∼ 0.5V/decade, and the linear-regime mobility is ∼ 0.5 cm2V−1s−1. We compare the mechanical behavior of a thin film on a stiff and on a compliant substrate. The thin film stress can be reduced to one half by changing from a stiff to a compliant substrate. A new equation is developed for the radius of curvature of thin films on compliant substrates.

Latch-up free power mos-bipolar transistor

Abstract: A MOS bipolar transistor is provided which includes a silicon carbide npn bipolar transistor formed on a bulk single crystal n-type silicon carbide substrate and having an n-type drift layer and a p-type base layer. Preferably the base layer is formed by epitaxial growth and formed as a mesa. A silicon carbide nMOSFET is formed adjacent the npn bipolar transistor such that a voltage applied to the gate of the nMOSFET causes the npn bipolar transistor to enter a conductive state. The nMOSFET has a source and a drain formed so as to provide base current to the npn bipolar transistor when the bipolar transistor is in a conductive state. Also included are means for converting electron current flowing between the source and the drain into whole current for injection into the p-type base layer. Means for reducing field crowding associated with an insulating layer of said nMOSFET may also be provided.

Fabrication and room-temperature characterization of a silicon self-assembled quantum-dot transistor

Abstract: A quantum-dot transistor based on silicon self-assembled quantum dots has been fabricated The device shows staircases and oscillations in the drain current at room temperature These data are interpreted as due to single electron tunneling through the dots located in the shortest current path between the source and the drain electrodes The dot size calculated from the data is ∼7 nm, which is consistent with the size of the self-assembled dots incorporated in the transistor

Kink-free polycrystalline silicon double-gate elevated-channel thin-film transistors

Abstract: The authors report the characterization and analysis of a novel double-gate elevated-channel thin-film transistor (ECTFT) fabricated using polycrystalline silicon. The transistor has a thin channel and thick source/drain regions with a double-gate control. Using this structure, the kink effect in the I-V characteristics of a conventional TFT is completely eliminated, and leakage current at zero gate bias is reduced by over 15 times. The elimination of the kink effect and the significant reduction in leakage current are obtained due to the reduction in lateral electric field at the channel/drain junction region. Two-dimensional (2-D) device simulations are used to study the electric field reduction mechanism in the structure. Experimental results on the forward conduction and gate transfer characteristics of the structure are also presented.

High-performance germanium-seeded laterally crystallized TFTs for vertical device integration

Abstract: Increasing chip complexity and area has resulted in interconnect delay becoming a significant fraction of overall chip delay. Continued scaling of design rules will further aggravate this problem. Vertical integration of devices will enable a substantial reduction in chip size and thus in interconnect delay. We present a novel technique to achieve vertical integration of CMOS devices. Germanium is used as a seeding agent at the source and/or drain of thin film transistors (TFTs) to laterally crystallize amorphous silicon films, resulting in high-performance devices. This is achieved through the formation of large grain polysilicon with a precise control over the location of the grain. TFTs have been demonstrated offering substantial performance improvement over conventional unseeded polycrystalline TFTs, with demonstrated mobilities as high as 300 cm2/V-s. The process is fully CMOS compatible and has a low thermal budget. It is highly scalable to deep-submicron technologies and, with suitable optimization, should enable the production of high-performance, high density, vertically integrated ULSI.

Method for making a complementary metal gate electrode technology

Abstract: A method for making a circuit device that includes a first transistor having a first metal gate electrode overlying a first gate dielectric on a first area of a semiconductor substrate. The first gate electrode has a work function corresponding to the work function of one of P-type silicon and N-type silicon. The circuit device also includes a second transistor coupled to the first transistor. The second transistor has a second metal gate electrode over a second gate dielectric on a second area of the semiconductor substrate. The second gate metal gate electrode has a work function corresponding to the work function of the other one of P-type silicon and N-type silicon.

Top-Gate Staggered Amorphous Silicon Thin-Film Transistors: Series Resistance and Nitride Thickness Effects

Abstract: Top-gate staggered hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) were fabricated over large-area glass substrates using a selective phosphorus-treatment (PT) of indium-tin-oxide (ITO) source/drain electrodes. The ohmic contact between a-Si:H and ITO had a specific contact resistivity of about 0.18 Ωcm2. For a 100-µm channel length TFT, the source/drain series resistance contributes less than 5% of the total drain-to-source resistance. This contribution increases to about 25% for a 10-µm channel length TFT. Our study also indicated that the interface quality of a-Si:H/a-SiNx:H is amorphous silicon nitride (a-SiNx:H) and a-Si:H thickness independent and dependent, respectively. Effective interface state densities of about 1.5×1012 cm-2eV-1 and 3.2×1012 cm-2eV-1 were obtained for top-gate TFTs with a 1300 and 300 A thick a-Si:H films, respectively. Channel conductance activation energy of about 0.1 eV was measured for this top-gate TFT with 300 A a-Si:H.

Active-matrix liquid crystal display

Abstract: On a TFT substrate, a TFT using a low-temperature poly silicon thin film as an active layer is formed and a plurality of pixel electrodes are formed over the TFT and its electrode wiring, with an interlayer insulating layer between. In a common electrode formed on an opposite substrate opposite the TFT substrate with a liquid crystal layer between, an alignment controlling window for the liquid crystal is formed at a predetermined position opposite each of the pixel electrodes. A wide viewing angle is achieved by dividing an alignment area of liquid crystal molecules in one pixel area. The liquid crystal layer is vertically aligned and can be operated at a low driving voltage obtained by a poly silicon TFT by including fluorine liquid crystal molecules having negative dielectric anisotropy and fluorine side chains in the liquid crystal.

Semiconductor thin film, method of producing the same, apparatus for producing the same, semiconductor device and method of producing the same

Abstract: A semiconductor device having a high field effect mobility is produced by increasing the particle diameter of a silicon thin film of a polycrystalline silicon thin film transistor. On a transparent insulating substrate (201) is formed an insulating film of a two-layer structure comprising a lower insulating film (202) contacting with the transparent insulating substrate (201) and having a heat conductivity larger than that of an upper insulating film (203) that is formed thereon. The upper insulating film (203) is patterned into a plurality of stripes. Then, an amorphous silicon thin film (204) is formed on the patterned insulating film. Thereafter, the amorphous silicon thin film (204) is transformed into a polycrystalline silicon thin film (210) by scanning the amorphous silicon thin film (204) with a laser beam in parallel with the stripes of the upper insulating film (203).

Semiconductor device having doped polycrystalline layer

Abstract: An insulated gate field effect transistor comprises a silicon channel region. The silicon is crystallized by heat annealing while a suitable metal element such as nickel helps the crystallization. The crystallization proceeds in the silicon film laterally from the portion where the nickel is directly introduced. The TFT is arranged in such a manner that the source-drain direction of the TFT is aligned with the direction of the crystal growth or intersects with the crystal growth direction at a desired direction.

High-performance thin-film transistors fabricated using excimer laser processing and grain engineering

Abstract: High-performance polysilicon thin-film transistors (TFTs) are fabricated using an excimer laser to recrystallize the undoped channel and dope the source-drain regions. Using a technique we call "grain engineering" we are able to control grain microstructure using laser parameters. Resulting polysilicon films are obtained with average grain sizes of /spl sim/4-9/spl times/m in sub-100 nm thick polysilicon films without substrate heating during the laser recrystallization process. Using a simple four-mask self-aligned aluminum top-gate structure, we fabricate TFTs in these films. By combining the grain-engineered channel polysilicon regions with laser-doped source-drain regions, TFTs are fabricated with electron mobilities up to 260 cm/sup 2//Vs and on/off current ratios greater than 10/sup 7/. To our knowledge, these devices represent the highest performance laser-processed TFTs reported to date fabricated without substrate heating or hydrogenation.

Semiconductor nonvolatile memory device and method of production of same

Abstract: A semiconductor nonvolatile memory device capable of lowering an operation voltage such as an erase voltage and capable of lowering costs and a method of production of the same, wherein a thin film transistor acting as the memory transistor is formed with a semiconductor layer 31b having a channel formation region formed on an insulating substrate 10 made of glass or plastic, a charge storing layer 32a formed on the semiconductor layer, a control gate 33a formed above the charge storing layer, and source and drain regions formed connected to the channel formation region.

Formation of integrated circuit structure using one or more silicon layers for implantation and out-diffusion in formation of defect-free source/drain regions and also for subsequent formation of silicon nitride spacers

Abstract: A process is described for using a silicon layer as an implant and out-diffusion layer, for forming defect-free source/drain regions in a semiconductor substrate, and also for subsequent formation of silicon nitride spacers. A nitrogen-containing dopant barrier layer is first formed over a single crystal semiconductor substrate by nitridating either a previously formed gate oxide layer, or a silicon layer formed over the gate oxide layer, to form a barrier layer comprising either a silicon, oxygen, and nitrogen compound or a compound of silicon and nitrogen. The nitridating may be carried out using a nitrogen plasma followed by an anneal. A polysilicon gate electrode is then formed over this barrier layer, and the exposed portions of the barrier layer remaining are removed. An amorphous silicon layer of predetermined thickness is then formed over the substrate and polysilicon gate electrode. This amorphous layer is then implanted with a dopant capable of forming a source/drain region in the underlying silicon substrate by subsequent diffusion of the implanted dopant from the amorphous silicon layer into the substrate. The structure is then annealed to diffuse the dopant from the implanted silicon layer into the substrate to form the desired source/drain regions and into the polysilicon gate electrode to dope the polysilicon. The annealing further serves to cause the amorphous silicon layer to crystalize to polycrystalline silicon (polysilicon). In one embodiment, the polysilicon layer is then nitridized to convert it to a silicon nitride layer which is then patterned to form silicon nitride spacers on the sidewalls of the polysilicon gate electrode to electrically insulate the gate electrode from the source/drain regions. The process may be further modified to also create LDD or HDD source/drain regions in the substrate (depending on the concentration of the dopant), using multiple implants into the same silicon layer or by the sequential use of several silicon layers, each of which is used as an implantation and out-diffusion layer.

Excimer-laser-induced lateral-growth of silicon thin-films

Abstract: A new excimer-laser crystallization method called the "gradient method", has been developed for large-grain growth of Si thin-films on glass. The method is based on a spatial modulation of an incident light intensity, which triggers the lateral grain growth. Grains of size as large as 5 µm were grown by a single shot irradiation at a substrate temperature of 500°C. By combining a step motion of the sample and the proposed method, the grain could be enlarged drastically.

Transfer method of thin-film device, the thin-film device, thin-film integrated circuit device, active matrix substrate, liquid crystal display device, and electronic apparatus

Abstract: PROBLEM TO BE SOLVED: To provide simple manufacturing process and a low-cost thin-film device, while laminating order at manufacturing of a thin-film device is maintained, by allowing transfer of the thin-film device to a substrate at actual use. SOLUTION: With a first separation layer such as amorphous silicon provided on a substrate which allows transmission of laser light, a thin-film device 140 such as TFT(thin-film-transistor) is formed on the substrate. A second separation layer 160 is formed on the thin-film device 140, over which a primary transfer body 180 is formed. By removing the substrate with a weakened bonding strength of the first separation layer under light irradiation, the thin-film device is primary-transferred to a primary-transfer body. Furthermore a secondary transfer body 200 is jointed to the underside surface of an exposed thin-film device via a bonding layer 190, and a second separation layer is fused with heat for weakened bonding strength, to have the primary-transfer body removed. Thus, the thin-film device is secondary-transferred to the secondary-transfer body.

Cross coupled thin film transistors and static random access memory cell

Abstract: A pair of thin film transistors formed in adjacent layers of polysilicon. The gate of the first TFT and the source, drain and channel regions of the second TFT are formed in the first polysilicon layer. The source, drain and channel regions of the first TFT and the gate of the second TFT are formed in the second polysilicon layer. A dielectric layer is interposed between the first and second polysilicon layers. The first TFT gate overlaps the second TFT drain region in the first polysilicon layer and the second TFT gate overlaps the first TFT drain region in the second polysilicon layer. In another aspect of the invention, two TFTs are incorporated into a SRAM memory cell. The memory cell includes: (i) a bit line; (ii) an access transistor having a first source/drain and a second source/drain, the first source/drain being electrically connected to the bit line; (iii) a parasitic diode formed between the second source/drain of the access transistor and the substrate; (iv) a pull down transistor having a source, drain, channel and gate; (v) a first TFT having a source, drain, channel and gate, the first TFT gate being coupled to a power supply voltage V cc through an active load device comprising a second TFT having a source, drain, channel and gate, and to a voltage not greater than ground through the pull down transistor; and (vi) a storage node for storing a high voltage representative of a first digital data state or a low voltage representative of a second digital state, the storage node being coupled to the bit line through the access transistor, to the substrate through the parasitic diode, to the pull down transistor gate and to the power supply voltage V cc through the first TFT.