scispace - formally typeset
Search or ask a question

Showing papers on "Thin-film transistor published in 2001"


Patent
23 Mar 2001
TL;DR: In this paper, a thin film transistor with a ZnO film as active layer is presented, which suppresses a leak current of a gate insulating film and obtains good transistor characteristics.
Abstract: (57) Abstract: Provided is a thin film transistor including a ZnO film as a semiconductor active layer, which suppresses a leak current of a gate insulating film and obtains good transistor characteristics. A thin film transistor T1 formed on an insulating substrate 1. On the substrate 1, a gate electrode 2, a gate insulating film 31, an intermediate layer 32, and a semiconductor active layer 4 made of ZnO are sequentially formed. On the semiconductor active layer 4, a source electrode 5 and a drain electrode 6 are formed. ing. The mid layer 32 It is provided to prevent mobile ions (Zn ions) from entering the gate insulating film 32 from the semiconductor active layer (ZnO film) 4 and is made of silicon nitride.

1,124 citations


Patent
Kazufumi Ogawa1
15 Nov 2001
TL;DR: By imparting conductivity to specified regions of a semiconductor material film 4 formed over a substrate 2, the semiconductor materials film 4, in addition to being processed into channel portions (active layers) 4 a, source portions 4 b, and drain portions 4 c of TFTs, is processed into conductive elements containing pixel electrodes 10 connected to the drain portion 4 c.
Abstract: By imparting conductivity to specified regions of a semiconductor material film 4 formed over a substrate 2 , the semiconductor material film 4 , in addition to being processed into channel portions (active layers) 4 a , source portions 4 b , and drain portions 4 c of TFTs, is processed into conductive elements containing pixel electrodes 10 connected to the drain portions 4 c . Regions composed of an intrinsic semiconductor to which impurities have not been added serve as the active layers (channel regions) of the TFTs and regions to which impurities have been added serve as conductive elements. When transparent electrodes are formed, an oxide semiconductor is used.

1,067 citations


Journal ArticleDOI
06 Dec 2001-Nature
TL;DR: In this paper, an active-matrix display with 64 × 64 pixels, each driven by a thin-film transistor with a solution-processed polymer semiconductor, is described.
Abstract: The handling of grey levels by these large displays paves the way for electronic paper. The main advantages of using soluble semiconductive polymers in microelectronic devices are ease of processing1,2,3 and mechanical flexibility4. Here we describe an active-matrix display with 64 × 64 pixels, each driven by a thin-film transistor with a solution-processed polymer semiconductor. In a significant step towards low-cost flexible displays, this polymer-dispersed liquid-crystal arrangement gives a reflective, low-power display with paper-like contrast, which can handle 256 grey levels while being refreshed at video speed.

518 citations


Journal ArticleDOI
TL;DR: In this paper, the integration of active matrix polysilicon TFT technology with organic light emitting diode (OLED) displays has been investigated with the goal of producing displays of uniform brightness.
Abstract: The integration of active matrix polysilicon TFT technology with organic light emitting diode (OLED) displays has been investigated with the goal of producing displays of uniform brightness. This work identifies and addresses several process integration issues unique to this type of display which are important in achieving bright and uniform displays. Rapid thermal processing has been incorporated to achieve uniform polysilicon microstructure, along with silicides to reduce parasitic source and drain series resistance. Using these processes, TFT drain current nonuniformity has been reduced below 5% for 90% of the devices. This work also introduces transition metals to produce low resistance contacts to ITO and to eliminate hillock formation in the aluminum metallization. These processes, along with spin on glasses for planarization, have been used to produce functional active matrix arrays for OLED displays. The final array pixel performance is also presented.

377 citations


Journal ArticleDOI
01 Jan 2001
TL;DR: In this paper, an analysis of the electrical properties of pentacene OTFTs fabricated on flexible polyethylene naphthalate (PEN) film is presented. Butts et al. used an octadecyltrichlorosilosilane vapor prime to prepare the SiO/sub 2/ gate dielectric surface for the deposition of the Pentacene layer.
Abstract: We present an analysis of the electrical characteristics of pentacene OTFTs fabricated on flexible polyethylene naphthalate (PEN) film. Nickel, silicon dioxide, and palladium were deposited by ion-beam sputtering and patterned by photolithography and lift-off to form the gate electrodes, the gate dielectric layer, and the source and drain contacts, respectively. An octadecyltrichlorosilane vapor prime was used to prepare the SiO/sub 2/ gate dielectric surface for the deposition of the pentacene layer, which was deposited by thermal evaporation and patterned using a water-soluble, photo-patterned polyvinyl alcohol layer.

337 citations


Journal ArticleDOI
TL;DR: In this article, self-assembled monolayers (SAMs) are used to change the surface energy of the metal electrodes and morphology of the pentacene subsequently grown on the electrodes.
Abstract: Pentacene-based organic field effect transistors (FETs) exhibit enormous potential as active elements in a number of applications. One significant obstacle to commercial application remains: no completely lithographic process exists for forming high-performance devices. Processing constraints prevent electrodes from being lithographically patterned once the semiconductor is deposited, but depositing the electrodes before the semiconductor leads to low-performance transistors. By using self-assembled monolayers (SAMs) to change the surface energy of the metal electrodes and morphology of the pentacene subsequently grown on the electrodes, high-performance transistors may be formed using a process compatible with lithographic definition of the source and drain electrodes.

308 citations


Journal ArticleDOI
TL;DR: In this article, the authors describe the monolithic integration of rubber-stamped thin-film organic transistors with polymer-dispersed liquid crystals (PDLCs) to create a multipixel, flexible display with plastic substrates.
Abstract: This letter describes the monolithic integration of rubber-stamped thin-film organic transistors with polymer-dispersed liquid crystals (PDLCs) to create a multipixel, flexible display with plastic substrates. We report the electro-optic switching behavior of the PDLCs as driven by the organic transistors, and we show that our displays operate robustly under flexing and have a contrast comparable to that of newsprint.

284 citations


Patent
19 Jun 2001
TL;DR: In this article, a CMOS inverter having a heterostructure including a Si substrate, a relaxed Si1-xGex layer on the Si substrate and a strained surface layer on said relaxed Si 1-xgex layer is presented.
Abstract: A CMOS inverter having a heterostructure including a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained surface layer on said relaxed Si1-xGex layer; and a pMOSFET and an nMOSFET, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained surface layer. Another embodiment provides an integrated circuit having a heterostructure including a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained layer on the relaxed Si1-xGex layer; and a p transistor and an n transistor formed in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor are interconnected in a CMOS circuit.

246 citations


Journal ArticleDOI
TL;DR: In this paper, a pentacene active layer organic thin film transistors (OTFTs) were fabricated on heavily doped, thermally oxidized single-crystal silicon substrates with linear field effect mobility greater than 0.5 cm/sup 2/V-s at a drain-source voltage of -0.1 V.
Abstract: We have fabricated pentacene active layer organic thin film transistors (OTFTs) using chemically-modified source and drain contacts with improved contact and linear region characteristics. OTFTs fabricated on heavily doped, thermally oxidized single-crystal silicon substrates have linear field-effect mobility greater than 0.5 cm/sup 2//V-s at a drain-source voltage of -0.1 V, on/off current ratio greater than 10/sup 7/, and subthreshold slope as low as 0.7 V/decade.

214 citations


Journal ArticleDOI
TL;DR: In this paper, the effect of light incident on a polymer-based field effect transistor was investigated and the utility of light as an additional controlling parameter of the transistor state was demonstrated.
Abstract: We report the effect of light incident on a polymer-based field-effect transistor and demonstrate the utility of light as an additional controlling parameter of the transistor state. The transistor exhibits large photosensitivity indicated by the sizable changes in the drain–source current at low levels of light. The response here is considerably higher than that from existing organic/polymeric planar, two-terminal photodetectors due to an additional process contributing to the enhancement. The light-responsive polymer transistor opens up a device-architecture concept for polymer-based electronics.

211 citations


Journal ArticleDOI
TL;DR: In this article, a ZnO thin film was deposited on a Si wafer having an oxidized SiO2 layer using a chemical solution deposition process and was applied to a bottom-gate type thin film transistor (TFT).
Abstract: A ZnO thin film was deposited on a Si wafer having an oxidized SiO2 layer using a chemical solution deposition process and was applied to a bottom-gate type thin film transistor (TFT). The films prepared by combined heating at 600° and 900°C exhibited typical enhancement-type TFT characteristics with electrons as carriers. The low heating temperature around 600°C degraded the insulating properties of the SiO2 layer but high temperature annealing recovered that.

Journal ArticleDOI
TL;DR: The state of the art of large-area low-temperature TFT-LCDs is reported in this paper, where possible applications and future trends are discussed together with the technologies required to achieve this goal.

Patent
Kevin L. Denis1, Yu Chen1, Paul Drzaic1, Joseph M. Jacobson1, Peter T. Kazlas1 
17 Apr 2001
TL;DR: In this paper, a polyphenylene polyimideal substrate was used for the formation of high quality silicon semiconductor layers, allowing the use of processing temperatures in excess of 300°C during the processes used to form the transistors.
Abstract: Transistors are formed by depositing at least one layer of semiconductor material on a substrate comprising a polyphenylene polyimide. The substrate permits the use of processing temperatures in excess of 300° C. during the processes used to form the transistors, thus allowing the formation of high quality silicon semiconductor layers. The substrate also has a low coefficient of thermal expansion, which closely matches that of silicon, thus reducing any tendency for a silicon layer to crack or delaminate.

Patent
29 Oct 2001
TL;DR: In this article, a method for improving the performance of an organic thin film field effect transistor comprising the steps of: (a) forming a transistor structure having patterned source and drain electrodes; and (b) treating the patterns with a thiol compound having the formula, RSH, wherein R is a linear or branched, substituted or unsubstituted, alkyl, alkenyl, cycloalkyl or aromatic containing from about 6 to about 25 carbon atoms, under conditions that are effective in forming a self-assembled monolayer of said thiol
Abstract: A method for improving the performance of an organic thin film field effect transistor comprising the steps of: (a) forming a transistor structure having patterned source and drain electrodes; and (b) treating the patterned source and drain electrodes with a thiol compound having the formula, RSH, wherein R is a linear or branched, substituted or unsubstituted, alkyl, alkenyl, cycloalkyl or aromatic containing from about 6 to about 25 carbon atoms under conditions that are effective in forming a self-assembled monolayer of said thiol compound on said electrodes. Organic thin film transistor structures containing the self-assembled monolayer of the present invention are also disclosed.

Patent
Brian S. Doyle1, Brian Roberds1
09 Nov 2001
TL;DR: In this article, a transistor having a source, a drain, and a channel region is formed on the substrate, wherein the at least one void is in the channel region of the transistor.
Abstract: A method of improving short channel effects in a transistor. First, a substance is implanted in a substrate. The substrate is then annealed such that the implanted substance forms at least one void in the substrate. Then, a transistor having a source, a drain, and a channel region is formed on the substrate, wherein the at least one void is in the channel region of the transistor.

Journal ArticleDOI
TL;DR: In this paper, a simple, low-cost, and parallel fabrication of patterned organic-inorganic thin-film transistors (TFTs) by microcontact printing a molecular template on the substrate surface prior to film deposition is reported.
Abstract: We report the simple, low-cost, and parallel fabrication of patterned organic–inorganic thin-film transistors (TFTs) by microcontact printing a molecular template on the substrate surface prior to film deposition. We printed molecules with hydrophobic tail groups on the gate oxide surfaces of TFTs to chemically, differentiate the substrate surface and confine the self-assembly of thin films, deposited from solutions flooded across the entire surface, to the transistor channels. TFTs are fabricated with good device characteristics and no current leakage. This process is more general to the patterning of other solution-deposited thin-film materials.

Patent
28 Aug 2001
TL;DR: In this article, an amorphous semiconductor film is etched so that a width of a narrowest portion thereof is 100 μm or less, thereby forming island semiconductor regions.
Abstract: An amorphous semiconductor film is etched so that a width of a narrowest portion thereof is 100 μm or less, thereby forming island semiconductor regions. By irradiating an intense light such as a laser into the island semiconductor regions, photo-annealing is performed to crystallize it. Then, of end portions (peripheral portions) of the island semiconductor regions, at least a portion used to form a channel of a thin film transistor (TFT), or a portion that a gate electrode crosses is etched, so that a region that the distortion is accumulated is removed. By using such semiconductor regions, a TFT is produced.

Journal ArticleDOI
01 Jun 2001
TL;DR: In this article, a lightweight electronic ink display on a conformable active-matrix array sheet was constructed using amorphous silicon thin film transistors and capacitors on a stainless steel foil substrate.
Abstract: We have fabricated prototype lightweight electronic ink displays on a conformable active-matrix array sheet. The active matrix arrays were built using amorphous silicon thin film transistors and capacitors on a stainless steel foil substrate. These prototype displays possess a resolution of 40 dpi, with 52×64 pixels (active area 1.3 inch × 1.6 inch) on a 1.8 inch × 2.0 inch stainless steel substrate. The display possesses an ink on paper appearance, with wide-viewing angle and good contrast ratio.

Journal ArticleDOI
TL;DR: In this article, the effect of surface order on the orientation and mobility of pentacene was investigated and the surface order was created using monolayers and polymers that are normally used to align liquid crystals.
Abstract: We have investigated the effect of surface order on the orientation and mobility of pentacene. The surface order was created using monolayers and polymers that are normally used to align liquid crystals. Rubbed polyvinylalcohol layers were found to align approximately 27% of the pentacene grains within a 30° range. When introduced in a thin-film transistor, they were found to enhance the saturation current by a factor of 2.5. A mechanism for this enhancement is proposed.

Patent
19 Jul 2001
TL;DR: In this paper, a process for producing an adhered SOI substrate without causing cracking and peeling of a single-crystal silicon thin film was proposed, which consists of selectively forming a porous silicon layer in a singlecrystal semiconductor substrate, adding hydrogen into the single-cysdrastic silicon substrate to form a hydrogen-added layer, adhering the singlecsydrastic semiconductor substratum to a supporting substrate, separating the polysilicon substrate at the hydrogen-add layer by thermal annealing, performing thermal-annealing again to stabilize
Abstract: A process for producing an adhered SOI substrate without causing cracking and peeling of a single-crystal silicon thin film. The process consists of selectively forming a porous silicon layer in a single-crystal semiconductor substrate, adding hydrogen into the single-crystal semiconductor substrate to form a hydrogen-added layer, adhering the single-crystal semiconductor substrate to a supporting substrate, separating the single-crystal semiconductor substrate at the hydrogen-added layer by thermal annealing, performing thermal annealing again to stabilize the adhering interface, and selectively removing the porous silicon layer to give single-crystal silicon layer divided into islands.

Patent
05 Feb 2001
TL;DR: In this paper, the authors proposed a method of forming a dielectric stack device having a plurality of layers, which comprises the steps of providing a silicon substrate, forming a metal-oxide layer on a silicon oxide layer which is formed on the silicon substrate and performing an annealing with respect to the metaloxide layer and the silicon oxide layers until a silicate layer is formed to replace the metal oxide layer.
Abstract: A method of forming a dielectric stack device having a plurality of layers comprises the steps of providing a silicon substrate, forming a metal-oxide layer on a silicon oxide layer which is formed on the silicon substrate, and performing an annealing with respect to the metal-oxide layer and the silicon oxide layer until a silicate layer is formed to replace the metal-oxide layer and the silicon oxide layer is removed, wherein the annealing is performed at a temperature between about 800° C. and about 1000° C. for a time period between about 1 second and about 10 minutes. After forming the silicon oxide layer on the silicon substrate, the metal-oxide layer may be deposited on the silicon oxide layer. Alternatively, the metal-oxide layer may be deposited on the silicon substrate, and the silicon oxide layer grows between the metal-oxide layer and the silicon substrate. The metal-based oxide is preferably an Yttrium-based oxide.

Journal ArticleDOI
TL;DR: In this paper, two organic thin-film transistors with SiO2 and ferroelectric PbZrTiO3 (PZT) gate insulator are compared and the fabrication of the devices is described and their electrical properties estimated.
Abstract: In this letter, two organic thin-film transistors with SiO2 and ferroelectric PbZrTiO3 (PZT) gate insulator are compared. The fabrication of the devices is described and their electrical properties estimated. The PZT-based devices show better performance: Low driving voltage, high Ion/Ioff ratio, etc. Moreover, a memory effect is reported in correlation with ferroelectric properties of PZT thin films.

Patent
04 Dec 2001
TL;DR: In this paper, a CMOS inverter having a heterostructure including a Si substrate, a relaxed Si1-xGex layer; and a pMOSFET and an nMOFSET are formed in the strained surface layer.
Abstract: A CMOS inverter having a heterostructure including a Si substrate, a relaxed Si1-xGex layer; and a pMOSFET and an nMOSFET, wherein the channel of said pMOSFET and the channel of the nMOFSET are formed in the strained surface layer. Another embodiment provides an integrated circuit having a heterostructure including a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained layer on the relaxed Si1-xGex layer; and a p transistor and an n transistor formed in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor are interconnected in a CMOS circuit.

Proceedings ArticleDOI
02 Dec 2001
TL;DR: In this article, a stable scanning DPSS CW laser lateral crystallization without introduction of thermal damage to 300/spl times/300 mm/sup 2/ glass substrates with process temperature below 450/spl deg/C.
Abstract: We have developed high performance poly-Si TFTs, which have comparable performance to that of [100] Si-MOSFETs, by using a stable scanning DPSS CW laser lateral crystallization without introduction of thermal damage to 300/spl times/300 mm/sup 2/ glass substrates with process temperature below 450/spl deg/C.

Journal ArticleDOI
TL;DR: In this article, two improved four thin-film transistors (TFTs) pixel electrode circuits based on hydrogenated amorphous silicon (a-Si:H) technology have been designed.
Abstract: Two improved four thin-film-transistors (TFTs) pixel electrode circuits based on hydrogenated amorphous silicon (a-Si:H) technology have been designed. Both circuits can provide a constant output current level and can be automatically adjusted for TFT threshold voltage variations. The circuit simulation results indicate that an excellent linearity between the output current and input current can be established. An output current level higher than /spl sim/5 /spl mu/A can be achieved with these circuits. This current level can provide a pixel electrode brightness higher than 1000 cd/m/sup 2/ with the organic light-emitting device (OLED) having an external quantum efficiency of 1%. These pixel electrode circuits can potentially be used for the active-matrix organic light-emitting displays (AM-OLEDs).

Journal ArticleDOI
TL;DR: In this article, the silicon filling of a very small indentation fabricated in the substrate will act as a seed for lateral growth of large grains, followed by a vertical growth phase during which grains become occluded.
Abstract: Single-crystal thin-film transistors on nonrefractory materials such as glass can be realized if monocrystalline islands of sufficient sizes can be grown at a predetermined position. By artificially controlling the super-lateral growth phenomenon observed in excimer-laser crystallization, this could be achieved. In this letter, we present such a method in which the silicon filling of a very small indentation fabricated in the substrate will act as a seed for lateral growth of large grains. When the melt is deep in these indentations, lateral growth is preceded by a vertical growth phase during which grains become occluded, so that a high yield of monocrystalline islands is obtained.

Patent
Katsuya Anzai1, Komiya Naoyaki1
28 Sep 2001
TL;DR: In this article, one or more EL elements for controlling the amount of current supplied from a power supply line VL is provided between an organic EL element ( 50 ) and the power supply lines VL, where the EL element is placed so that its channel length direction is parallel to the longitudinal direction of the pixel.
Abstract: One or more element driving TFTs ( 20 ) for controlling the amount of current supplied from a power supply line VL is (are) provided between an organic EL element ( 50 ) and the power supply line VL. The element driving TFT ( 20 ) is placed so that its channel length direction is parallel to the longitudinal direction of the pixel, the extension direction of a data line for supplying a data signal to a switching TFT ( 10 ) for controlling the element driving TFT ( 20 ), or the scan direction of laser annealing for polycrystallizing the active layer ( 16 ) of the TFT ( 20 ).

Patent
30 Jan 2001
TL;DR: In this article, a method for making a field effect transistor (FET) is described, which includes a stripe trench extending from the major surface of a semiconductor substrate into the substrate to a predetermined depth.
Abstract: A field effect transistor device and a method for making a field effect transistor device are disclosed. The field effect transistor device includes a stripe trench extending from the major surface of a semiconductor substrate into the semiconductor substrate to a predetermined depth. The stripe trench contains a semiconductor material of the second conductivity type to form a PN junction at an interface formed with the semiconductor substrate.

Journal ArticleDOI
Gee Sung Chae1
TL;DR: In this paper, a 2.0-4.0 wt% ZnO-alloyed ITO film (named ITZO) is proposed for the pixel electrodes of a TFT-LCD designed with specifications for high resolution and large display size.
Abstract: To keep up with the current development trends of thin film transistor liquid-crystal display (TFT-LCD), two major requirements must be satisfied in the transparent conducting oxide (TCO)-meterial itself. First, there must be no etch residue after TCO patterning and good etch selectivity against low electrical resistivity metals. Second, there must be good chemical endurance of the TCO material to secure a good electrical signal that is transported from the controller to the TFT-LCD by way of contact between the TCO and the tape carrier package (TCP). To obtain a new TCO material to achieve the kind of trade-off behavior that a TCO film has, the method in which ZnO is alloyed into indium tin oxide (ITO) was studied. It was determined that the 2.0–4.0 wt% ZnO-alloyed ITO film (named ITZO) is desirable in order to obtain a well-defined patterning ability and the stable TCP-contact property simultaneously. It is concluded that ITZO film can replace ITO and IZO for the pixel electrodes of a TFT-LCD designed with specifications for high resolution and large display size.

Patent
22 Mar 2001
TL;DR: In this article, the authors proposed a method for forming a semiconductor device with a metallic substrate, which can improve the reliability and life-time of the semiconductor devices by having high thermal and electrical conductivity.
Abstract: The present invention provides a method for forming a semiconductor device with a metallic substrate. The method comprises providing a semiconductor substrate. At least a semiconductor layer is formed on the semiconductor substrate. A metallic electrode layer is formed on the semiconductor layer. The metallic substrate is formed on the metallic electrode layer and the semiconductor substrate is removed. The metallic substrate has advantages of high thermal and electrical conductivity, that can improve the reliability and life-time of the semiconductor device.