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Thin-film transistor

About: Thin-film transistor is a research topic. Over the lifetime, 48425 publications have been published within this topic receiving 680879 citations. The topic is also known as: TFT.


Papers
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Journal ArticleDOI
TL;DR: In this article, the authors present a process for manufacturing printable thin-film transistors that is based on solution processing and direct inkjet printing of polymer semiconductors, dielectrics, and conductors, as well as inorganic nanoparticle conductors.
Abstract: We present a process for manufacturing printable thin-film transistors (TFTs) that is based on solution processing and direct inkjet printing of polymer semiconductors, dielectrics, and conductors, as well as inorganic nanoparticle conductors. We show that the high device yield, uniformity, and resolution required for thin-film electronic applications can be achieved by using a substrate that contains a surface energy pattern to control the flow and spreading of inkjet droplets. This technique overcomes many of the limitations of current inkjet printing technology related to its limited droplet placement accuracy. We demonstrate the potential of this printing-based TFT manufacturing process with the fabrication of 50 dpi active-matrix, polymer dispersed liquid-crystal and Gyricon Smartpaper electronic paper displays.

146 citations

Patent
26 Oct 1992
TL;DR: In this paper, a semiconductor memory device is formed having a substrate (12). A diffusion (14) is formed within the substrate, and a first vertical transistor stack (122) was formed.
Abstract: A semiconductor memory device is formed having a substrate (12). A diffusion (14) is formed within the substrate (12). A first vertical transistor stack (122) is formed. A second vertical transistor stack (124) is formed. The first vertical transistor stack (122) has a transistor (100) underlying a transistor (104). The second vertical transistor stack (124) has a transistor (102) underlying a transistor (106). The transistors (100 and 104) are connected in series, and the transistors (102 and 106) are connected in series. In a preferred form, transistors (100 and 102) are electrically connected as latch transistors for a semiconductor memory device and transistors (106 and 104) are connected as pass transistors. Two vertical stacks (126 and 128) form electrical interconnections (118 and 120) and resistive devices (134 and 138) for the semiconductor memory device.

146 citations

Journal ArticleDOI
18 Jul 2012-ACS Nano
TL;DR: In this paper, the authors integrate high-purity semiconducting carbon nanotube films with a custom-designed hybrid inorganic-organic gate dielectric to achieve a synergistic combination of materials that circumvents conventiona...
Abstract: In the past decade, semiconducting carbon nanotube thin films have been recognized as contending materials for wide-ranging applications in electronics, energy, and sensing. In particular, improvements in large-area flexible electronics have been achieved through independent advances in postgrowth processing to resolve metallic versus semiconducting carbon nanotube heterogeneity, in improved gate dielectrics, and in self-assembly processes. Moreover, controlled tuning of specific device components has afforded fundamental probes of the trade-offs between materials properties and device performance metrics. Nevertheless, carbon nanotube transistor performance suitable for real-world applications awaits understanding-based progress in the integration of independently pioneered device components. We achieve this here by integrating high-purity semiconducting carbon nanotube films with a custom-designed hybrid inorganic–organic gate dielectric. This synergistic combination of materials circumvents conventiona...

146 citations

Journal ArticleDOI
TL;DR: In this article, the velocity and viscous damping of capillary waves are computed and discussed during short-pulse laser crystallization of amorphous silicon on quartz, surface roughening occurs via the freezing of the capillary wave excited in the silicon melt.
Abstract: During short‐pulse laser crystallization of amorphous silicon on quartz, surface roughening occurs via the freezing of capillary waves excited in the silicon melt. The velocity and viscous damping of these capillary waves is computed and discussed. Volume change of the silicon during solidification appears to drive liquid silicon toward the last areas of solidification. Film thickness variation observed by transmission electron microscopy and atomic force microscopy shows increased film thickness at grain boundaries, and vertices of single pulse irradiated films. This effect is most pronounced within a narrow laser fluence regime wherein large lateral grain growth occurs. For 100 nm thick amorphous silicon films on quartz, this regime extends from approximately 520 to 560 mJ/cm2; standard deviation roughness can be as large as 40 nm. These effects have important implications for large area thin film transistor manufacturing.

146 citations

Patent
10 Sep 2012
TL;DR: In this article, a display device consisting of a thin film transistor, a second layer, a pixel electrode, a connection line, a third layer, and a common electrode is discussed.
Abstract: Discussed is a display device. The display device includes a thin film transistor, a first protective layer, a second protective layer, a pixel electrode, a connection line, a third protective layer, and a common electrode.

145 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023341
2022918
2021640
20201,333
20192,015
20182,080