Thin-film transistor

About: Thin-film transistor is a research topic. Over the lifetime, 48425 publications have been published within this topic receiving 680879 citations. The topic is also known as: TFT.

Method for forming dielectric stack without interfacial layer

Abstract: A method of forming a dielectric stack device having a plurality of layers comprises the steps of providing a silicon substrate, forming a metal-oxide layer on a silicon oxide layer which is formed on the silicon substrate, and performing an annealing with respect to the metal-oxide layer and the silicon oxide layer until a silicate layer is formed to replace the metal-oxide layer and the silicon oxide layer is removed, wherein the annealing is performed at a temperature between about 800° C. and about 1000° C. for a time period between about 1 second and about 10 minutes. After forming the silicon oxide layer on the silicon substrate, the metal-oxide layer may be deposited on the silicon oxide layer. Alternatively, the metal-oxide layer may be deposited on the silicon substrate, and the silicon oxide layer grows between the metal-oxide layer and the silicon substrate. The metal-based oxide is preferably an Yttrium-based oxide.

High-performance thin-film transistors in low-temperature crystallized LPCVD amorphous silicon films

Abstract: Thin-film transistors (TFT's) were fabricated in low-temperature (550°C) crystallized amorphous LPCVD silicon films. The performance of these devices was found to depend upon the deposition temperature. Low threshold voltages and effective mobilities as high as 32 cm2/V.s are reported for devices fabricated in 150-nm-thick films with maximum processing temperature of 860°C. The performance of these devices is shown to be far superior to devices fabricated in as-deposited polycrystalline silicon films.

Method of manufacturing thin film transistor

Abstract: In a method of manufacturing a thin film transistor, when impurity ions are introduced in a channel region between source and drain regions in a semiconductor layer, an insulator layer is first formed on the semiconductor layer. Then, impurity ions generated on high frequency discharge are introduced through the insulator layer into the semiconductor layer under a specified acceleration voltage. Then, the introduction depth of impurities and the amount of the impurities to be introduced in the channel region can be controlled or the threshold voltage of the thin film transistor can be controlled. This method can be applied to a large substrate.

Influence of Channel Layer Thickness on the Electrical Performances of Inkjet-Printed In-Ga-Zn Oxide Thin-Film Transistors

Abstract: Inkjet-printed In-Ga-Zn oxide (IGZO) thin-film transistors (TFTs) with bottom-gate bottom-contact device architecture are studied in this paper. The impact of the IGZO film thickness on the performance of TFTs is investigated. The threshold voltage, field-effect mobility, on and off drain current, and subthreshold swing are strongly affected by the thickness of the IGZO film. With the increase in film thickness, the threshold voltage shifted from positive to negative, which is related to the depletion layer formed by the oxygen absorbed on the surface. The field-effect mobility is affected by the film surface roughness, which is thickness dependent. Our results show that there is an optimum IGZO thickness, which ensures the best TFT electrical performance. The best result is from a 55-nm-thick IGZO TFT, which showed a field-effect mobility in the saturation region of 1.41 cm2/V·s, a threshold voltage of 1 V, a drain current on/off ratio of approximately 4.3 × 107, a subthreshold swing of 384 mV/dec, and an off-current level lower than 1 pA.