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Thin-film transistor

About: Thin-film transistor is a research topic. Over the lifetime, 48425 publications have been published within this topic receiving 680879 citations. The topic is also known as: TFT.


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Patent
29 Sep 2008
TL;DR: In this article, Phosphorus is added to a semiconductor layer by using a pattern made of a conductive film as a mask to form an N-type impurity region in a self-alignment manner.
Abstract: The object of the present invention is to form a low-concentration impurity region with good accuracy in a top gate type TFT. Phosphorus is added to a semiconductor layer by using a pattern made of a conductive film as a mask to form an N-type impurity region in a self-alignment manner. A positive photoresist is applied to a substrate so as to cover the pattern and then is exposed to light applied to the back of the substrate and then is developed, whereby a photoresist 110 is formed. The pattern is etched by using the photoresist pattern as an etching mask to form a gate electrode. A channel forming region, a source region, a drain region, and low-concentration impurity regions, are formed in the semiconductor layer in a self-alignment manner by using the gate electrode as a doping mask.

101 citations

Journal ArticleDOI
TL;DR: In this paper, high performance amorphous silicon thin-film transistors (a-Si:H TFTs) were fabricated on 2 mil. (51 µm) thick polyimide foil substrates.
Abstract: We have fabricated high-performance amorphous silicon thin-film transistors (a-Si:H TFTs) on 2 mil. (51 µm) thick polyimide foil substrates. The TFT structure was deposited by r.f.-excited plasma enhanced chemical vapor deposition (PECVD). All TFT layers, including the gate silicon nitride, the undoped, and the n+ amorphous silicon were deposited at a substrate temperature of 150°C. The transistors have inverted-staggered back-channel etch structure. The TFT off-current is ∼ 10−12 A, the on-off current ratio is > 107, the threshold voltage is 3.5 V, the sub-threshold slope is ∼ 0.5V/decade, and the linear-regime mobility is ∼ 0.5 cm2V−1s−1. We compare the mechanical behavior of a thin film on a stiff and on a compliant substrate. The thin film stress can be reduced to one half by changing from a stiff to a compliant substrate. A new equation is developed for the radius of curvature of thin films on compliant substrates.

101 citations

Journal ArticleDOI
TL;DR: In this paper, the effects of source/drain series resistance on amorphous gallium-indium-doped zincoxide (a-GIZO) thin film transistors (TFTs) were investigated.
Abstract: In this letter, we investigated the effects of source/drain series resistance on amorphous gallium-indium-doped zinc-oxide (a-GIZO) thin film transistors (TFTs). A linear least square fit of a plot of the reciprocal of channel resistance versus gate voltage yields a threshold voltage of 3.5 V and a field-effect mobility of about 13.5 cm2/Vldrs. Furthermore, in a-GIZO TFTs, most of the current flows in the distance range of 0-0.5 mum from the channel edge and shorter than that in a-Si:H TFTs. Moreover, unlike a-Si:H TFTs, a-GIZO TFTs did not show an intersection point, because they did not contain a highly doped ohmic (n+) layer below the source/drain electrodes.

101 citations

Patent
10 Jun 1998
TL;DR: In this article, a MOS bipolar transistor is provided which includes a silicon carbide npn bipolar transistor formed on a bulk single crystal n-type silicon carbides substrate and having an n type drift layer and a p-type base layer.
Abstract: A MOS bipolar transistor is provided which includes a silicon carbide npn bipolar transistor formed on a bulk single crystal n-type silicon carbide substrate and having an n-type drift layer and a p-type base layer. Preferably the base layer is formed by epitaxial growth and formed as a mesa. A silicon carbide nMOSFET is formed adjacent the npn bipolar transistor such that a voltage applied to the gate of the nMOSFET causes the npn bipolar transistor to enter a conductive state. The nMOSFET has a source and a drain formed so as to provide base current to the npn bipolar transistor when the bipolar transistor is in a conductive state. Also included are means for converting electron current flowing between the source and the drain into whole current for injection into the p-type base layer. Means for reducing field crowding associated with an insulating layer of said nMOSFET may also be provided.

101 citations

Journal ArticleDOI
TL;DR: In this paper, the authors investigated the illuminated behaviors of InGaZnO thin film transistors with and without a SiOx passivation and found that more interface states were generated during SiOx layer deposition by plasma-enhanced-chemical-vapor-deposition.
Abstract: This paper investigates the illuminated behaviors of InGaZnO thin film transistors with and without a SiOx passivation. For the passivated device, more interface states were generated during SiOx passivation layer deposition by plasma-enhanced-chemical-vapor-deposition. The enhanced trap-assisted photoexcited hole generation induces source side barrier lowering and causes an apparent subthreshold stretch-out phenomenon. However, for the unpassivated device, the fact that the threshold voltage shift in ambient oxygen is lower than in vacuum under light illumination suggests oxygen desorption and readsorption occurs simultaneously, which is consistent with the accelerated recovery rate in oxygen ambiance.

101 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023341
2022918
2021640
20201,333
20192,015
20182,080