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Thin-film transistor

About: Thin-film transistor is a research topic. Over the lifetime, 48425 publications have been published within this topic receiving 680879 citations. The topic is also known as: TFT.


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Journal ArticleDOI
TL;DR: In this article, the authors report on the contact resistances for pentacene thin film transistors with two different designs: top and bottom contact configurations (referred to as TC and BC TFTs, respectively) for two different contact metals (gold and palladium).
Abstract: We report on the contact resistances for pentacene thin film transistors with two different designs: top and bottom contact configurations (referred to as TC and BC TFTs, respectively) for two different contact metals (gold and palladium). The extraction was done based on the dependencies of the channel resistances on the gate length and gate voltage. The extracted gold TC TFT contact resistance depends on VGS, but shows no dependence on the drain bias. The TC TFT contact resistance is comparable to or exceeds the channel resistance for channels shorter than approximately 10 μm. The contact resistance of BC TFTs depends both on gate and drain bias. We propose a circuit simulating the BC TFT contact resistance and verify the circuit applicability by extracting and comparing the TFT channel resistances at different drain voltages. Our results reveal an important role played by contact resistances and provide an accurate model of the contact phenomena suitable for implementation in Spice or other circuit simulators.

312 citations

Journal ArticleDOI
TL;DR: In this article, the field effect mobility of organic thin-film transistors (OTFTs) was measured using top-contact devices and the results indicated that the mobility saturates when 6 monolayers of pentacene are deposited on the gate dielectric, SiO2.
Abstract: The dependence of the field-effect mobility of organic thin-film transistors (OTFT) was measured using top-contact devices. OTFTs were fabricated by vacuum sublimation of pentacene on thermally oxidized silicon wafers to form films with nominal thickness between 2 and 25 monolayers. The deposition was carried out at a low rate and the substrate was heated in order to yield high-quality films. The results indicate that the mobility saturates when 6 monolayers of pentacene are deposited on the gate dielectric, SiO2.

311 citations

Journal ArticleDOI
TL;DR: The most important instability mechanism in amorphous silicon-silicon nitride thin-film transistors is charge trapping in the silicon nitride layer, which leads to a threshold voltage shift (ΔVT).
Abstract: The most important instability mechanism in amorphous silicon‐silicon nitride thin‐film transistors is charge trapping in the silicon nitride layer, which leads to a threshold voltage shift (ΔVT). We have measured the time, temperature, and gate voltage dependence of ΔVT and conclude that the rate limiting process, in the charge transfer from semiconductor to insulator, is the conduction in the nitride by variable‐range hopping. The threshold shift (under positive bias) is temperature dependent with an activation energy of 0.3 eV. This activation energy is identified with the mean hop energy required to inject charge deep into the silicon nitride at the low applied fields appropriate to transistor operation.

308 citations

Journal ArticleDOI
TL;DR: In this article, self-assembled monolayers (SAMs) are used to change the surface energy of the metal electrodes and morphology of the pentacene subsequently grown on the electrodes.
Abstract: Pentacene-based organic field effect transistors (FETs) exhibit enormous potential as active elements in a number of applications. One significant obstacle to commercial application remains: no completely lithographic process exists for forming high-performance devices. Processing constraints prevent electrodes from being lithographically patterned once the semiconductor is deposited, but depositing the electrodes before the semiconductor leads to low-performance transistors. By using self-assembled monolayers (SAMs) to change the surface energy of the metal electrodes and morphology of the pentacene subsequently grown on the electrodes, high-performance transistors may be formed using a process compatible with lithographic definition of the source and drain electrodes.

308 citations

Journal ArticleDOI
TL;DR: A first principles stick-percolation-based transport model provides a simple, yet quantitative framework to interpret the sometimes counterintuitive transport parameters measured in single-walled carbon nanotubes in thin film type transistor structures.
Abstract: Gate-modulated transport through partially aligned films of single-walled carbon nanotubes (SWNTs) in thin film type transistor structures are studied experimentally and theoretically. Measurements are reported on SWNTs grown by chemical vapor deposition with systematically varying degrees of alignment and coverage in transistors with a range of channel lengths and orientations perpendicular and parallel to the direction of alignment. A first principles stick-percolation-based transport model provides a simple, yet quantitative framework to interpret the sometimes counterintuitive transport parameters measured in these devices. The results highlight, for example, the dramatic influence of small degrees of SWNT misalignment on transistor performance and imply that coverage and alignment are correlated phenomena and therefore should be simultaneously optimized. The transport characteristics reflect heterogeneity in the underlying anisotropic metal-semiconductor stick-percolating network and cannot be reproduced by classical transport models.

308 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023341
2022918
2021640
20201,333
20192,015
20182,080