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Thin-film transistor

About: Thin-film transistor is a research topic. Over the lifetime, 48425 publications have been published within this topic receiving 680879 citations. The topic is also known as: TFT.


Papers
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Journal ArticleDOI
TL;DR: In this article, a new fabrication process for polycrystalline silicon thin film transistors on 7059 glass substrates is reported, which has the advantages of short processing time and low processing temperature (≤600°C).
Abstract: A new fabrication process for polycrystalline silicon thin film transistors on 7059 glass substrates is reported. This unique fabrication process has the advantages of short processing time and low processing temperature (≤600 °C). The processing is based on the key step of using an ultrathin Pd layer, introduced to the surface of the glass prior to the deposition of an a‐Si:H film, to reduce the crystallization time and temperature. It is also based on using an electron cyclotron resonance hydrogen plasma to reduced the passivation time. The n‐channel TFTs produced by this new fabrication process have mobilities of 20 cm2/V s, and off‐currents of 0.5 pA/μm.

207 citations

Journal ArticleDOI
TL;DR: In this paper, a high-performance organic thin-film transistor array fabricated on a flexible paper substrate is demonstrated, using poly(3-hexylthiophene) as an active layer.
Abstract: We demonstrate a high-performance organic thin-film transistor array fabricated on a flexible paper substrate. As a water and chemical barrier layer, 6-/spl mu/m-thick parylene has been coated on the paper substrate by using the vacuum deposition. The parylene layer protects the paper substrate from becoming damp during the wet chemical process. Using poly (3-hexylthiophene) as an active layer, a high-performance organic transistor with field effect mobility up to 0.086 cm/sup 2//V/spl middot/s and an on/off ratio of 10/sup 4/ can be achieved. Organic transistors built on a cheap paper substrate open a channel for future applications in flexible and disposable electronics with extremely low-cost.

207 citations

Patent
19 Jul 1999
TL;DR: In this paper, a circuit including at least five thin film transistors (TFTs) which are provided with an approximately M-shaped semiconductor region for a single pixel electrode and gate lines and a capacitances line which cross the M-shape semiconductor regions, is used as a switching element.
Abstract: In an active matrix display device, a circuit including at least five thin film transistors (TFTs) which are provided with an approximately M-shaped semiconductor region for a single pixel electrode and gate lines and a capacitances line which cross the M-shaped semiconductor region, is used as a switching element. Each of the TFT have offset regions and lightly doped drain (LDD) regions. Then, by supplying a selection signal to the gate lines, the TFTs are operated, thereby writing data to the pixel, while a suitable voltage is supplied to the capacitance line, a channel is formed thereunder and it becomes a capacitor. Thus the amount of discharge from the pixel electrode is reduced by the capacitor.

206 citations

Journal ArticleDOI
TL;DR: In this article, a type of thin-film transistor that uses aligned arrays of thin (submicron) ribbons of single-crystal silicon created by lithographic patterning and anisotropic etching of bulk silicon wafers was introduced.
Abstract: This letter introduces a type of thin-film transistor that uses aligned arrays of thin (submicron) ribbons of single-crystal silicon created by lithographic patterning and anisotropic etching of bulk silicon (111) wafers. Devices that incorporate such ribbons printed onto thin plastic substrates show good electrical properties and mechanical flexibility. Effective device mobilities, as evaluated in the linear regime, were as high as 360cm2V−1s−1, and on/off ratios were >103. These results may represent important steps toward a low-cost approach to large-area, high-performance, mechanically flexible electronic systems for structural health monitors, sensors, displays, and other applications.

206 citations

Patent
28 Feb 2006
TL;DR: An integrated circuit and methods for its manufacture are provided in this article, where a bulk silicon substrate (20) consisting of a first region (64, 66) of (100) crystalline orientation and a second region (66, 64) of(110) orientation is presented.
Abstract: An integrated circuit and methods for its manufacture are provided. The integrated circuit (20) comprises a bulk silicon substrate (24) having a first region (64, 66) of (100) crystalline orientation and a second region (66, 64) of (110) crystalline orientation. A layer (62) of silicon on insulator overlies a portion of the bulk silicon substrate. At least one field effect transistor (96, 98) is formed in the layer (62) of silicon on insulator, at least one P-channel field effect transistor (90, 92) is formed in the second region (66, 64) of (110) crystalline orientation, and at least one N-channel field effect transistor (90, 92) is formed in the first region (64, 66) of (100) crystalline orientation.

206 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023341
2022918
2021640
20201,333
20192,015
20182,080