Thin-film transistor

About: Thin-film transistor is a research topic. Over the lifetime, 48425 publications have been published within this topic receiving 680879 citations. The topic is also known as: TFT.

Low temperature thin film transistor process, device property, and device stability improvement

Abstract: A method and apparatus for forming a thin film transistor is provided. A gate dielectric layer is formed, which may be a bilayer, the first layer deposited at a low rate and the second deposited at a high rate. In some embodiments, the first dielectric layer is a silicon rich silicon nitride layer. An active layer is formed, which may also be a bilayer, the first active layer deposited at a low rate and the second at a high rate. The thin film transistors described herein have superior mobility and stability under stress.

Constant-Voltage-Bias Stress Testing of a-IGZO Thin-Film Transistors

Abstract: Constant-voltage-bias (VDS = VGS = 30 V) stress measurements are performed for a period of 105 s on thin-film transistors (TFTs) with amorphous indium-gallium-zinc-oxide (IGZO) channel layers fabricated via RF sputtering using a postdeposition annealing temperature of 200degC, 250degC, or 300degC. Thermal silicon dioxide is employed as a TFT bottom-gate insulator. All SiO2/IGZO TFTs tested exhibit the following: 1) a positive rigid log(ID)- VGS transfer curve shift; 2) a continuous drain-current decrease over the entire stress duration; and 3) recovery of the log(ID)-VGS transfer curve toward the prestressed state when the stressed TFT is left unbiased in the dark at room temperature for an extended period of time. The SiO2/IGZO TFTs subjected to a higher postdeposition annealing temperature are more stable. A small (and typically negligible) amount of clockwise hysteresis is present in the log(ID) -VGS transfer curves of IGZO TFTs. These instability and hysteresis observations are consistent with a SiO2/ IGZO TFT instability mechanism involving electron trapping within the IGZO channel layer.

Method of increasing the mobility of MOS transistors by use of localized stress regions

Abstract: A method of modifying the mobility of a transistor. First, a substance is implanted into a substrate. The substrate is then annealed such that the implanted substance forms at least one void in the substrate. Then, a transistor is formed on the substrate.

Amorphous In–Ga–Zn–O coplanar homojunction thin-film transistor

Abstract: A fabrication process of coplanar homojunction thin-film transistors (TFTs) is proposed for amorphous In–Ga–Zn–O (a-IGZO), which employs highly doped contact regions naturally formed by deposition of upper protection layers made of hydrogenated silicon nitride (SiNX:H). The direct deposition of SiNX:H reduced the resistivity of the semiconductive a-IGZO layer down to 6.2×10−3 Ω cm and formed a nearly ideal Ohmic contact with a low parasitic source-to-drain resistance of 34 Ω cm. Simple evaluation of field-effect mobilities (μsat) overestimated their values especially for short-channel TFTs, while the channel resistance method proved that μsat was almost constant at 9.5 cm2 V−1 s−1.

Semiconductor device including active matrix circuit

Abstract: There is provided a combination of doping process and use of side walls which allows the source and drain of a thin film transistor of an active matrix circuit to be doped with only one of N-type and P-type impurities and which allows the source and drain of a thin film transistor used in a peripheral circuit of the same conductivity type as that of the thin film transistor of the active matrix circuit to include both of N-type and P-type impurities. Also, a thin film transistor in an active matrix circuit has offset regions by using side walls, and another thin film transistor in a peripheral circuit has a lightly doped region by using side walls.