Threshold voltage

About: Threshold voltage is a research topic. Over the lifetime, 36543 publications have been published within this topic receiving 485574 citations.

Electronic transport properties of amorphous indium-gallium-zinc oxide semiconductor upon exposure to water

Abstract: The effect of water exposure on amorphous indium-gallium-zinc oxide (a-IGZO) semiconductors was reported. It was found that water can diffuse in and out of the a-IGZO film, reversibly affecting the transistor properties. Two competing mechanisms depending on the thickness of the active channel were clarified. The electron donation effect caused by water adsorption dominated for the thicker a-IGZO films (⩾100nm), which was manifested in the large negative shift (>14V) of the threshold voltage. However, in the case of the thinner a-IGZO films (⩽70nm), the dominance of the water-induced acceptorlike trap behavior was observed. The direct evidence for this behavior was that the subthreshold swing was greatly deteriorated from 0.18V/decade (before water exposure) to 4.4V/decade (after water exposure) for the thinnest a-IGZO films (30nm). These results can be well explained by the screening effect of the intrinsic bulk traps of the a-IGZO semiconductor.

Double-Gate Tunnel FET With High- $\kappa$ Gate Dielectric

Abstract: In this paper, we propose and validate a novel design for a double-gate tunnel field-effect transistor (DG tunnel FET), for which the simulations show significant improvements compared with single-gate devices using a gate dielectric. For the first time, DG tunnel FET devices, which are using a high-gate dielectric, are explored using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average subthreshold swing of 57 mV/dec, and a minimum point slope of 11 mV/dec. The 2D nature of tunnel FET current flow is studied, demonstrating that the current is not confined to a channel at the gate-dielectric surface. When varying temperature, tunnel FETs with a high-kappa gate dielectric have a smaller threshold voltage shift than those using SiO2, while the subthreshold slope for fixed values of Vg remains nearly unchanged, in contrast with the traditional MOSFET. Moreover, an Ion/Ioff ratio of more than 2 times 1011 is shown for simulated devices with a gate length (over the intrinsic region) of 50 nm, which indicates that the tunnel FET is a promising candidate to achieve better-than-ITRS low-standby-power switch performance.

Semiconductor device, manufacturing method, and electronic device

Abstract: In a thin film transistor ( 1 ), a gate insulating layer ( 4 ) is formed on a gate electrode ( 3 ) formed on an insulating substrate ( 2 ). Formed on the gate insulating layer ( 4 ) is a semiconductor layer ( 5 ). Formed on the semiconductor layer ( 5 ) are a source electrode ( 6 ) and a drain electrode ( 7 ). A protective layer ( 8 ) covers them, so that the semiconductor layer ( 5 ) is blocked from an atmosphere. The semiconductor layer ( 5 ) (active layer) is made of, e.g., a semiconductor containing polycrystalline ZnO to which, e.g., a group V element is added. The protective layer ( 8 ) thus formed causes decrease of a surface level of the semiconductor layer ( 5 ). This eliminates a depletion layer spreading therewithin. Accordingly, the ZnO becomes an n-type semiconductor indicating an intrinsic resistance, with the result that too many free electrons are generated. However, the added element works on the ZnO as an accepter impurity, so that the free electrons are reduced. This decreases a gate voltage required for removal of the free electrons, so that the threshold voltage of the thin film transistor ( 1 ) becomes on the order of 0 V. This allows practical use of a semiconductor device which has an active layer made of zinc oxide and which includes an protective layer for blocking the active layer from an atmosphere.

42.2: World's Largest (15‐inch) XGA AMLCD Panel Using IGZO Oxide TFT

Abstract: The world's largest (15-inch) XGA active matrix liquid crystal display (AMLCD) panel made with IGZO TFTs (W/L=29.5/4 μm) was fabricated and evaluated with the field effective mobility of 4.2±0.4 cm2/V-s, Vth of −1.3±1.4V and sub-threshold swing (SS) of 0.96±0.10 V/dec. for a manufacturing-oriented process, the main factors affecting threshold voltage (Vth) of the IGZO thin film transistors (TFT) are investigated. On the glass surface, thicker regions of IGZO film have a negative threshold voltage shift. A dry etching process of molybdenum source and drain (S/D) causes negative shift of the average threshold voltage compared to wet etching in the bottom gate back channel etched TFTs. However, optimization of SiOx passivation and subsequent annealing shift average Vth positively and reduce Vth variation.

Improving the Gate Stability of ZnO Thin-Film Transistors with Aluminum Oxide Dielectric Layers

Abstract: We report on the fabrication of gate-stable ZnO thin-film transistors (TFTs) with aluminum oxide dielectric. When an off-stoichiometric AlO x was deposited at room temperature, the ZnO-TFT revealed unreliable transfer characteristics: a large drain current-gate bias (I D -V G ) hysteresis and a large amount of threshold voltage (V T ) shift under gate-bias stress. As rapid thermal annealing (RTA) in O 2 ambient was applied onto AIO X at 300°C prior to ZnO channel deposition, the gate-bias reliability of the ZnO device was improved. The RTA might cause our AlO x surface to be more stoichiometric and thus to be resistant against ZnO sputter-induced damage. When the bottom-gate ZnO-TFT was fabricated with a stoichiometric Al 2 O 3 dielectric grown by atomic layer deposition (ALD), our device showed much more stable electrical characteristics than with the sputter-deposited off-stoichiometric AlO x . Last, as an ultimate effort to improve the gate reliability, we fabricated a top-gate ZnO-TFT device adopting the same thick ALD-grown stoichiometric Al 2 O 3 as in the bottom-gate device. Our top-gate device with the Al 2 O 3 dielectric then showed no hysteresis and no V T shift after several times of gate bias sweep. We conclude that both the high quality dielectric and optimized device structure are necessary to realize electrically stable ZnO-TFTs.