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Timing attack

About: Timing attack is a research topic. Over the lifetime, 726 publications have been published within this topic receiving 25462 citations.


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Patent
27 Feb 1998
TL;DR: In this paper, a method and apparatus for hiding cryptographic keys based on autocorrelation timing attacks is presented, which allows independent software entities to authenticate themselves without storing a private cryptographic key, by storing timing statistics related to the evaluation of an equation in the software entity rather than the cryptographic key itself.
Abstract: A method and apparatus for hiding cryptographic keys based on autocorrelation timing attacks is provided. The method and apparatus of the present invention utilize a autocorrelation timing attack to allow independent software entities to authenticate themselves without storing a private cryptographic key. This is accomplished by storing timing statistics related to the evaluation of an equation in the software entity rather than the cryptographic key itself. When the software entity authenticates itself, the cryptographic key is derived based on information provided by the timing statistics contained in the software entity.

40 citations

Book ChapterDOI
02 Oct 2019
TL;DR: By exploiting Edwards arithmetic and optimal addition chains, this work produces the fastest constant-time version of CSIDH to date, and considers the stronger attack scenario of fault injection, which is relevant for the security ofCSIDH static keys in embedded hardware.
Abstract: CSIDH is a recent quantum-resistant primitive based on the difficulty of finding isogeny paths between supersingular curves. Recently, two constant-time versions of CSIDH have been proposed: first by Meyer, Campos and Reith, and then by Onuki, Aikawa, Yamazaki and Takagi. While both offer protection against timing attacks and simple power consumption analysis, they are vulnerable to more powerful attacks such as fault injections. In this work, we identify and repair two oversights in these algorithms that compromised their constant-time character. By exploiting Edwards arithmetic and optimal addition chains, we produce the fastest constant-time version of CSIDH to date. We then consider the stronger attack scenario of fault injection, which is relevant for the security of CSIDH static keys in embedded hardware. We propose and evaluate a dummy-free CSIDH algorithm. While these CSIDH variants are slower, their performance is still within a small constant factor of less-protected variants. Finally, we discuss derandomized CSIDH algorithms.

39 citations

Journal ArticleDOI
TL;DR: A general statistical model for side-channel attack analysis that takes characteristics of both the physical implementation and cryptographic algorithm into consideration is proposed and expected to be extendable to other SCAs, like timing attacks, and would provide valuable tools for evaluating cryptographic system’s resistance to those SCAs.
Abstract: Side-channel attacks (SCAs) exploit leakage from the physical implementation of cryptographic algorithms to recover the otherwise secret information. In the last decade, popular SCAs like differential power analysis (DPA) and correlation power analysis (CPA) have been invented and demonstrated to be realistic threats to many critical embedded systems. However, there is still no sound and provable theoretical model that illustrates precisely what the success of these attacks depends on and how. Based on the maximum likelihood estimation theory, this paper proposes a general statistical model for side-channel attack analysis that takes characteristics of both the physical implementation and cryptographic algorithm into consideration. The model establishes analytical relations between the success rate of attacks and the cryptographic system. For power analysis attacks, the side-channel characteristic of the physical implementation is modeled as signal-to-noise ratio (SNR), which is the ratio between the single-bit unit power consumption and the standard deviation of power distribution. The side-channel property of the cryptographic algorithm is extracted by a novel algorithmic confusion analysis. Experimental results of DPA and CPA on both DES and AES verify this model with high accuracy and demonstrate effectiveness of the algorithmic confusion analysis and SNR extraction. We expect the model to be extendable to other SCAs, like timing attacks, and would provide valuable tools for evaluating cryptographic system’s resistance to those SCAs.

39 citations

Patent
09 Jun 2000
TL;DR: In this paper, a cryptography circuit provides secure processing of data by utilizing countermeasures that combat timing and power attacks, such as multiplication operations, modular reductions by an integer, storage of data to memory, etc.
Abstract: A cryptography circuit provides secure processing of data by utilizing countermeasures that combat timing and power attacks. Superfluous operations such as multiplication operations, modular reductions by an integer, storage of data to memory are available for use by a processor to disguise the amount of power usage and the amount of time required to perform a cryptographic operation. A cryptographic key is available for use in order to trigger when these emulated operations occur. The occurrences of the emulated operations in controlled by the user to provide the preferred tradeoff between security and use of resources.

38 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202312
202221
202120
202030
201956
201849