Topic

# Timing failure

About: Timing failure is a research topic. Over the lifetime, 1774 publications have been published within this topic receiving 29718 citations.

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TL;DR: This article illustrates that many of the proposed clock synchronization protocols can be interpreted and their performance assessed using common statistical signal processing methods, and shows that advanced signal processing techniques enable the derivation of optimal clock synchronization algorithms under challenging scenarios.

Abstract: Clock synchronization is a critical component in the operation of wireless sensor networks (WSNs), as it provides a common time frame to different nodes. It supports functions such as fusing voice and video data from different sensor nodes, time-based channel sharing, and coordinated sleep wake-up node scheduling mechanisms. Early studies on clock synchronization for WSNs mainly focused on protocol design. However, the clock synchronization problem is inherently related to parameter estimation, and, recently, studies on clock synchronization began to emerge by adopting a statistical signal processing framework. In this article, a survey on the latest advances in the field of clock synchronization of WSNs is provided by following a signal processing viewpoint. This article illustrates that many of the proposed clock synchronization protocols can be interpreted and their performance assessed using common statistical signal processing methods. It is also shown that advanced signal processing techniques enable the derivation of optimal clock synchronization algorithms under challenging scenarios.

571 citations

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Bell Labs

^{1}TL;DR: Using a model to detect clocking hazards, two linear programs are investigated: minimizing the clock period, while avoiding clock hazards, and for a given period, maximizing the minimum safety margin against clock hazard.

Abstract: Improving the performance of a synchronous digital system by adjusting the path delays of the clock signal from the central clock source to individual flip-flops is investigated. Using a model to detect clocking hazards, two linear programs are investigated: (1) minimizing the clock period, while avoiding clock hazards, and (2) for a given period, maximizing the minimum safety margin against clock hazard. These programs are solved for a simple example, and circuit simulation is used to contrast the operation of a resulting circuit with the conventionally clocked version. The method is extended to account for clock skew caused by relative variations in the drive capabilities of N-channel versus P-channel transistors in CMOS. >

485 citations

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01 May 2001TL;DR: A theoretical background of clock skew is provided and minimum and maximum timing constraints are developed from the relative timing between the localized clock skew and the data paths.

Abstract: Clock distribution networks synchronize the flow of data signals among synchronous data paths. The design of these networks can dramatically affect system-wide performance and reliability. A theoretical background of clock skew is provided in order to better understand how clock distribution networks interact with data paths. Minimum and maximum timing constraints are developed from the relative timing between the localized clock skew and the data paths. These constraint relationships are reviewed, and compensating design techniques are discussed. The field of clock distribution network design and analysis can be grouped into a number of subtopics: 1) circuit and layout techniques for structured custom digital integrated circuits; 2) the automated layout and synthesis of clock distribution networks with application to automated placement and routing of gate arrays, standard cells and larger block-oriented circuits; 3) the analysis and modeling of the timing characteristics of clock distribution networks; and 4) the scheduling of the optimal timing characteristics of clock distribution networks based on architectural and functional performance requirements. Each of these areas is described the clock distribution networks of specific industrial circuits are surveyed and future trends are discussed.

475 citations

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27 Aug 1984

TL;DR: A new fault-tolerant algorithm for solving a variant of Lamport's clock synchronization problem for a system of distributed processes that communicate by sending messages, which solves the problem of maintaining closely synchronized local times, assuming that processes' local times are closely synchronized initially.

Abstract: We describe a new fault-tolerant algorithm for solving a variant of Lamport's clock synchronization problem. The algorithm is designed for a system of distributed processes that communicate by sending messages. Each process has its own read-only physical clock whose drift rate from real time is very small. By adding a value to its physical clock time, the process obtains its local time. The algorithm solves the problem of maintaining closely synchronized local times, assuming that processes' local times are closely synchronized initially. The algorithm is able to tolerate the failure of just under a third of the participating processes. It maintains synchronization to within a small constant, whose magnitude depends upon the rate of clock drift, the message delivery time, and the inital closeness of synchronization. We also give a characterization of how far the clocks drift from real time. Reintegration of a repaired process can be accomplished using a slight modification of the basic algorithm. A similar style algorithm can also be used to achieve synchronization initially.

331 citations

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TL;DR: A circuit for detecting timing errors between a binary signal and a local clock pulse generator and logical control signals for the clock are derived.

Abstract: A circuit for detecting timing errors between a binary signal and a local clock pulse generator is described. Three binary samples are compared and logical control signals for the clock are derived.

328 citations