Showing papers on "Topology (electrical circuits) published in 1983"

Fully integrated active RC filters in MOS technology

Abstract: A fully integrated continuous-time low-pass filter has been fabricated with CMOS technology. The device implements an active RC network using integrated capacitors and MOS transistors operated in the nonsaturation region as voltage-controlled resistors. The filter topology is fully balanced for good linearity and for good power supply rejection. The cutoff frequency is voltage adjustable around 3 kHz, allowing compensation for process and temperature variations. For 5-V power supplies a dynamic range of over 94 dB has been achieved.

An Analytic Approach to Optimum Oscillator Design Using S-Parameters

Abstract: An analytic approach to the design of microwave FET oscillators for maximum power output into a given load is presented. By the use of FET S-parameters, characterized as a function of incident input powers, design information can he obtained for any standard topology. By means of this technique, an experimental 5.3-GHz oscillator has been demonstrated which delivers 245 mW at 35-percent efficiency into a 50-Omega load.

Equivalence Between Direct and Synthetic Short-Circuit Interruption Tests on HV Circuit Breakers

Abstract: Verified thermal models of the circuit breaker arc resistance were used to evaluate the equivalence lence between direct and corresponding currenttioninjec- ion synthetic circuits during short-circuit intetionrup- ion tests. It was observed that it is not sufficient for both circuits to produce the same prospective current ent stress and recovery voltage envelope but that they must have the same topology of their voltage branch although the values of their inductance can be quite different.

A new flyback DC-to -three-phase converter with sinusoidal outputs

Abstract: Systematic extension of any dc-to-dc converter leads to its dc-to-three-phase equivalent characterized by sinusoidal output voltages and fast dynamic responses. This genralization principle is illustrated for the special case of the flyback topology. State-space averaging has modeled with a high degree of accuracy the performance of dc-to-dc converters. Here it is combined with the stationary-to-rotating coordinate transformation, customarily used in plyphase ac systems, to results in an effective analysis method for switched-mode dc-to-polyphase converters.

A modular and orthogonal digital filter structure for parallel processing

Abstract: An orthogonal filter structure is presented, whose synthesis is based on a generalized Levinson algorithm. This structure has a ladder-like flow graph topology. It is modular and has a high degree of computational parallelism. Implementation guidelines in the framework of parallel data processing are considered. A closed form for the round off noise error variance is given, from which it appears that the structure will be particularly useful for the implementation of narrow bandwidth filters.

Efficient algorithms for the constraint generation for integrated circuit layout compaction

Abstract: A compactor for VLSI layouts is an essential component in many CAD systems for VLSI design It reduces the area of a given layout violating any of the design rules dictated by the fabrication process In many CAD systems for VLSI design the compacter generates a number of linear inequalities from the circuit layout These so-called constraints restrict the coordinates of the layout components The resulting inequality system is then solved in some optimum way The solution of such inequality system can be done efficiently The generation of the constraints, however, is a problem for which no efficient algorithms have been devised so far We define the graph problem underlying the constraint generation for VLSI circuit compaction Furthermore we develop efficient, ie, O(nlogn) time algorithms for the generation of constraint systems that allow to change the layout topology during the conpaction in order to yield good compaction results, but at the same time are sparse enough to be solved efficiently, ie, of size O(n) These algorithms are simple enough to be implemented

Full adder using transmission gates

Abstract: A binary full adder, including provision for carry digits, is implemented using metal-oxide semiconductor field-effect transistors (MOSFET) in the exclusive-OR configuration. The improved structure realizes economies in space occupancy, and device topology, reduction in power requirement and no loss in propagation time over prior full adders employing conventional logic structures.

Optimal Network Bus Ordering in Power System State Estimation --- Its Consistency with that in Load Flow

Abstract: This paper presents a basic rule of making network bus ordering for state estimation by taking into consideration both circuit topology and measurement set information. In order to unify these two different kinds of reference information, measurement information is translated into its topological equivalent and annexed to the system topology representation. Therefore, the ordering can be done by referring only to the modified network topology information. The translation rule is found through the investigation of the topological property of the coefficient matrix of a normal equation in state estimation calculation.

Interconnection of Local Computer Networks: Modeling and Optimization Problems

Abstract: We study problems of optimization of the topology of interconnected local computer networks using random access to a single channel. An approach to modeling of the system by a queueing network is proposed: the analytical solution of the model allows us to obtain global performance measures, which may be used as evaluation criteria in network topology optimization problems. A heuristic is proposed for the latter aspect for one class of problems. We also derive from the model the time needed, for a new user which joins the network, to transmit its number of messages.

A Layout Verification System for Analog Bipolar Integrated Circuits

Abstract: A new layout verification system, called ALAS (A Layout Analysis System) is presented. Its main intention is to tackle the particular verification problems of analog bipolar circuits. At present, the system comprises four main parts: a device recognition program produces a list of devices, a plot program converts these data to a layout-oriented circuit diagram, a connectivity analysis program yields device-oriented or net-oriented descriptions of the derived circuit and a network comparison program tests the consistency of this actual circuit with the intended nominal one. A fifth program, that will calculate the parameters of the actual circuit, is under development. To derive the actual circuit from layout ALAS uses geometrical mask data only; no additional circuit information is needed. If not available from the design system, a description of the nominal circuit may be supplied manually in a SPICE-like input format.

A Mathematical Model for Dynamic Simulation of HVDC Systems

Abstract: This paper develops a mathematical model for the dynamic simulation of ac-dc systems. The basic features of the proposed model are: All the subsystems and components of a realistic HVDC scheme are included in the model. The power system components are modelled using the exact differential equations derived from their three phase equivalent networks and therefore the model can give the instantaneous values of voltage, current and power at any point of the system. The considerable amount of computation involved is substantially reduced using tensor techniques as the differential equations of the system are automatically assembled to deal with the time varying topology of the network caused by the switching action of the valves. Line and bus faults are also simulated using tensor techniques and this increases considerably the flexibilty of the computer program. The basic disadvantage of the model is the extensive computation required and is, therefore, suitable only for applications where accuracy is essential, as for the final testing of new converter control systems.

Topology quasi-preservation by local parallel operations

Abstract: A set of local parallel operations on binary images, represented as sets of square lattice points is determined, whose members use 2 × 3 windows and do shrinking with the quasi-preservation of topological structures of the images. The adjacency tree is used to define the topology of the images, and is required to be ultimately reduced to the root node (background) by repeated elimination of the leaves which correspond to simply connected components. The set of operations is constructively obtained by determining necesary and sufficient conditions for a parallel operation to satisfy the quasi-preservation property thus defined.

Analysis of switched-capacitor networks containing operational amplifiers with finite DC gain and gain-bandwidth product values

Abstract: A new analysis technique is proposed to take into account the finite DC gain and gain-bandwidth product of the operational amplifiers (OAs) on the response of switched-capacitor (SC) networks, operated by a biphase clock. The technique is simple, versatile and applicable to an SC network of any topology. Examples are given to illustrate the technique. As an application, all the parasitic insensitive SC biquadratic filters, bilinearly equivalent to their analogue counterparts, known to date, are compared using the proposed method. Extensive experimental tests were conducted. Results agree closely with theoretical predictions.

A Topology for Semicustom Array-Structured LSI Devices, and Their Automatic Customisation

Abstract: This paper describes the design of a topology for array-structured (both Gate-Array and Polycell) semicustom LSI, in the context of a CMOS gate-array fabricated to test both the topology and the unique functional cells. Design emphasis has been placed on 100% routability, which is achieved by use of interdigitating cell terminals. Also described is the structure and operation of an automatic customisation software package which has been developed for the array, and which utilises the topological advantages to achieve track densities which are comparable with state-of-the-art algorithms. Examples are cited which show that this methodology is economical in both its speed of operation and its silicon-area utilisation.

Optimum design of a new DC-SC circuit

Abstract: Detailed analysis and optimum design of the commutating circuit of the recently proposed DC-side commutated current-source inverter are given. Analysis was performed for each topology mode during a step transition interval under certain assumptions and using various normalised quantities. Using the analysis results, optimum design of the commutating circuit was studied with an aim to maximising the turn-off time with a minimum commutating energy. Experimental results showed reasonably good agreement with the theoretical results.

Practical design considerations for Coupled-Single-Amplifier-Biquad active bandpass filters

Abstract: This paper presents a synthesis method and practical design considerations for the Coupled-Single-Amplifier-Biquad (CSAB) realization of all-pole symmetrical bandpass (BP) filters. The CSAB topology consists of a cascade of second-order SAB bandpass sections, together with negative feedback around adjacent sections. A straightforward procedure that leads to the block diagram representation of the CSAB is shown. Explicit design formulas are given for the optimum element values of the Deliyannis-Friend SAB bandpass section, as well as for the feedback resistors. This CSAB design offers improved performance over the cascade SAB approach without using additional operational amplifiers. Also described are the effects on the filter response due to finite amplifier gain, capacitor dissipations, noninfinite pole-Q sections, and their compensation techniques. These are followed by discussions on maximizing the filter dynamic range and tuning.

Gain-bandwidth product effects on SC filters including a quasi-optimal topology

Abstract: The gain-bandwidth product (GB) effects on switched-capacitor (SC) filters are analyzed and described in detail. A systematic general analysis method is reviewed. To biquad SC filters with the same ideal transfer function are compared. It is shown that when the op amps are modeled with one dominant pole, their frequency responses differ significantly. The importance of switch phasing is emphasized and explained, and GB effects on SC filters are discussed. A quasi-optimal SC biquad topology with respect to GB effects is described. Its performance is illustrated by means of a root-locus plot. This plot allows the designer to determine the ω0 and Q deviations for different values of GB/ω0.

Easily testable interconnection network from three-state cells (parallel processing)

Abstract: A design methodology for an easily testable multistage interconnection network utilising three-state switching elements (SES) is presented. The proposed network topology is determined from a general graph model of such networks. The network is implemented in such a way that one test is enough to detect single or multiple faults. The faculty modules are tested and reflected at the output of the external links. Such modules consist of a large number of 2-input/2-output three-state SES and are assumed to be fabricated with LSI/VLSI technology. 16 references.

Battery Model using Advice Computer Simulation of PIN Diodes and RLC Circuit Topology

Abstract: The two terminal electrical behavior of batteries is simulated in detail using a circuit model based on the dynamics of the charge storage PIN diode and RLC circuit elements. The standard Bell Labs integrated circuit analysis computer program ADVICE has been used to calculate the responses shown.

Emunet “emulator of network systems” a general framework

Abstract: The project discussed here provides a general tool, the architecture of which allows to emulate various network configurations, and to implement various synchronization algorithms for distributed control, distributed data or functions. This emulation enables the measurement of various characteristics of these algorithms: resiliency, overhead, fairness, response time and so on. This tool resides in a physically local network, built with homogeneous microcomputers. The desired network is simulated on this physical network. The topology of the physical network supporting the simulation is a star. The central node is considered from the other satellite computers as a simple transport medium which emulates the links of the required network to which each one is connected. In the central node a simple interpreter performs the desired emulated network (loop, mutidrop, mesh….) by consulting a description of the links of this network. The simulation is made, using 3 layers of software in the central node emulator: first level: connections with the various computers of the physical network and data link control protocols. second level: path control where the routing of the various messages is performed between the satellites in the simulation. third level: traffic supervision, keeping track of the different transactions and to develop measurements and statistics on the running of the simulated network. In the satellites, the distributed systems and applications are implemented. This tool is intended to facilitate the implementation and the testing of algorithms for distributed control as well as algorithms for distributed data: ticketing algorithms, virtual rings, logical clocks or any other. Even more, it is designed to measure the different characteristics of these algorithms so as to permit their comparison. Its modularity authorizes also to perform the simulation of various faults in the satellites.

The J3 SCR Model Applied to Resonant Converter Simulation

Abstract: The J3 SCR model is a continuous topology computer model for the SCR. Its circuit analog and Parameter estimation procedure are uniformly applicable to popular computer aided design and analysis programs such as SPICE2 and SCEPTRE. The circuit analog is based on the intrinsic three PN junction structure of the SCR. The parameter estimation procedure requires only manufacturer's specification sheet quantities as a data base. This uniform model, denoted the J3 SCR model is shown to be a useful design aid through computer simulation of fault transients which may occur in a "Schwartz" converter. The transients simulated would not be observable without use of a highly accurate continuous topology non-linear SCR model such as the J3 SCR model.