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Showing papers on "Topology (electrical circuits) published in 1984"


Journal ArticleDOI
TL;DR: In this paper, a canonical nonlinear programming circuit for simulating general non-linear programming problems has been developed using the Kuhn-Tucker conditions from mathematical programming theory, which is canonical in the sense that its topology remains unchanged and that it requires only a minimum number of 2terminal nonlinear circuit elements.
Abstract: Using the Kuhn-Tucker conditions from mathematical programming theory, a canonical nonlinear programming circuit for simulating general nonlinear programming problems has been developed. This circuit is canonical in the sense that its topology remains unchanged and that it requires only a minimum number of 2-terminal nonlinear circuit elements. Rather than solving the problem by iteration using a digital computer, we obtain the answer by setting up the associated nonlinear programming circuit and measuring the node voltages. In other words, the nonlinear programming circuit is simply a special purpose analog computer containing a repertoire of nonlinear function building blocks. To demonstrate the feasibility and advantage of this approach, several circuits have been built and measured. In all cases, the answers are obtained almost instantaneously in real time and are accurate to within 3 percent of the exact answers.

194 citations


Journal ArticleDOI
TL;DR: Attention is paid to fabrication tolerances, wire capacitance, wire resistance, coupling capacitances and capacitance associated with contacts and the aspect ratio of (non-rectangular) transistors.

185 citations


Patent
24 Dec 1984
TL;DR: In this article, the authors proposed two different topologies for implementing a second order allpass function filter which is vital for equalization of the phase of other arbitrary response magnitude shaping filters.
Abstract: This invention comprises two separate topologies for implementing a second order allpass function filter which is vital for equalization of the phase of other arbitrary response magnitude shaping filters. While the allpass response itself does not affect the frequency spectrum of the signal, these topologies have available outputs that have either bandpass or bandstop characteristics. Thus, two types of useful frequency characteristics formed by the filters that have exactly the same resonant frequency and Q (or Quality factor). Using the well known general two amplifier topology to implement a monolithic switched allpass filter with a high Q leads to very high capacitance ratios and hence excessive silicon area in manufacture. Both the topologies described here reduce the required silicon area by either reducing the required capacitance ratios or making the sensitivity to the smallest capacitor extremely small allowing it to violate otherwise necessary area-to-perimeter matching of the capacitor geometries. Reducing the overall silicon area reduces the overall cost of producing the filters and allows more functionality to be integrated on a single silicon chip.

64 citations


Journal ArticleDOI
Woo1
TL;DR: This article examines four data structure conversions using two types of internal representation: a CSG tree and a boundary representation graph.
Abstract: Because of their many possible uses, geometric models must be applicationindependent as well as informationally complete. This article examines four data structure conversions using two types of internal representation: a CSG tree and a boundary representation graph. Just as research in computer graphics in the 1960's led to the development of contemporary CAD/CAM systems, so is research in geometric modeling in the 1970's likely to be the core of a new generation of CAD/ CAM systems in the 80's. One of the goals of geometric modeliing is to enable the construction of a central database for the information storage, retrieval, and updating of three-dimensional mechanical components, assemblies, and systems. Because such informatioin is intended for a Nvide X ariety of purposes, such as documentation, drafting, engineering analysis, simulation, process planning, part programming, and automatic assembly, a geometric model must be not onlyx complete (having all the necessary information) but also application-independent. At the University of Michigan, the College of Engineering recently embarked on a long-range program (currently funded by a grant from the Air Force Office of Scientific Research) involving integrated manufacturing and robotics. Amid a wide range of research applications such as high-

55 citations


Journal ArticleDOI
TL;DR: In this article, an algorithm for obtaining an optimal network topology which gives the maximum s−t reliability is presented, which has an additional advantage that the system is not to be redesigned, if at a later stage the permissible cost is enhanced by budgetary provisions.

46 citations


Journal ArticleDOI
TL;DR: An algorithm is presented which compares the actual topology of an integrated circuit derived from its layout with a user-supplied description of the intended nominal circuit at the transistor level, which has proven to be particularly efficient for analog bipolar circuits.
Abstract: An algorithm is presented which compares the actual topology of an integrated circuit derived from its layout with a user-supplied description of the intended nominal circuit at the transistor level. Devices and nets in both circuits may be named arbitrarily. Using information about device types and pin types to weight the nodes of the corresponding graphs, isomorphism is tested and the names of devices and nets are matched. Differences are isolated and result in an error report for layout correction. The implemented program NEtwork COMparison (NECOM) has proven to be particularly efficient for analog bipolar circuits. It represents an essential part of a recently developed complete mask artwork analysis system called ALAS.

23 citations


Proceedings ArticleDOI
George B. Yundt1
18 Jun 1984
TL;DR: In this paper, power amplifiers based on combining two power stages where one power stage supplies the bulk of the load power and the other insures high output signal quality are discussed.
Abstract: Power amplifiers based on combining two power stages where one supplies the bulk of the load power and the other insures high output signal quality are discussed. This description yields a unique parallel topology. Experimental and theoretical results shows this topology has high performance without large efficiency or hardware penalties.

15 citations


Journal ArticleDOI
Jeffrey M. Jaffe1, Adrian Segall1
01 Jun 1984
TL;DR: The present paper describes an algorithm that allows complete flexibility in the placement of the topology information and assumes that an arbitrary subset of network nodes are capable of maintaining theTopology.
Abstract: In computer communication networks, routing is often accomplished by maintaining copies of the network topology and dynamic performance characteristics in various network nodes The present paper describes an algorithm that allows complete flexibility in the placement of the topology information In particular, we assume that an arbitrary subset of network nodes are capable of maintaining the topology In this environment, protocols are defined to allow automatic updates to flow between these more capable nodes In addition, protocols are defined to allow less capable nodes to report their topology data to the major nodes, and acquire route information from them

11 citations


Journal ArticleDOI
TL;DR: In this paper, design guidelines for biquadratic SC filters taking into consideration passive sensitivity, output voltage swing, and total capacitance area are described, and the tradeoffs between these three parameters are discussed.
Abstract: Design guidelines for biquadratic SC filters taking into consideration passive sensitivity, output voltage swing, and total capacitance area are described. In this paper, we discuss the tradeoffs between these three parameters. A popular SC topology with additional positive feedback is used to illustrate the tradeoffs involved in the design of SC filters.

11 citations


Journal ArticleDOI
TL;DR: A novel loop-structured switching network intended for highly parallel processing architectures that has the advantage of incremental extensibility, and-it could avoid store-and-forward deadlocks (SFD) which prevail in other recirculating packet-switched networks.
Abstract: This paper describes a novel loop-structured switching network (LSSN) intended for highly parallel processing architectures. With L loops, it can connect up to N = L* log2 L pairs of transmitting and receiving devices using only N/2 two-by-two switching elements; thus, it is very cost-effective in terms of its component count. Its topology resembles that of the indirect binary n-cube network, but a much higher device-to-switch ratio is achieved because all the links between the switches could be used as both transmitting and receiving stations. It has the advantage of incremental extensibility, and-it could avoid store-and-forward deadlocks (SFD) which prevail in other recirculating packet-switched networks. Our simulation studies show that the average throughput rate and delay of LSSN are close to that of other designs despite its relatively low component count.

8 citations


Journal ArticleDOI
TL;DR: A new technique is described for the realisation of the general biquad topology by means of passive switched-capacitor networks, i.e. utilising only capacitors and MOS switches.
Abstract: A new technique is described for the realisation of the general biquad topology by means of passive switched-capacitor networks, i.e. utilising only capacitors and MOS switches.

Journal ArticleDOI
01 Jan 1984
TL;DR: A novel implementation of a Two-dimensional FFT array processor is given and the reasons for its superior performance are the one-to-one and onto mapping of the problem communications topology onto the interconnection network.
Abstract: A novel implementation of a Two-dimensional FFT array processor is given. The reasons for its superior performance is the one-to-one and onto mapping of the problem communications topology onto the interconnection network, VLSI-based implementation, a proper choice for the number system, multiple-parallelism, and the use of packet-switching as opposed to circuit switching. A performance comparison also presented.


DOI
01 Apr 1984
TL;DR: Methods of removing the looping problem are discussed and a modified Anarchy flood routing (MAFR) protocol is proposed, for which a simplified performance analysis and simulation studies indicate that better network performance can be achieved with little additional hardware.
Abstract: The lack of satisfactory passive connectors, of standardisation in fibre-optic devices and the unidirectional light transmission employed in most fibre links prohibits the direct translation of networking techniques from the better developed wire or cable systems. A point-to-point network with nodes connected in an arbitrary fashion can provide an ideal solution to these problems while maintaining high network reliability and permitting easy reconfiguration, but has associated problems in the routing of the data. A possible solution is to use the flood routing technique as proposed by Neff and Senzig in their Anarchy network. Unfortunately, this network exhibits very low channel utilisation and has packet looping problems. In the paper we discuss methods of removing the looping problem and then propose a modified Anarchy flood routing (MAFR) protocol, for which a simplified performance analysis and simulation studies indicate that better network performance can be achieved with little additional hardware. However, we believe that a hybrid flood routing scheme (HFR) involving MAFR and a virtual circuit approach will produce a better system.

Journal ArticleDOI
01 Dec 1984
TL;DR: A modelling technique which employs the modified Gauss-Newton optimisation algorithm in conjunction with some strategies for modifying linear network topology is described, demonstrating the power of the technique.
Abstract: The paper describes a modelling technique which employs the modified Gauss-Newton optimisation algorithm in conjunction with some strategies for modifying linear network topology. Results obtained in a number of cases of modelling high-frequency transistors are given, demonstrating the power of the technique. It is emphasised that all changes in model topology are decided entirely automatically by the computer.

Proceedings ArticleDOI
01 Oct 1984


Journal ArticleDOI
TL;DR: The proposed technique envisages minimizing the external links and reducing the propagation delay, and the dual tree topology which allows a smaller pin count for the chip is considered for the realization of the modularized network.
Abstract: A technique is described for making alignment networks more reliable and cost effective. The proposed technique envisages minimizing the external links and reducing the propagation delay. The VLSI implementation of the network is based on the modularization concept, achieving a simple layout, flexible design, increased computational speed and high circuit, density. The dual tree topology which allows a smaller pin count for the chip is considered for the realization of the modularized network.

Book ChapterDOI
01 Jan 1984
TL;DR: Dynamic Network Colouring (DNC) uses the results of topology identification, discriminates the energized/de-energized / earthed parts of the network and represents them as coloured single-line diagrams on monitor CRT's and facilitates the implementation of a state estimator.
Abstract: Dynamic Network Colouring (DNC) - a new software-function of the network control technique - uses the results of topology identification, discriminates the energized/de-energized / earthed parts of the network and represents them as coloured single-line diagrams on monitor CRT's DNC supports the operator in his decision process by giving him compressed information on the actual network topology and energized state DNC bridges the gap between SCADA functions and power system security analysis and predictive software functions (PAS) Based on the actual status of all switching devices, a real-time topology module determines the network connectivity; additionally by processing measurements it permits the identification of the energized state of the network The results are displayed in an easy-to-interpret form such as one-line-coloured-diagrams or network schemas DNC permits a network representation in a diagrammatic form at different levels of details with different colours according to various operating criteria During the implementation and testing phase DNC represents an useful tool for detecting erroneous data DNC is designed for HV- and very large MV-networks A production grade computer program has been developed and integrated into a large and complex on-line SW-system The general design will be outlined and the experience of some first implementations in network monitoring will be summarized errors in the data for the monitor displays and the data for DNC and the network calculation functions In this way DNC facilitates the implementation of a state estimator The plausibility checks included in DNC help the operator to recognize errors in the SCADA system Identifying and correcting the errors works like a preprocessor for state estimation


01 Jan 1984
TL;DR: In this paper, the performance and design of integrated circuit/packet-switched computer-communication networks were investigated, where the trunk lines carry both voice and data simultaneously, while data subscribers terminate directly to the circuit switch nodes of the subnet.
Abstract: : This research investigates the performance and design of integrated circuit/packet-switched computer-communication networks. The integrated network under consideration has a circuit-switched communications subnet whose trunk lines carry both voice and data simultaneously. Peripheral packet switches provide data subscribers access to the subnet, while voice subscribers terminate directly to the circuit switch nodes of the subnet.

Journal ArticleDOI
TL;DR: This paper describes the design of a new functional-cell gate-array with inherently high routability, and its automated customization software which achieves 100 percent first-time routing.
Abstract: This paper describes the design of a new functional-cell gate-array with inherently high routability, and its automated customization software which achieves 100 percent first-time routing. Emphasis is placed upon the considerations which influence the selection of a functional array primitive. A highly structured interconnection architecture will be described, which employs interdigitating cell terminals in a polycell-like wiring channel topology to simplify the routing procedure for the array. The detailed structure and operation of an automatic customization software package is discussed. This package, developed specially for the array, utilizes the structured topology to achieve track densities which are comparable with those produced by state-of-the-art algorithms. This array has been fabricated, in a CMOS technology, as a test-vehicle for both the unusual topology and the unique functional cells. Throughout the study, emphasis has been placed on achieving a coherent strategy for producing efficiently routed gate-arrays with the minimum of sophisticated design tools. Examples will be cited to show that this methodology is economical both in the rapidity with which finished designs may be produced, and in its utilization of silicon-area.

01 Jan 1984
TL;DR: This thesis describes novel work in: CAD for Switched-Capacitor filter analysis as implemented in the DIANA.SC program, CAD for Digital Filter analysis and simulation as realized in the DIGEST program and CAD for control generation in bit-serial VLSI implementations of digital filters by means of delay management for the CATHEDRAL-I system.
Abstract: This thesis describes novel work in: CAD for Switched-Capacitor filter analysis as implemented in the DIANA.SC program, CAD for Digital Filter analysis and simulation as realized in the DIGEST program and CAD for control generation in bit-serial VLSI implementations of digital filters by means of delay management for the CATHEDRAL-I system. New analysis and associated matrix compaction techniques for multi-rate switched capacitor and digital filters with an arbitrary topology are described in detail. The analysis of arbitrary topology multi-rate SC-filters can be done in various ways (frequency domain, continuous coupling effects, sample and hold effects, group delay, amplitude slopes, sensitivities...). The techniques are illustrated by the implementation in the DIANA.SC program. New analysis techniques for the CAD of arbitrary topology and single and/or multi-rate digital filters, by analysis (frequency domain, transfer functions, phases, group delay, amplitude slope, sensitivities, noise, limit cycles, parasitic oscillations, scaling analysis according to several criteria, adjoint networks, template analysis,...) and bit-true simulation are described. These methods are illustrated by the implementation in the DIGEST digital filter analysis and simulation program. New techniques for the characterization of parasitic oscillations (with and without input signals) in function of the oscillation period are described. These determine upper and lower bounds on arbitrary topology digital filter structures, with an accurate modeling of the finite word length effects induced by e.g. truncation of operations (e.g. value- or magnitude truncation). This is illustrated by the program LIMCYC for characterizing parasitic oscillations by analysis. DIGEST serves as a preprocessor for the automatic synthesis of digital filters into the CATHEDRAL-I bit-serial silicon compiler. The last part of the thesis describes techniques for optimizing the distribution of "shimming delay" shift registers in bit-serial filters as well as the generation of the associated control logic and synchronization signals. This is implemented in a program called DELMAN.

01 Mar 1984
TL;DR: The interconnection of a photovoltaic generator to a utility can be made more cost effective by eliminating the need for an isolation or dedicated utility transformer.

Book ChapterDOI
01 Jan 1984
TL;DR: A software subsystem which dynamically evaluates and displays the current topological state of a power system and is part of the PSI software system for power system monitoring and control is presented.
Abstract: The paper presents a software subsystem which dynamically evaluates and displays the current topological state of a power system. The topology subsystem is part of the PSI software system for power system monitoring and control, the general structure of which will be described.

Book ChapterDOI
01 Jan 1984
TL;DR: A comprehensive approach to power network topology updating is presented, which includes the measurement assignment, power network model, base of cycles, list of cuts, definition of islands, isolated nodes, switched out and open ended lines.
Abstract: A comprehensive approach to power network topology updating is presented. It includes the measurement assignment, power network model, base of cycles, list of cuts, definition of islands, isolated nodes, switched out and open ended lines.

01 Jan 1984
TL;DR: In this article, a detailed analysis of two SC pseudo-N-path filters is presented to determine the effects of their transfer functions due to the op amp gain-bandwidth product (GB).
Abstract: A detailed analysis of two novel SC pseudo-N-path filters 131, (4) are presented to determine the effects of their transfer functions due to .the op amp gain-bandwidth product (GB). To appreciate the difference between the two filters, z-plane root locus plots as a function of GB/f,. are presented. An approach to implement narrow-band comb filters is by means of the N-path concept (l). Switched-capacitor techniques can be easily incorporated with the N-path filters to realize practical monolithic filters. The basic N-path concept involves N ideally identical SC low-pass filters (2) that are cyclically oper- ated each at the low frequency fc and the input signal is sampled at a higher clock frequency Nfc. Unfortunately, with true N-path filters a number of unwanted image frequencies is generated, since in practice the N individual paths are not matched per- fectly. Besides this problem, there is clock feedthrough at the signal frequencies. The pseudo-N-path filters have been proposed to eliminate these problems (3), (4). In this approach each feed- back capacitor is replaced by a circulating shift register. The RAM-type shift register reported in (3) eliminated the matching problem. An alternative realization for a shift register that pro- vides a solution to both mismatching and clock feedthrough problems is proposed in (3). Fig. 1 shows a three-path time multiplexed SC N-path filter with inversion. This circuit (3) is a modification by Patangia and Cartinhour (5). Another novel circulating shift register (4) with favorable discharge time, en- abling the filter to theoretically operate at a relatively high frequency is shown in Fig. 2. In this paper we compare these two novel SC pseudo-N-patch filters. It is shown that when the op amps are modeled with one dominant pole, their frequency responses differ significantly. To illustrate the difference between the shift registers, a numerical example is considered. The design factors are: a center frequency f0 =l kHz, a sampling frequency fc = 6 kHz, and N = 3. The circuit of Fig. 1 uses one op amp and 4 clock phases. CZp was included to simulate the parasitic capacitance of the topology at that node. Fig. 2 involves 3 op amps and 2 clock phases. The circuits were analyzed assuming all the op amps have the same GB and are characterized by a dominant pole. The analysis of Fig. 1 involves one circuit analysis for each phase. The equation characterizing any of the four circuits is a linear differential equation, the initial conditions are naturally different at each phase. The step response of any simple op amp SC circuit is an exponential ramp. For an ideal op amp, i.e., GB + 00 the step response would be another step. The complete description of the analysis requires the solution of four simultaneous differential equations. In the case of Fig. 2, the analysis involves the solution of three differential equations (one for each op amp) for each of