Showing papers on "Topology (electrical circuits) published in 1987"

Pseudo-resonant full bridge DC/DC converter

Abstract: This paper proposes a new dc/dc converter topology which combines the ease of control and wide range of conventional dc/dc converters, with low switching losses, low dv/dt and low EMI that is typical of zero voltage switched resonant converters. Consequently, the ratings of these components are substantially lower than for similarly rated resonant topologies. Operation at very high frequencies is possible and is shown with the fabrication of a 200 watt, 1 MHz dc/dc converter.

Applying static network protocols to dynamic networks

Abstract: This paper addresses the problem of how to adapt an algorithm designed for fixed topology networks to produce the intended results, when run in a network whose topology changes dynamically, in spite of encountering topological changes during its execution. We present a simple and unified procedure, called a reset procedure, which, when combined with the static algorithm, achieves this adaptation. The communication and time complexities of the reset procedure, per topological change, are independent of the number of topological changes and are linearly bounded by the size of the subset of the network which participates in the algorithm.

Network topology in simulated water

Abstract: Configurations of 216 water molecules sampled during the course of isobaric-isothermal simulations over the temperature range -25 to 100 /sup 0/C at 1 atm pressure, using the TIP4P model, are analyzed to study the hydrogen-bond network topology. Results are presented for the total number of polygons of up to seven molecules and for primitive polygons, being those which have no pair of nonadjacent vertices connected by a bridge which is shorter than either of the paths between these vertices within the polygon itself. The authors introduce the concept of a reference network, in which each molecule is hydrogen bonded to four others, and report on the temperature dependence of its topological characteristics.

Topology conserving mappings for learning motor tasks

Abstract: Topology conserving mappings play an important role for biological processing of sensory input. We suggest that principles found capable of establishing such maps can also be applied to organize the learning of motor tasks. As an example we consider the task of learning to balance a pole.

Generalization of resonant switches and quasi-resonant DC-DC converters

Abstract: The concept of resonant switch topology is defined and is used to develop a procedure to classify known quasi-resonant converters or to synthesize new ones. Two new resonant switch topologies and the corresponding classes of converters are identified by the synthesis procedure. The steady-state performance of one converter is analyzed and verified.

An oversampling analog-to-digital converter topology for high-resolution signal acquisition systems

Abstract: High-precision analog-to-digital converters (ADC's) which periodically sample continuous time waveforms are required in many "signal acquisition" applications such as digital audio and instrumentation. This paper describes a specific topology for an oversampling differential pulse code modulation (DPCM)-type ADC that requires neither an analog anti-aliasing filter nor a sample-and-hold. Dithering techniques are presented which cause the quantization error to resemble an additive Gaussian white-noise source whose mean and variance are independent of the input. A smoothing technique is presented which improves the linearity of the ADC's transfer function. Results presented are based on both simulations and measurements of a test system constructed from discrete components. The potential for integration in a standard digital CMOS process is discussed.

Source volt-ampere/load volt-ampere differential converter

Abstract: A source V-A/load V-A differential converter (single quaddrant DC-DC topology) combines the canonical functions of both the boost and buck converter topologies. Basic advantages of the boost and buck topologies are retained, disadvantages of these and prior art compound topologies are eliminated, and several entirely new and useful functions are realized. These new functions include sub-microsecond source voltage/load step response (independent of feedback loop parameters), extremely wide source voltage range, very high conversion efficiency/power density, multiple auxiliary outputs with closely held voltage range parameters (without resort to minimum load, pre-load, or sub-regulation), galvanic input/output isolation, enhanced capacitance safety/energy storage, reduced gain bandwidth requirements, and intrinsic stability. The differential term derives from the transfer function for this new compound topology, i.e., x=δ(a+x).

Design Considerations for Very High Frequency Resonant Mode DC/DC Converters

Abstract: The demand for higher switching frequencies in power converters has rekindled interest in resonant mode topologies. Conventional resonant converter circuits, however, are not optimized for high-frequency operation. A new resonant mode dc/dc converter topology exhibits desirable characteristics including zero switching losses, elimination of snubbers, simple control strategy, and circuit operation that is insensitive to parasitics such as diode reverse recovery. Analysis and design techniques are discussed in detail and are experimentally verified with a 150-W prototype converter operating in the frequency range 500 kHz-1 MHz.

A 3-phase inductor fed SMR converter with high frequency isolation, high power density and improved power factor

Abstract: A novel two stage Inductor fed Switch Mode Rectifier (SMR) topology has been developed and presented In this paper. Its advantages over other SMR topologies Include; high Input power factor; Improved reliability; high power density; minimum Input line current harmonic distortion; elimination of the Input filter AC capacitors and elimination of of the DC link capacitor.

Unified Topological Modeling Method of Switching DC-DC Converters in Duty-Ratio Programmed Mode

Abstract: A unified continuous small-signal modeling method of switching dc-dc converters operating in duty-ratio programmed mode is presented. The method can be considered a new implementation of the widely known state-space averaging approach. Its principal advantage is a reduction of the order of the matrices to be inverted resulting in a significant simplification of the modeling procedure, especially for more complex converter configurations. The method leads to the unifled expressions for the elements of two useful forms of circuit model, namely, Y-parameter model and ladder LC filter-form model. To demonstrate the usefulness of the proposed modeling technique the dynamic model of the ?uk converter with damping network is derived.

Design considerations for very high frequency resonant mode dc/dc converters

Abstract: The demand for higher switching frequencies in power converters has rekindled interest in resonant mode topologies. Conventional resonant converter circuits, however, are not optimized for high-frequency operation. A new resonant mode dc/dc converter topology exhibits desirable characteristics including zero switching losses, elimination of snubbers, simple control strategy, and circuit operation that is insensitive to parasitics such as diode reverse recovery. Analysis and design techniques are discussed in detail and are experimentally verified with a 150-W prototype converter operating in the frequency range 500 kHz-1 MHz.

An SMR Topology with Suppressed DC Link Components and Predictive Line Current Waveshaping

Abstract: A new switch-mode rectifier (SMR) topology has been developed and presented in this paper. Its advantages over other SMR topologies include: high input power factor, minimum input current distortion, elimination of dc link bus electrolytic capacitors, and minimization of switching stresses of high-frequency inverter stage components.

Nutcracker: An Efficient and Intelligent Channel Spacer

Abstract: A new algorithm for channel spacing is discussed in this paper. In contrast to existing compaction algorithms, we rely on the geometric method and bypass the constraint graph during the whole spacing process. We propose an efficient way to enumerate all possible jogs. Therefore, for the given channel routing topology, our algorithm yields the minimal channel height with the incorporation of contacts sliding and automatic jog insertion. In the final output, only necessary jogs are inserted, and the total wire length is minimized.

Wave Analysis of Noise in Interconnected Multiport Networks

Abstract: The noise performance of multiport networks of arbitrary topology is treated using wave analysis.This approach has advantages over other methods when using computer-aided design programs that are based on scattering parameters. In this paper we discuss the wave representation of noise in two-ports and passive multiports. We indicate bow to compute the noise performance of an arbitrary network and we demonstrate the effectiveness of this approach with an example.

Three-phase inductor fed SMR convertor with high frequency isolation, high power density and improved power factor

Abstract: A novel two stage inductor fed switch mode rectifier (SMR) topology has been developed and is presented in the paper. Its advantages over other SMR topologies include high input power factor, improved reliability, high power density, minimum input line current harmonic distortion, elimination of the input filter AC capacitors and elimination of the DC link capacitor.

A Unified Approach to Local Area Network Interconnection

Abstract: An approach to local area network interconnection is presented Which combines the advances in static interconnection topologies, demand assignment multiple access protocols, and the availability of high-bandwidth fiber optic channels to create a cost-effective structure capable of interconnecting a large number of LAN's with heavy traffic. This approach is independent of the protocol implemented at each LAN. The structure is based on a hypercube topology where each vertex of the graph represents a LAN. Multiple access channels spanning all dimensional axes are used in this scheme. This approach is compared to a topology with direct point-to-point connections between all nodes sharing a common axis. Through the development of the degree, diameter, average distance, cost, and average packet delay, we show that using fewer high-capacity channels, a LAN interconnection network with excellent performance characteristics can be constructed, able to support a large number of LAN's with heavy traffic at a significant reduction in cost over the point-to-point case. The resulting structure has many of the desirable characteristics for static interconnection networks such as high fault tolerance, totally distributed packet routing in the interconnection network, low average distance for good performance, and low degree, resulting in low cost. For the total number of required LAN nodes and the expected amount of internode traffic, the structure is optimized for minimum cost.

Comparison of the square-wave and quasi-resonant topologies

Abstract: The waveforms of a square-wave and a quasi-resonant dc-dc converter are examined in detail so that a comparison between the switching and conduction losses for each topology can be made. Using data from commercially available semiconductor devices, conservative estimates are then given for the switching frequency at which the resonant approach becomes advantageous. The effect of an isolation transformer on this comparison is also addressed.

A method for frequency-domain analysis of switched-capacitor filters

Abstract: In this paper, a new method is proposed for the frequencyresponse evaluations of switched-capacitor networks of any topology. It relies on reducing the z -transform impulse response of the SCN into a rational function form. Closed-form expressions for the coefficients of the rational expansion, as well as its degree, are given. Illustrative examples showing the merits of this new approach over the existing one .are also included.

The Concept and Implementation of Data-Driven Processor Arrays

Abstract: V arious topologies and architectural designs for processor arrays have recently been proposed. These designs include systolic arrays and globally asynchronous wavefront arrays. ' Both array types have a computation front that propagates according to a predetermined control sequence, and consequently these control-driven arrays have proven to be very effective for executing highly regular algorithms like vector and matrix operations. There are, however, many computationally demanding problems that do not exhibit high regularity and may therefore prove unsuitable for these control-driven arrays. Still, many ofthese problems have an inherent parallelism, and it should be possible to exploit this parallelism by means of processor arrays that can provide a high degree of pipelining. In Koren and Silberman,2 a new approach to array design was proposedthat of developing specialized array architectures that would be capable of executing any given algorithm. In this approach, the algorithm is first represented in the form of a dataflow graph (DFG) and is then mapped onto the array. The processing elements (PEs) in the array execute the operations included in the corresponding nodes (or subsets of nodes) of the DFG; regular interconnections ofthese PEs serve as edges of the graph. In general, when an arbitrary algorithm is executed on an array there is no regular propagation of computation fronts. Hence, to speed up the execution of arbitrary algorithms, a more flexible array is needed. Such an array should make possible the generation of new computation fronts and their cancellation at a later time

Comments on "Reliable Loop Topologies for Large Local Computer Networks"

Abstract: We comment on the paper by Raghavendra, Gerla, and Avizienis recently published in this TRANSACTIONS [3]. We point out a different routing strategy leading to a skip distance with diameter roughly √3N as compared to the diameter 2√N from the "optimal" skip distance obtained in that paper.

Optimum Design of Non Linear Power FET Amplifiers

Abstract: In this paper, an efficient approach to optimum design of power amplifiers stages is described. The impedances presented to the FET are optimized independently of the topology chosen for their realization. They are then synthetized by usual methods of linear circuits. The proposed method has been applied to the design of broadband power FET amplifiers. The realizations have given a good correlation between the theoretical and experimental results. Moreover, the method may be used to the optimum design of power FET multipliers.

Equivalent Circuits For High Frequency Transistors

Abstract: topology is determined by physical arguments and two-port characterization techniques. Mathematical functions are determined by physical device modeling or curve fitting to experimental data. The functions can then be analyzed to define a topology. In this manner, for example, it can be shown that the input circuit of an FET can be represented as a series RC circuit and the output network can be represented as a parallel RC circuit. The element values and their relationship to device parameters can be determined by analytic device modeling of the physical structure and the mechanisms responsible for device operation. Once the circuit topology is known the element values can also be extracted from experimental data taken from actual devices over a specified frequency band. The equivalent circuit is generally valid only over the frequency band for which the circuit has been determined. Attempts to extrapolate the response of the circuit beyond the characterized frequency band can produce misleading results, especially for circuits that have been simplified for convenience by removing certain elements. If an equivalent circuit is to be used to predict the upper frequency potential of devices (e.g., to determine ft or fmax) the equivalent circuit must be topologically accurate and based upon device physics. Elements representing the physical processes responsible for device operation must be present. The high frequency operation of four candidate transistors for mm-wave applications is compared in this paper. Physically based equivalent circuits are determined and used to predict high frequency potential. The element values are determined by extraction from measured dc and s-parameter data. The circuits are analyzed to determine the elements that limit high frequency operation. The four transistors investigated are listed in Table I and consist of a Hughes GaAs MESFET, the MIT Lincoln Labs PBT, a TRW AlGaAs/GaAs HEMT, and an Alpha AlGaAs/InGaAs/GaAs pseudomorphic HEMT.

Generation of Connection Matrices for Digital Simulation of Converter Circuits Using the Tensor Approach

Abstract: The tensor approach to simulating converter circuits with time-varying topology depends on the generation of connection matrices which relate the independent variables of the reduced networks resulting from the opening of some switches, to the independent variables of the complete network in which all switches are closed. Thus far, specific procedures for generating the connection matrices for three phase bridge circuits have been developed, but these procedures are not readily extendible to other circuit configurations. This paper describes a general method that has been developed to automatically generate such connection matrices for any drive circuit. Examples on three common ac drive circuits are given to illustrate the method.

Optimum Design of Nonlinear FET Amplifiers

Abstract: In this paper, an efficient approach to the optimum design of power amplifier stages is described. The impedances presented to the FET are optimized independently of the topology chosen for their realization. They are then synthesized by the usual methods of Iinear circuits. The proposed method has been applied to the design of broad-band power FET amplifiers. The realizations have given a good correlation between the theoretical and experimental results. Moreover, the method is being used in the optimum design of power FET multipliers.